This document summarizes some key challenges for digital circuits related to process, voltage, and temperature variations. It discusses techniques to prevent latchup and electrostatic discharge issues in integrated circuits. It also describes simultaneous switching noise that can occur when large numbers of circuits switch simultaneously. The document proposes using adaptive body biasing techniques to compensate for PVT variations and control output slope under different conditions. Simulation results show this approach can adjust rising and falling times of an output buffer for different substrate bias voltage conditions.
LOW VOLTAGE LOW DROPOUT REGULATOR USING CURRENT SPLITTING TECHNIQUEEditor IJMTER
We proposed a low voltage low dropout regulator that converts an input of 1 v to an
output of 0.85-0.5 v with 90-nm CMOS technology. Current splitting technique used to boost the
gain by using an error amplifier. A power noise cancellation mechanism is formed in the rail-to-rail
output stage of the error amplifier, to minimize the size of power MOS transistor. In this paper we
achieve a fast transient response, high power supply rejection, low dropout regulator, low voltage,
and small area. CMOS processes have been used in Large scale integrated circuits like LSI and
microprocessor they have been miniaturized constantly. Taking full advantage of the miniaturization
technology, CMOS linear regulators have become the power management ICs that are widely used in
portable electronics products to realize low profile, low dropout, and low supply current.
Sources of Power Dissipation
Dynamic Power Dissipation
Static Power Dissipation
Power Reduction Techniques
Algorithmic Power Minimization
Architectural Power Minimization
Logic and Circuit Level Power Minimization
Control Logic Power Minimization
System Level Power Management.
Negitive Feedback in Analog IC Design 02 April 2020 Javed G S, PhD
The webinar discusses the topics of negative feedback and its importance across the Analog IC design spectrum. In the talk, we discuss about the variations of feedback (Shunt and Series combinations) and their usage. It has applications in many control circuit design for power management, reference designs, regulator design, noise reduction in the system, gain desensitization and PLL design among many other systems.
And the end of the talk, the audience is expected to understand the need for the feedback and its applications
The paper introduces a multi-pass loop voltage controlled ring oscillator. The proposed structure uses cross-coupled PMOS transistors and replica bias with coarse/fine control signal. The design implemented in TSMC 90 nm CMOS technology, 0.9V power supply with frequency tuning range 481MHz to 4.08GHz and -94.17dBc/Hz at 1MHz offset from 4.08GHz with 26.15mW power consumption.
LOW VOLTAGE LOW DROPOUT REGULATOR USING CURRENT SPLITTING TECHNIQUEEditor IJMTER
We proposed a low voltage low dropout regulator that converts an input of 1 v to an
output of 0.85-0.5 v with 90-nm CMOS technology. Current splitting technique used to boost the
gain by using an error amplifier. A power noise cancellation mechanism is formed in the rail-to-rail
output stage of the error amplifier, to minimize the size of power MOS transistor. In this paper we
achieve a fast transient response, high power supply rejection, low dropout regulator, low voltage,
and small area. CMOS processes have been used in Large scale integrated circuits like LSI and
microprocessor they have been miniaturized constantly. Taking full advantage of the miniaturization
technology, CMOS linear regulators have become the power management ICs that are widely used in
portable electronics products to realize low profile, low dropout, and low supply current.
Sources of Power Dissipation
Dynamic Power Dissipation
Static Power Dissipation
Power Reduction Techniques
Algorithmic Power Minimization
Architectural Power Minimization
Logic and Circuit Level Power Minimization
Control Logic Power Minimization
System Level Power Management.
Negitive Feedback in Analog IC Design 02 April 2020 Javed G S, PhD
The webinar discusses the topics of negative feedback and its importance across the Analog IC design spectrum. In the talk, we discuss about the variations of feedback (Shunt and Series combinations) and their usage. It has applications in many control circuit design for power management, reference designs, regulator design, noise reduction in the system, gain desensitization and PLL design among many other systems.
And the end of the talk, the audience is expected to understand the need for the feedback and its applications
The paper introduces a multi-pass loop voltage controlled ring oscillator. The proposed structure uses cross-coupled PMOS transistors and replica bias with coarse/fine control signal. The design implemented in TSMC 90 nm CMOS technology, 0.9V power supply with frequency tuning range 481MHz to 4.08GHz and -94.17dBc/Hz at 1MHz offset from 4.08GHz with 26.15mW power consumption.
Low Power VLSI design architecture for EDA (Electronic Design Automation) and Modern Power Estimation, Reduction and Fixing technologies including clock gating and power gating
Design of Ota-C Filter for Biomedical ApplicationsIOSR Journals
Abstract-This paper presents design of operational transconductance amplifier is to amplify the ECG signal
having low frequency of 300Hz, with the supply voltage of 0.8v. To reduce the power dissipation of 779nW, by
using fifth order low pass filter. The OTA-C filter is to eliminate noise voltage and increases the reliability of
the system. A chip is fabricated in a 0.18μm CMOS process is simulated and measured to validate the system
performance using HSPICE.
The Analysis of Dead Time on Switching Loss in High and Low Side MOSFETs of Z...IDES Editor
This work is about the analysis of dead time variation
on switching losses in a Zero Voltage Switching (ZVS)
synchronous buck converter (SBC) circuit. In high frequency
converter circuits, switching losses are commonly linked with
high and low side switches of SBC circuit. They are activated
externally by the gate driver circuit. The duty ratio, dead time
and resonant inductor are the parameters that affect the
efficiency of the circuit. These variables can be adjusted for
the optimization purposes. The study primarily focuses on
varying the settings of input pulses of the MOSFETs in the
resonant gate driver circuit which consequently affects the
performance of the ZVS synchronous buck converter circuit.
Using the predetermined inductor of 9 nH, the frequency is
maintained at 1 MHz for each cycle transition. The switching
loss graph is obtained and switching losses for both S1 and S2
are calculated and compared to the findings from previous
work. It has shown a decrease in losses by 13.8 % in S1. A dead
time of 15 ns has been determined to be optimized value in
the SBC design.
Design and Simulation of Low Noise Amplifiers at 180nm and 90nm TechnologiesIJERA Editor
With continued process scaling, CMOS has become a viable technology for the design of high-performance low noise amplifiers (LNAs) in the radio frequency (RF) regime. This thesis presents design and simulation of LNA at 180nm and 90nm technology. The LNA function is used to amplify signals without adding noise. The work is done on Cadence Virtuoso platform and the performance parameters like transient response and Noise figure are simulated and plotted. A supply voltage of just 5mV is used here. The noise figure at 180nm is found to be 259.722mdB at 1.04502GHz and The noise figure at 90nm is found to be 183.21mdB at 1.157GHz. 1.04502GHz and 1.157GHz are the peak frequency obtained from the frequency response of the Low noise amplifier. It is observed that the noise figure varies in each technology.
FAST TRANSIENT RESPONSE LOW DROPOUT VOLTAGE REGULATORijseajournal
This paper presents the design of Low Drop-Out (LDO) voltage regulator has fast transient response and which exploits a few current else low quiescent current in the operational amplifier PMOS type. We use band-gap reference for eliminate the temperature dependence. The proposed LDO voltage regulator implemented in 0.18-μm CMOS technology, we use Folded cascode CMOS amplifiers high performance in the stability , provide fast transient response which explains a fast settling, the LDO itself should provide in the output regulator voltages at t equal 2ps with transient variation of the voltage less than 170mV. High accuracy in the DC response terms, the simulation results show that the accuracy of the output regulator voltages is 1.54±0.009V, and power consumption of 1.51 mW.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Temperature analysis of lna with improved linearity for rf receivereSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Temperature analysis of lna with improved linearity for rf receivereSAT Journals
Abstract In this paper we are fully integrated 5.5 GHz high-linearity low noise amplifier (LNA) is designing using post-linearization technique, in sub-120nm & sub-70nm technology. It developed using cascode amplifier with inductors. RC linearization circuit is designed to improve the linearity of the design. Cascode LNA circuit is designed for linearity improvement. In this work Temperature analysis is carried out for LNA circuit performance improvement fully integrated 5.5 GHz high-linearity low noise amplifier (LNA) is designing using post-linearization technique, in sub-120nm & sub-70nm technology. Temperature stability of the circuit is analysed for different temperature ranges our results prove that the proposed LNA design achieve high gain with good linearity. Although power dissipation of the circuit is high, good temperature stability is achieved. Temperature stability of the circuit is analysed for different temperature ranges our results prove that the proposed LNA design achieve high gain with good linearity. Although power dissipation of the circuit is high, we are able to achieve good temperature stability. The Low Noise Amplifier is a special type of electronic amplifier used in communication systems which amplifies very weak signals captured by an antenna. Keywords: Linearity improvement LNA circuit, DSCH and Microwind software.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Low Power VLSI design architecture for EDA (Electronic Design Automation) and Modern Power Estimation, Reduction and Fixing technologies including clock gating and power gating
Design of Ota-C Filter for Biomedical ApplicationsIOSR Journals
Abstract-This paper presents design of operational transconductance amplifier is to amplify the ECG signal
having low frequency of 300Hz, with the supply voltage of 0.8v. To reduce the power dissipation of 779nW, by
using fifth order low pass filter. The OTA-C filter is to eliminate noise voltage and increases the reliability of
the system. A chip is fabricated in a 0.18μm CMOS process is simulated and measured to validate the system
performance using HSPICE.
The Analysis of Dead Time on Switching Loss in High and Low Side MOSFETs of Z...IDES Editor
This work is about the analysis of dead time variation
on switching losses in a Zero Voltage Switching (ZVS)
synchronous buck converter (SBC) circuit. In high frequency
converter circuits, switching losses are commonly linked with
high and low side switches of SBC circuit. They are activated
externally by the gate driver circuit. The duty ratio, dead time
and resonant inductor are the parameters that affect the
efficiency of the circuit. These variables can be adjusted for
the optimization purposes. The study primarily focuses on
varying the settings of input pulses of the MOSFETs in the
resonant gate driver circuit which consequently affects the
performance of the ZVS synchronous buck converter circuit.
Using the predetermined inductor of 9 nH, the frequency is
maintained at 1 MHz for each cycle transition. The switching
loss graph is obtained and switching losses for both S1 and S2
are calculated and compared to the findings from previous
work. It has shown a decrease in losses by 13.8 % in S1. A dead
time of 15 ns has been determined to be optimized value in
the SBC design.
Design and Simulation of Low Noise Amplifiers at 180nm and 90nm TechnologiesIJERA Editor
With continued process scaling, CMOS has become a viable technology for the design of high-performance low noise amplifiers (LNAs) in the radio frequency (RF) regime. This thesis presents design and simulation of LNA at 180nm and 90nm technology. The LNA function is used to amplify signals without adding noise. The work is done on Cadence Virtuoso platform and the performance parameters like transient response and Noise figure are simulated and plotted. A supply voltage of just 5mV is used here. The noise figure at 180nm is found to be 259.722mdB at 1.04502GHz and The noise figure at 90nm is found to be 183.21mdB at 1.157GHz. 1.04502GHz and 1.157GHz are the peak frequency obtained from the frequency response of the Low noise amplifier. It is observed that the noise figure varies in each technology.
FAST TRANSIENT RESPONSE LOW DROPOUT VOLTAGE REGULATORijseajournal
This paper presents the design of Low Drop-Out (LDO) voltage regulator has fast transient response and which exploits a few current else low quiescent current in the operational amplifier PMOS type. We use band-gap reference for eliminate the temperature dependence. The proposed LDO voltage regulator implemented in 0.18-μm CMOS technology, we use Folded cascode CMOS amplifiers high performance in the stability , provide fast transient response which explains a fast settling, the LDO itself should provide in the output regulator voltages at t equal 2ps with transient variation of the voltage less than 170mV. High accuracy in the DC response terms, the simulation results show that the accuracy of the output regulator voltages is 1.54±0.009V, and power consumption of 1.51 mW.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Temperature analysis of lna with improved linearity for rf receivereSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Temperature analysis of lna with improved linearity for rf receivereSAT Journals
Abstract In this paper we are fully integrated 5.5 GHz high-linearity low noise amplifier (LNA) is designing using post-linearization technique, in sub-120nm & sub-70nm technology. It developed using cascode amplifier with inductors. RC linearization circuit is designed to improve the linearity of the design. Cascode LNA circuit is designed for linearity improvement. In this work Temperature analysis is carried out for LNA circuit performance improvement fully integrated 5.5 GHz high-linearity low noise amplifier (LNA) is designing using post-linearization technique, in sub-120nm & sub-70nm technology. Temperature stability of the circuit is analysed for different temperature ranges our results prove that the proposed LNA design achieve high gain with good linearity. Although power dissipation of the circuit is high, good temperature stability is achieved. Temperature stability of the circuit is analysed for different temperature ranges our results prove that the proposed LNA design achieve high gain with good linearity. Although power dissipation of the circuit is high, we are able to achieve good temperature stability. The Low Noise Amplifier is a special type of electronic amplifier used in communication systems which amplifies very weak signals captured by an antenna. Keywords: Linearity improvement LNA circuit, DSCH and Microwind software.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
CMOS Analog IC design by Dr GS Javed - Refresher Course - Batch 1Javed G S, PhD
Topics covered in the course
1. DC Biasing of the circuits
2. Circuits for reference voltage and current generation
-Voltage Regulator
-BGR
-LDO
-V-to-I
3. Precision Current References
4. Opamp design for Analog to digital converters
- OTA
- Buffer
- Unity Feedback OTA
- Layout design strategies – 2stage opamp + CMFB
5. Sense and Return mechanisms in Feedback circuits
- Current and Voltage circuits
6. Sub-Threshold Conduction
- Low voltage Operation
7. ADC Design and Simulation
-Near Nyquist performance of Opamp for ADC Circuits
-Spectral Analysis and No. of FFT Points for simulation
-Simulation time for performance
-Resistors – their variation and Calibration
-Switch design for S/H
-CDAC
8. On-Chip Inductors
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Design of an ADC using High Precision Comparator with Time Domain Offset Canc...IJTET Journal
Abstract— The comparator is a combinational logic circuit that plays an important role in the design of analog to digital converter. One of its most important properties is its input referred offset. When mismatches are present in a dynamic comparator, due to internal positive feedback and transient response, it is always challenging to analytically predict the input-referred random offset voltages since the operating points of transistors are time varying. To overcome the offset effect a novel time-domain bulk-tuned offset cancellation method is applied to a low power dynamic comparator. Using this comparator in analog to digital converter it does not increase the power consumption, but at the same time the delay is reduced and the speed is increased. The comparator is designed using the 250-nm CMOS technology in mentor graphics tool. Operating at a supply voltage of 5v and clock frequency 100MHZ, the comparator together with the offset cancellation circuitry dissipates 335.49nW of power and dissipates 1.027uW of power for comparator without offset cancellation circuit. The simulation result indicates that the offset cancellation circuitry consumes negligible power and it does not draw any static current. Using this high precision offset cancelled comparator in the analog to digital converter circuit the static power consumption is less and it is able to work under very low supply voltage.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Power Gating Based Ground Bounce Noise ReductionIJERA Editor
As low power circuits are most popular the decrease in supply voltage leads to increase in leakage power with respect to the technology scaling. So for removing this kind of leakages and to provide a better power efficiency many power gating techniques are used. But the leakage due to ground connection to the active part of the circuit is very high rather than all other leakages. As it is mainly due to the back EMF of the ground connection it was called it as ground bounce noise. To reduce this noise different methodologies are designed. In this paper the design of such an efficient technique related to ground bounce noise reduction using power gating circuits and comparing the results using DSCH and Microwind low power tools. In this paper the analysis of adders such as full adders using different types of power gated circuits using low power VLSI design techniques and to present the comparison results between different power gating methods.
LOW POWER SI CLASS E POWER AMPLIFIER AND RF SWITCH FOR HEALTH CAREieijjournal1
This research was to design a 2.4 GHz class E Power Amplifier (PA) for health care, with 0.18um
Semiconductor Manufacturing International Corporation CMOS technology by using Cadence software.
And also RF switch was designed at cadence software with power Jazz 180nm SOI process. The ultimate
goal for such application is to reach high performance and low cost, and between high performance and
low power consumption design. This paper introduces the design of a 2.4GHz class E power amplifier and
RF switch design. PA consists of cascade stage with negative capacitance. This power amplifier can
transmit 16dBm output power to a 50Ω load. The performance of the power amplifier and switch meet the
specification requirements of the desired.
LOW POWER SI CLASS E POWER AMPLIFIER AND RF SWITCH FOR HEALTH CAREieijjournal
This research was to design a 2.4 GHz class E Power Amplifier (PA) for health care, with 0.18um
Semiconductor Manufacturing International Corporation CMOS technology by using Cadence software.
And also RF switch was designed at cadence software with power Jazz 180nm SOI process. The ultimate goal for such application is to reach high performance and low cost, and between high performance and low power consumption design. This paper introduces the design of a 2.4GHz class E power amplifier and
RF switch design. PA consists of cascade stage with negative capacitance. This power amplifier can
transmit 16dBm output power to a 50Ω load. The performance of the power amplifier and switch meet the specification requirements of the desired.
LOW POWER SI CLASS E POWER AMPLIFIER AND RF SWITCH FOR HEALTH CAREieijjournal
This research was to design a 2.4 GHz class E Power Amplifier (PA) for health care, with 0.18um
Semiconductor Manufacturing International Corporation CMOS technology by using Cadence software.
And also RF switch was designed at cadence software with power Jazz 180nm SOI process. The ultimate
goal for such application is to reach high performance and low cost, and between high performance and
low power consumption design. This paper introduces the design of a 2.4GHz class E power amplifier and
RF switch design. PA consists of cascade stage with negative capacitance. This power amplifier can
transmit 16dBm output power to a 50Ω load. The performance of the power amplifier and switch meet the
specification requirements of the desired
LOW POWER SI CLASS E POWER AMPLIFIER AND RF SWITCH FOR HEALTH CAREieijjournal
This research was to design a 2.4 GHz class E Power Amplifier (PA) for health care, with 0.18um
Semiconductor Manufacturing International Corporation CMOS technology by using Cadence software.
And also RF switch was designed at cadence software with power Jazz 180nm SOI process. The ultimate
goal for such application is to reach high performance and low cost, and between high performance and
low power consumption design. This paper introduces the design of a 2.4GHz class E power amplifier and RF switch design. PA consists of cascade stage with negative capacitance. This power amplifier can transmit 16dBm output power to a 50Ω load. The performance of the power amplifier and switch meet the specification requirements of the desired.
Low Power SI Class E Power Amplifier and Rf Switch for Health Careieijjournal1
This research was to design a 2.4 GHz class E Power Amplifier (PA) for health care, with 0.18um Semiconductor Manufacturing International Corporation CMOS technology by using Cadence software. And also RF switch was designed at cadence software with power Jazz 180nm SOI process. The ultimate goal for such application is to reach high performance and low cost, and between high performance and low power consumption design. This paper introduces the design of a 2.4GHz class E power amplifier and RF switch design. PA consists of cascade stage with negative capacitance. This power amplifier can transmit 16dBm output power to a 50Ω load. The performance of the power amplifier and switch meet the specification requirements of the desired.
High performance novel dual stack gating technique for reduction of ground bo...eSAT Journals
Abstract The development of digital integrated circuits is challenged by higher power consumption. The combination of higher clock speeds, greater functional integration, and smaller process geometries has contributed to significant growth in power density. Today leakage power has become an increasingly important issue in processor hardware and software design. So to reduce the leakages in the circuit many low power strategies are identified and experiments are carried out. But the leakage due to ground connection to the active part of the circuit is very higher than all other leakages. As it is mainly due to the back EMF of the ground connection we are calling it as ground bounce noise. To reduce this noise, different methodologies are designed. In this paper, a number of critical considerations in the sleep transistor design and implementation includes header or footer switch selection, sleep transistor distribution choices and sleep transistor gate length, width and body bias optimization for area, leakage and efficiency. Novel dual stack technique is proposed that reduces not only the leakage power but also dynamic power. The previous techniques are summarized and compared with this new approach and comparison of both the techniques is done with the help of Digital Schematic( DSCH ) and Microwind low power tools. Stacking power gating technique has been analyzed and the conditions for the important design parameters (Minimum ground bounce noise) have been derived. The Monte-Carlo simulation is performed in Microwind to calculate the values of all the needed parameters for comparison. Index Terms: Ground Bounce Noise ,Power gating schemes ,Static power dissipation, Dynamic power dissipation, Power gating parameters, Sleep transistors, Novel dual stack approach, Transistor leakage power
PARASITIC-AWARE FULL PHYSICAL CHIP DESIGN OF LNA RFIC AT 2.45GHZ USING IBM 13...Ilango Jeyasubramanian
• Analyzed and designed a single stage cascoded LNA with Q-based calculation for desired input matching, output matching, power gain, IIP3 and Noise figure, including all the parasitics in the on-chip and off-chip components using SpectreRF simulations.
• Synthesized the LNA layout for on-chip components with spiral inductor, MOS capacitor, MIM capacitor and Bond-pads with ESD protections.
• Our LNA exhibited a noise figure of 1.23dB, linear gain of 18.54 dB, IIP3 of -4.60dbm, S11 of -31.11db, S22 of -24.91db with the operating range between 2.4-2.5GHZ along with 10% variation tolerance.
Optimization of Threshold Voltage for 65nm PMOS Transistor using Silvaco TCAD...
Bt31482484
1. Mrs. Sonika, Mr. Anshuman Singh / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 1, January -February 2013, pp.482-484
Adaptive body biasing process compensation techniques for
Digital circuit
Mrs. Sonika*, Mr. Anshuman Singh**
*(lecturer in GNIT ,Greater Noida)
** (Assistant professor in NIET,Greater Noida)
ABSTRACT
The present invention relates generally drain coupled with functional failure, parametric failure
to the integrated circuits(ICs) & in particular to and/or device destruction.latch-up is an-undesirable
process, voltage & temperature(PVT) variations but controllable phenomenon.
in an ICs. PVT variations are critical factor that This Latchup may be prevented in two basic ways:•
hamper performance of Ics forexample PVT Latchup resistant CMOS process• Layout
variations can result in a change in setup &hold technique.[16]
times of synchronous circuits. Different
components of asynchronous circuit are driven 2.2 ELCTROSTATIC DISCHARGE
by a common system clock. Therefore any Electrostatic discharge is a subclass of the
change in setup or hold times corresponding to failure causes known as electrical overstress (EOS).
any one component causes an erroneous circuit The ESD events have four major stages: (1) charge
ouput.one technique to reduce PVT variations in generation (2) charge transfer (3) charge conduction
a circuit isbased on sensing the variations in the (4) charge induced damage.There are two basic
circuit &then taking the appropriate action to ways that circuits are protected: 1) Improve the
reducethese variations. unprotected elements 2) Add additional circuit
elements to divert the charge and clamp the voltage
Keywords: PVT compensation,Adaptive body most circuits use a combination of these three
biasing. techniques.
INTRODUCTION 2.3 ELECTROMIGRATION
In this era of ultra large scale integration Electro migration refers to the gradual
for a chip to be efficient , the I/O structures requires displacement of the metal atoms of a conductor as a
the circuit design expertise along with the result of the current flowing through that conductor.
knowledge of processes in detail. It is the I/O Electromigration can be prevented by:1) Proper
element which finally interfaces with the core signal design of the device 2) Good selection and
to the off chip environment. The i/o cells are placed deposition of the passivation
on the periphery of chip along with supply cells,
corners & fillers. The supply for the core is 2.4 SIMULTANEOUS SWITCHING NOISE
separated from supply of I/O’s because the noise (SSN):
that arise at the switching of the large output buffer This Switching Noise is called Simultaneous
.PAD is basically a sandwitch of various metal Switching Noise (SSN).SSN is studied byFeiYuan, Ph.D,
layers from where user can either receive the output P.Eng[8] and discussed lot of methods to reduce
or apply the input. The present work describes some it.SSN Reduction Techniques-Separate power and
of the basic design considerations for I/O pads. ground pins and pads for analog and digital circuits
Wherever possible, design option for smaller area whenever possible.
,low power &high speed has been comprehensively Corner pads will have long bond wire and there
dealt with. The emphasis is on having an idea of the inductance is very high.
various circuit elements involved in an I/O library
&an understanding of the behavior & their 3. DESIGN SPECIFICATION
performance & finally an optimized design is The specifications are a set of conditions
proposed for 3.3V tolerant bidirectional I/O. and functionality which are required by the
customer. For a designer it is necessary to observe
2. I/Os: problems & solutions specifications properly and then provide optimized
Main problems occur in I/Os are solution. The design must be ensured to work under
Latchup,Electrostatic discharge, electromigration& the process, temperature and Voltage variation.Here
simultaneous switching noise. by the design presented ensured to work under type
process, temperature variation from 0°C to 50°C ,
2.1 LATCH UP core supply variation from 1.1 to 1.2 and VDDE
Latch-up is a failure mechanism of CMOS variation from 3.0 V to 3.6 V. Other specifications
integrated circuits characterized by excessive current are delay, frequency of operation, VIL and VIH
482 | P a g e
2. Mrs. Sonika, Mr. Anshuman Singh / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 1, January -February 2013, pp.482-484
levels. These specifications are defined separately maximum operational frequency and the maximum
for the input and output path. leakage power,in the presence of within die(WID)
variations
3.1 DESIGN OPTIMIZATION
The designer has to ensure that the design 5. RESULT & ANALYSIS
is efficient as well as cost effective. The cost of Output Buffer output slope can be adjusted
production of a chip is much more expensive then to through compensation technique. Either by change in
design. It is necessary to optimize area so that compensation codes or by adjusting proper substrate
production in each batch increases thereby reduction biasing voltage. Here in this project I am trying to
in cost. Power consumption is also very important adjust output slope which is affected by process
issue. There are some important parameters among variation through substrate biasing control
which we have to compromise during the design: mechanism. Adaptive biasing technique used to
Area, power consumption, delay, speed, etc. Hence control the output slope of buffer. Hereby we are
by taking care of all these parameters we have to able to design output path having a compensated
provide an optimized design. output slope under all PVT conditions. Using
feedback signals from I/O PAD slew rate control is
3.1.1 DECISION OF W/L RATIO also achieved. LTSPICE simulation results are
Area of a chip is basically determined by shown here.
the (W/L) ratio of transistors. we have taken Wave SUBP=1.8 SUBP=2.1 SUBP=1.
transistor model from the Linear Technology 130nm form V V 5V
technology and then with suitable biasing simulated P
the ckt and plots are obtained. According to Buffe
application specific, we will decide the lengths if r-
there is the issue of leakage current then we have to Risin 61.159ps 60.281ps 63.348ps
choose the length according to the plot of leakage g
current wrt length. Wave
form
3.1.2 SPEEDS VERSUS AREA TRADE-OFF P
The speed of a circuitry is determined by Buffe
the switching response of the circuit. The rise time r-
and fall time of output determines how fast the Fallin 90.354ps 78.139ps 116.5ps
circuit is operating. Faster the circuit lesser time it g
will take to settle. The basic cause of the rise time Wave
and fall time is the parasitic offered by the circuit. form
SUBN=0.3 SUBN=-
3.1.3 DESIGN AND OPTIMIZATION SUBN=0.0
V 0.3V
TECHNIQUES N
The physical design is a design process Buffe
which is an intermediate between circuit design and r-
circuit on silicon. During the physical design we use Risin 406.7ps 388.06ps 416.79ps
different polygon layers which represent the g
different layers on the silicon. By using these layers Wave
a schematic is transformed into layout which is used form
later for mask preparation during fabrication N
process. So layout is a heart of all over the circuit Buffe
design because it transfers the circuit into real r-
world. After the layout design we check it for Fallin 34.236ps 32.779ps 39.042ps
certain rules known as DRC (Design Rule Check) g
and LVS (Layout versus Schematic) check. When Wave
our layout passesboth these checks then we extract form
netlist from the layout. By simulating this
postlayoutnetlist we verify our results, the dc results N PRE-BUFFER PULSE
will remain same but there may be some changes in
transient results due to the parasitics .
4. ADAPTIVE BODY BIASING
Adaptive Body Bias (ABB) involves
recovering dies impacted by process variations
through post silicon tuning.ABB is a dynamic
control technique used to tighten the distribution of
483 | P a g e
3. Mrs. Sonika, Mr. Anshuman Singh / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 1, January -February 2013, pp.482-484
N Pre-buffer Rise References
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[4] C.Duvvury and A.Amerasekera,” ESD
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[5] Canh Q Tran,Hiroshi Kawaguchi and
Takayasu Sakurai .” Low Power High
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Output Waveform Rising [6] Craig Brunty and Laszlo Gal ,” Optimum
Tapered Buffer” IEEEJSSC Vol 27 Jan
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[7] C.R. Parthasarthy,” Investigation of Slew
Rate Control in the buffersof HCMOSS I/O
library,” Library development
group,Central R&D ,ST Microelectronics
Gr.Noida.
[8] FeiYuan ,Ph.D,P.Engg,” Simultaneous
Switching Noise(SSN),” Department of
Electrical and computer
Engg,RyersonUniversity,Toronto,Canada.
[9] Jose Rocha,MarcelinoSantos,J.MDores
Output Waveform Falling Costa and Floriberto Lima,” High Voltage
Tolerent Level Shifters and Logic Gates in
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[10] J.S.Shor,Y.Afek and E.Engel,”I/O buffer
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[11] J.E.Vinson and J.J.Liou,” Electrostatic
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CONCLUSION:
Due to change in Substrate Voltage Slope of
the output Curve changesIncrease inSubstrate Bias
Voltage Decrease in Rise (tr) and Fall (tf) time of
output waveform. The Complete design of the
compensated circuit for an I/O buffer is presented
with the cost of area and process mask generation
time. The system will work at hundreds of MHz and
presents same quality of output signal and hence
reduces the noise encounters due to change in
process design.
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