The document discusses the design of an energy efficient carry save adder using asynchronous adiabatic logic. It first discusses existing work on using double pass transistor logic with asynchronous adiabatic logic to design an energy efficient full adder cell. It then proposes using a carry save adder which can add 3 n-bit numbers using only 2 numbers of additions, reducing delay and improving performance. The document discusses the design of a static energy recovery full adder cell and use of double pass transistor logic to avoid signal degradation. It also provides background on asynchronous adiabatic logic which aims to reduce power dissipation by reusing stored energy.

1. Asynchronous Design of Energy Efficient
Carry Save Adder
Abstract:
Asynchronous circuits are often presented as a means to achieve low power operation. We
investigate their suitability for lowenergy applications, where long battery life and delay
tolerance is the principal design goal, and where performance is not a critical requirement.
Asynchronous adiabatic logic (AAL) is a novel lowpower design technique which combines
the energy saving benefits of asynchronous systems with adiabatic benefits. In this paper,
energy efficient full adder cell using double pass transistor with asynchronous adiabatic logic
(DPTAAL) is investigated. Asynchronous adiabatic circuits are very low power circuits to
preserve energy for reuse, which reduces the amount of energy drawn directly from the
power supply. In this work, a full adder cell using DPTAAL is designed and simulated, which
exhibits less energy and reliable logical operations. To improve the circuit performance at
reduced voltage level, double pass transistor logic (DPL) is introduced. In proposed we used
carry save adder A carry-save is a type of digital adder used in computer micro architecture to
compute the sum of three or more n-bit numbers in binary. It differs from other digital adders
in that it outputs two numbers of the same dimensions as the inputs, one which is a sequence
of partial sum bits and another which is a sequence of carry bits.
EXISTING SYSTEM:
In existing paper, energy efficient full adder cell using double pass transistor with
asynchronous adiabatic logic (DPTAAL) is investigated. Asynchronous adiabatic circuits are
very low power circuits to preserve energy for reuse, which reduces the amount of energy
drawn directly from the power supply. In this work, a full adder cell using DPTAAL is
designed and simulated, which exhibits less energy and reliable logical operations. To
improve the circuit performance at reduced voltage level, double pass transistor logic (DPL)
is introduced.
PROPOSED SYSTEM

2. In proposed we use carry save adder, The carry-save adder [11][12]reduces the addition of 3
numbers to the addition of 2 numbers. The propagation delay is 3 gates regardless of the
number of bits. The carry-save unit consists of n full adders, each of which computes a single
sum and carries bit based solely on the corresponding bits of the three input numbers. The
entire sum can then be computed by shifting the carry sequence left by one place and
appending a 0 to the front (most significant bit) of the partial sum sequence and adding this
sequence with RCA produces the resulting n + 1-bit value. This process can be continued
indefinitely, adding an input for each stage of full adders, without any intermediate carry
propagation. These stages can be arranged in a binary tree structure, with cumulative delay
logarithmic in the number of inputs to be added, and invariant of the number of bits per input.
The main application of carry save algorithm is, well known for multiplier architecture is
used for efficient CMOS implementation of much wider variety of algorithms for high speed
digital signal processing .CSA applied in the partial product line of array multipliers will
speed up the carry propagation in the array.
FULL ADDER
Static Energy-Recovery Full Adder As an initial step toward designing low power arithmetic
circuit modules, we designed a Static Energy Recovery Full adder (SERF) cell module
illustrated in Figure 4. The cell uses only 10 transistors and it does not need inverted inputs.
The design was inspired by the XNOR gate full adder design. In non-energy recovery design
the charge applied to the load capacitance during logic level high is drained to ground during
the logic level low. It should be noted that the new SERF adder has no direct path to the
ground. The elimination of a path to the ground reduces power consumption, removing the
Psc variable (product of Isc and voltage) from the total power equation. The charge stored at
the load capacitance is reapplied to the control gates. The combination of not having a direct
path to ground and the re-application of the load charge to the control gate makes the energy

3. recovering full adder an energy efficient design. To the best of our knowledge this new
design has the lowest transistor count for the complete realization of a full adder.
DPL
The basic difference of pass transistor logic compared to the CMOS logic style is that the
source side of the logic transistor networks is connected to some input signals instead of the
power lines. In the Double Pass Transistor Logic (DPL) style both NMOS and PMOS logic
networks are used in parallel. Pass transistor logic is attractive as fewer transistors are needed
to implement important logic functions, smaller transistors and smaller capacitances are
required, and it is faster than conventional CMOS. However, the pass transistor gates
generate degraded signals, which slow down signal propagation. This situation will be more
critical when the output signals should be propagated to next stage as is the case for the carry
gate in ripple carry adder. To avoid this signal degradation, inverters are added in the outputs
of the circuit.
DPTAAL

4. ADIABATIC LOGIC DESIGN
“Adiabatic” is a term of Greek origin which spent most of its history related with classical
thermodynamics. It refers to a system in which a transition occurs without energy (usually in
the form of heat) being either lost to or gained from the system. In the context of electronic
systems, rather than heat, electronic charge is preserved. Adiabatic logic is viewed on issues
related with the thermodynamics of computation. By considering this branch of physics that
usually looks at mechanical engines and applying it to computing engines, research areas
such as reversible computation as well as adiabatic logic have been developed. By moving to
a computing paradigm that is reversible, energy can be reprocessed from a computing engine,
and reused to perform further calculations. This style of logical approach differs from CMOS
circuits, which dissipate energy during switching. There are some classical approaches to
reduce the dynamic power such as reducing supply voltage, decreasing physical capacitance
and reducing switching activity. These techniques are not fit enough to meet today’s power
requirement. However, most research has focused on building adiabatic logic, which is a

5. promising design for low power applications. Adiabatic logic works with the concept of
switching activities which reduces the power by giving stored energy back to the supply.
Thus, the term adiabatic logic is used in low-power VLSI circuits which implements
reversible logic. In this, the main design changes are focused in power clock which plays the
vital role in the principle of operation. Each phase of the power clock gives user to achieve
the following major design rules for the adiabatic circuit design.
In recent years, there is a huge demand for low power and low noise digital circuits motivated
by VLSI designers to introduce new methods to the design of low power VLSI circuits. There
are some classical approaches to reduce the dynamic power such as reducing supply voltage,
decreasing physical capacitance and reducing switching activity. These techniques are not fit
enough to meet today’s power requirement. However, most research has focused on building
adiabatic logic, which is a promising design for low power applications. Adiabatic logic
works with the concept of switching activities which reduces the power by giving stored
energy back to the supply. Thus, the term adiabatic logic is used in low-power VLSI circuits
which implements reversible logic. In this, the main design changes are focused in power
clock which plays the vital role in the principle of operation. Each phase of the power clock
gives user to achieve the two major design rules for the adiabatic circuit design.
In this work, Asynchrobatic Logic is presented. It is a novel low-power design style that
combines the energy saving benefits of asynchronous logic and adiabatic logic to produce
systems whose power dissipation is reduced in several different ways. The term
“Asynchrobatic” is a new word that can be used to describe these types of systems, and is
derived from the concatenation and shortening of Asynchronous, Adiabatic Logic. This thesis
introduces the concept and theory behind Asynchrobatic Logic. It first provides an
introductory background to both underlying parent technologies (asynchronous logic and
adiabatic logic). The background material continues with an explanation of a number of
possible methods for designing complex data-path cells used in the adiabatic data-path.
Asynchrobatic Logic is then introduced as a comparison between asynchronous and
Asynchrobatic buffer chains, showing that for wide systems, it operates more efficiently.
Two more-complex sub-systems are presented, firstly a layout implementation of the
substitution boxes from the Twofish encryption algorithm, and secondly a front-end only
(without parasitic capacitances, resistances) simulation that demonstrates a functional system
capable of calculating the Greatest Common Denominator (GCD) of a pair of 16-bit unsigned

6. integers, which under typical conditions on a 0.35µm process, executed a test vector
requiring twenty-four iterations in 2.067µs with a power consumption of 3.257nW. These
examples show that the concept of A synchrobatic Logic has the potential to be used in real-
world applications, and is not just theory without application. At the time of its first
publication in 2004, A synchrobatic Logic was both unique and ground-breaking, as this was
the first time that consideration had been given to operating large-scale adiabatic logic in an
asynchronous fashion, and the first time that Asynchronous Stepwise Charging (ASWC) had
been used to drive an adiabatic data-path.
CARRY SAVE ADDER
Carry save adder is used to compute sum ofthree or more n-bit binary numbers. Carrysave
adder is same as a full adder. The carry-save adder reduces the addition
of 3numbers to the addition of 2 numbers. The carry-save unit consists of ‘n’ full
adders,each of which computes a single sum andcarry bit, based on the corresponding bitsof
the three input numbers. The entiresum can then be computed by shiftingthe carry sequence
left by one place andappending a 0 to the front of the partialsum sequence. The figure, given
here showsthe sum of two 32-bit binary numbers, so 32full adders are used at first stage. Let
X andY are two 32-bit numbers and produces partial sum and carry as S and C as shown
inthe following example:Si = Xi xor YiCi = Xi and YiThe final addition is then computed
as:1. Shifting the carry sequence C left by one place.2. Placing a 0 to the front (MSB) of
the partial sum sequence S.3. Finally, a ripple carry adder is used to add these two together
and computing the resulting sum.

9. Computation Flow of Carry Save Adder.
Again, to add three numbers (Let X ,Y ,Z)the process will be like :X + Y + Z = C + S, where
C is carry and Sis the sum.
IV.
CONCLUSION:
In this paper we have presented a novel methodology for designing energy efficient
full adder cell using double pass transistor with asynchronous adiabatic logic (DPTAAL).
The performance of this design is compared with the conventional logic designs. It is
observed that for frequencies between 100MHz to 200MHz, asynchronous adiabatic full
adder cell consume less energy than the conventional quasi-adiabatic families of cell designs.
Thisapproach confirms the feasibility of asynchronous adiabatic full adder cells in low power
computing applications.