IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Adiabatic Logic Based Low Power Carry Select Adder for future TechnologiesIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
This document proposes a new mixed-style architecture for reducing power in multipliers. It combines a traditional Wallace tree-based part with a bypass array-based part. Simulations show the mixed architecture offers up to a 6.5x improvement in delay-power product compared to traditional array and Wallace tree multipliers. The mixed style exploits low power benefits of bypassing in arrays and performance benefits of Wallace trees.
Design of a Low Power Combinational Circuit by using Adiabatic LogicIJERA Editor
A novel low power and Positive Feedback Adiabatic Logic (PFAL) combinational low power circuit is presented in this paper. The power consumption and general characteristics of the PFAL combinationallow power circuit arethen compared against two combinational low power circuit Efficient Charge Recovery Logic (ECRL), Conventional CMOS. The proposed PFAL combinational low power circuit design was proven to be superior to the other two designs in power dissipation and area. The combination of low power and low transistor count makes the new PFAL cell a viable option for low power design.
This paper proposes two new simplified cascade multiphase DC-DC boost power converters with high voltage-gain and low ripple. All simplifications reduce the number of active switching devices from 2N into N, where N is the phase number. The first simplification reduces the number of inductors from 2N into N+1 and increases the number of diodes from 2N into (2N+1). The second simplification reduces the number of inductors from 2N into N+1 and increases the number of diodes from 2N into (3N+1). The second simplification needs inductors with smaller current rating than the first simplification. The expressions of output voltage as a function of load current are derived by taking into account the voltage drops across the inductors and switching power devices. Simulated and experimental results are included to show the basic performance of the proposed cascade multiphase DC-DC boost power converters.
International Journal of Engineering Research and Applications (IJERA) is a team of researchers not publication services or private publications running the journals for monetary benefits, we are association of scientists and academia who focus only on supporting authors who want to publish their work. The articles published in our journal can be accessed online, all the articles will be archived for real time access.
Our journal system primarily aims to bring out the research talent and the works done by sciaentists, academia, engineers, practitioners, scholars, post graduate students of engineering and science. This journal aims to cover the scientific research in a broader sense and not publishing a niche area of research facilitating researchers from various verticals to publish their papers. It is also aimed to provide a platform for the researchers to publish in a shorter of time, enabling them to continue further All articles published are freely available to scientific researchers in the Government agencies,educators and the general public. We are taking serious efforts to promote our journal across the globe in various ways, we are sure that our journal will act as a scientific platform for all researchers to publish their works online.
SIMULTANEOUS OPTIMIZATION OF STANDBY AND ACTIVE ENERGY FOR SUB-THRESHOLD CIRC...VLSICS Design
Increased downscaling of CMOS circuits with respect to feature size and threshold voltage has a result of dramatically increasing in leakage current. So, leakage power reduction is an important design issue for active and standby modes as long as the technology scaling increased. In this paper, a simultaneous active and standby energy optimization methodology is proposed for 22 nm sub-threshold CMOS circuits. In the first phase, we investigate the dual threshold voltage design for active energy per cycle minimization. A
slack based genetic algorithm is proposed to find the optimal reverse body bias assignment to set of noncritical
paths gates to ensure low active energy per cycle with the maximum allowable frequency at the optimal supply voltage. The second phase, determine the optimal reverse body bias that can be applied to all gates for standby power optimization at the optimal supply voltage determined from the first phase.
Therefore, there exist two sets of gates and two reverse body bias values for each set. The reverse body bias is switched between these two values in response to the mode of operation. Experimental results are obtained for some ISCAS-85 benchmark circuits such as 74L85, 74283, ALU74181, and 16 bit RCA. The optimized circuits show significant energy saving ranged (from 14.5% to 42.28%) and standby power
saving ranged (from 62.8% to 67%)
PERFORMANCE ANALYSIS OF MODIFIED QSERL CIRCUITVLSICS Design
The document summarizes the performance analysis of a modified quasi-static energy recovery logic (MQSERL) circuit. Some key points:
1) MQSERL aims to improve energy efficiency over previous quasi-static energy recovery logic (QSERL) circuits by reducing non-adiabatic losses. It replaces diodes with transistors to minimize voltage drop.
2) The circuit uses two complementary sinusoidal power clocks for evaluation and hold phases. During evaluation, the load capacitance is slowly charged or discharged via transistors.
3) Simulation results show the MQSERL inverter has 30% lower energy dissipation than CMOS and 20% lower than QSERL up to 20MHz and 20fF
This document summarizes a novel interleaved boost converter proposed for photovoltaic power generation systems. The converter aims to reduce switching losses and voltage stress across switches compared to conventional interleaved boost converters. It achieves this by adding a coupling capacitor in series with one switch, which lowers the voltage stress on that switch and provides softer switching. Simulation results on a 0.5kW prototype verify that the proposed converter reduces voltage stress on one switch and achieves softer switching. The converter is also shown to effectively track the maximum power point using a perturb and observe control method under changing solar irradiation levels.
Adiabatic Logic Based Low Power Carry Select Adder for future TechnologiesIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
This document proposes a new mixed-style architecture for reducing power in multipliers. It combines a traditional Wallace tree-based part with a bypass array-based part. Simulations show the mixed architecture offers up to a 6.5x improvement in delay-power product compared to traditional array and Wallace tree multipliers. The mixed style exploits low power benefits of bypassing in arrays and performance benefits of Wallace trees.
Design of a Low Power Combinational Circuit by using Adiabatic LogicIJERA Editor
A novel low power and Positive Feedback Adiabatic Logic (PFAL) combinational low power circuit is presented in this paper. The power consumption and general characteristics of the PFAL combinationallow power circuit arethen compared against two combinational low power circuit Efficient Charge Recovery Logic (ECRL), Conventional CMOS. The proposed PFAL combinational low power circuit design was proven to be superior to the other two designs in power dissipation and area. The combination of low power and low transistor count makes the new PFAL cell a viable option for low power design.
This paper proposes two new simplified cascade multiphase DC-DC boost power converters with high voltage-gain and low ripple. All simplifications reduce the number of active switching devices from 2N into N, where N is the phase number. The first simplification reduces the number of inductors from 2N into N+1 and increases the number of diodes from 2N into (2N+1). The second simplification reduces the number of inductors from 2N into N+1 and increases the number of diodes from 2N into (3N+1). The second simplification needs inductors with smaller current rating than the first simplification. The expressions of output voltage as a function of load current are derived by taking into account the voltage drops across the inductors and switching power devices. Simulated and experimental results are included to show the basic performance of the proposed cascade multiphase DC-DC boost power converters.
International Journal of Engineering Research and Applications (IJERA) is a team of researchers not publication services or private publications running the journals for monetary benefits, we are association of scientists and academia who focus only on supporting authors who want to publish their work. The articles published in our journal can be accessed online, all the articles will be archived for real time access.
Our journal system primarily aims to bring out the research talent and the works done by sciaentists, academia, engineers, practitioners, scholars, post graduate students of engineering and science. This journal aims to cover the scientific research in a broader sense and not publishing a niche area of research facilitating researchers from various verticals to publish their papers. It is also aimed to provide a platform for the researchers to publish in a shorter of time, enabling them to continue further All articles published are freely available to scientific researchers in the Government agencies,educators and the general public. We are taking serious efforts to promote our journal across the globe in various ways, we are sure that our journal will act as a scientific platform for all researchers to publish their works online.
SIMULTANEOUS OPTIMIZATION OF STANDBY AND ACTIVE ENERGY FOR SUB-THRESHOLD CIRC...VLSICS Design
Increased downscaling of CMOS circuits with respect to feature size and threshold voltage has a result of dramatically increasing in leakage current. So, leakage power reduction is an important design issue for active and standby modes as long as the technology scaling increased. In this paper, a simultaneous active and standby energy optimization methodology is proposed for 22 nm sub-threshold CMOS circuits. In the first phase, we investigate the dual threshold voltage design for active energy per cycle minimization. A
slack based genetic algorithm is proposed to find the optimal reverse body bias assignment to set of noncritical
paths gates to ensure low active energy per cycle with the maximum allowable frequency at the optimal supply voltage. The second phase, determine the optimal reverse body bias that can be applied to all gates for standby power optimization at the optimal supply voltage determined from the first phase.
Therefore, there exist two sets of gates and two reverse body bias values for each set. The reverse body bias is switched between these two values in response to the mode of operation. Experimental results are obtained for some ISCAS-85 benchmark circuits such as 74L85, 74283, ALU74181, and 16 bit RCA. The optimized circuits show significant energy saving ranged (from 14.5% to 42.28%) and standby power
saving ranged (from 62.8% to 67%)
PERFORMANCE ANALYSIS OF MODIFIED QSERL CIRCUITVLSICS Design
The document summarizes the performance analysis of a modified quasi-static energy recovery logic (MQSERL) circuit. Some key points:
1) MQSERL aims to improve energy efficiency over previous quasi-static energy recovery logic (QSERL) circuits by reducing non-adiabatic losses. It replaces diodes with transistors to minimize voltage drop.
2) The circuit uses two complementary sinusoidal power clocks for evaluation and hold phases. During evaluation, the load capacitance is slowly charged or discharged via transistors.
3) Simulation results show the MQSERL inverter has 30% lower energy dissipation than CMOS and 20% lower than QSERL up to 20MHz and 20fF
This document summarizes a novel interleaved boost converter proposed for photovoltaic power generation systems. The converter aims to reduce switching losses and voltage stress across switches compared to conventional interleaved boost converters. It achieves this by adding a coupling capacitor in series with one switch, which lowers the voltage stress on that switch and provides softer switching. Simulation results on a 0.5kW prototype verify that the proposed converter reduces voltage stress on one switch and achieves softer switching. The converter is also shown to effectively track the maximum power point using a perturb and observe control method under changing solar irradiation levels.
Design and Implementation of Low Power 16-bit Carry-lookahead Adder using Adi...IRJET Journal
This document describes the design and implementation of a low power 16-bit carry-lookahead adder using two-phase clocked adiabatic static CMOS (2PASCL) logic. 2PASCL circuits can recover energy stored at output nodes during state transitions, providing power savings over conventional CMOS. The authors designed inverters, NAND, NOR, XOR gates and 4, 8, 16-bit carry-lookahead adders using 2PASCL logic in Cadence. Simulation results showed the 2PASCL designs consumed less power than equivalent static CMOS designs. Layouts were also produced for the 4, 8, 16-bit adders. Power analysis confirmed the 2PASCL adders achieved significant
This document discusses hybrid supercapacitors, which combine characteristics of electrochemical and double layer supercapacitors. It aims to study hybrid supercapacitor design, equivalent circuit modeling, and experimental evaluation. The key points are:
1) Hybrid supercapacitors have higher energy density and power density than conventional supercapacitors due to their combination of materials.
2) An experimental hybrid supercapacitor was constructed with a nickel hydroxide positive electrode and activated carbon negative electrode in KOH electrolyte.
3) The hybrid supercapacitor's equivalent circuit model and parameters were analyzed based on its internal structure and components. Experimental charging tests validated the fast charging capability of the hybrid supercapacitor.
Improving the Stability of Cascaded DC Power Supply System by Adaptive Active...IJMER
Abstract: When all links are changes in the cascade is the corner of the shape in the dc division
energy orbit (DEO). When resistances are intermission betwixt one by one stylish changes in that
would possibly end up so the cascaded orbits are unsteady. They are antecedent we can place in a
nearer to the useful in the cascaded orbit can be got in compelled to vary the supply they have load
changes in the internal structure of the same regions in the electrical device they can be opposed in
a quality of the characteristic of dc DEO. Throughout the Associate in nursing adaptation active
device in the (AACC) we can know another determined in the cascaded orbit. Therefore the AACC
was connected by side by side in the cascaded orbit’s they can mediate in between the carries and
completely a requirement of a notice then they carries the voltage with none modification in this
subsystems. Then it will have a stylish to the customary have basic units to measuring in the dc
DEO. When the AACC is additionally a similar bus device to cut back the output resistance of the
supply device, therefore averting in a interiority have their load changes in the input resistance, of
the cascaded orbit have their solutions then they becomes constant. We have important carrier
device it will computing in the AACC adaptation in line with they have output energy to the
cascaded orbit, they have energy vesting in the AACC that’s way they will reduced and therefore
they have a lot of energy in a reacting to the orbit so it is a best in the orbit of a submissive device.
What\'s many, since no capacitance have a requirement among an AACC, when the cascaded orbits
have their quantity of it slowly it will extend in time. They have activity fundamental truth to stop
their magnificence thought in the AACC are mentioned throughout of this project, it can have four
thousand eight hundred and zero watts cascaded orbit was contain a strive of process to move in a
full-bridge changes they can be styli shed and evaluated. So when the simulation solutions have to
clear the performance of the arrangement of AACC.
Designing Conservative Reversible N-Bit Binary Comparator for Emerging Quantu...VIT-AP University
The quantum-dot cellular automata (QCA) has more advantages than CMOS regarding area and power. This
work targets a conservative reversible comparator and its realization in QCA. In this work, we construct a
conservative reversible comparator with an optimal value of reversible metrics. In state to design, three conservative
reversible gates, namely PPC, PPNG-1 and PPNG-2 (PP = parity-preserving, C = comparator, N = new,
G = gate), are proposed. Furthermore, the quantum equivalent of 1-bit and 2-bit comparator is presented. The
proposed concept has been implemented through an algorithm for the n-bit comparator. Also, PPC workability
is tested in QCA. The PPC has been performing 1-bit comparator result with minimum area, cell complexity,
and latency, which is found to be 0.52 m2, 387 and 1 respectively. In addition, the complete energy dissipation
analysis to explore such as a thermal layout map of PPC is also presented in this paper. Further, average
energy dissipation v’s kink energy, maximum energy dissipation v’s kink energy, minimum energy dissipation
v’s kink energy and average output node polarization v’s temperature are provided in this paper. The proposed
comparator forwards an improved ratio of 33.33% in gate count and ranging from 27.27% to 29.35% in garbage
outputs than its counterparts circuits, which ensure more scalable.
Dynamic model of A DC-DC quasi-Z-source converter (q-ZSC)IJECEIAES
Two quasi-Z-source DC-DC converters (q-ZSCs) with buck-boost converter gain were recently proposed. The converters have advantages of continuous gain curve, higher gain magnitude and buck-boost operation at efficient duty ratio range when compared with existing q-ZSCs. Accurate dynamic models of these converters are needed for global and detailed overview by understanding their operation limits and effects of components sizes. A dynamic model of one of these converters is proposed here by first deriving the gain equation, state equations and state space model. A generalized small signal model was also derived before localizing it to this topology. The transfer functions (TF) were all derived, the poles and zeros analyzed with the boundaries for stable operations presented and discussed. Some of the findings include existence of right-hand plane (RHP) zero in the duty ratio to output capacitor voltage TF. This is common to the Z-source and quasi-Z-source topologies and implies control limitations. Parasitic resistances of the capacitors and inductors affect the nature and positions of the poles and zeros. It was also found and verified that rather than symmetric components, use of carefully selected smaller asymmetric components L1 and C1 produces less parasitic voltage drop, higher output voltage and current under the same conditions, thus better efficiency and performance at reduced cost, size and weight.
Selection of Passive Component for Cockroft Walton Voltage Multiplier: A Low ...IRJET Journal
This document summarizes a research paper on selecting passive components for a Cockroft-Walton voltage multiplier circuit to generate high voltages for educational laboratories. It describes criteria for selecting the number of stages, capacitors, and diodes in the circuit based on the required output voltage and allowable ripple. Simulation results show the effect of these selections on ripple voltage at different stages. The selection approach aims to minimize ripple at the final stage by reducing it at earlier stages, requiring non-equal capacitor values. This circuit can generate up to 100kV for laboratory experiments in a low-cost manner.
This paper presents a new simplified cascade multiphase DC-DC buck power converter suitable for low voltage and large current applications. Cascade connection enables very low voltage ratio without using very small duty cycles nor transformers. Large current with very low ripple content is achieved by using the multiphase technique. The proposed converter needs smaller number of components compared to conventional cascade multiphase DC-DC buck power converters. This paper also presents useful analysis of the proposed DC-DC buck power converter with a method to optimize the phase and cascade number. Simulation and experimental results are included to verify the basic performance of the proposed DC-DC buck power converter.
Design and Implementation of Low Power Multiplier Using Proposed Two Phase Cl...IJECEIAES
This paper presents a design and implementation of 2*2 array and 4*4 array multiplier using proposed Two Phase Clocked Adiabatic Static CMOS logic (2PASCL) circuit. The proposed 2PASCL circuit is based on adiabatic energy recovery principle which consumes less power. The proposed 2PASCL uses two sinusoidal power clocks which are 180 0 phase shifted with each other. The measurement result of 2*2 array proposed 2PASCL multiplier gives 80.16 % and 97.67 %power reduction relative to reported 2PASCL and conventional CMOS logic and the measurement result of 4*4 array proposed 2PASCL multiplier demonstrate 32.88 % and 82.02 %power reduction compared to reported 2PASCL and conventional CMOS logic. Another advantage of the proposed circuit is that it gives less power though the number of transistors in proposed and reported 2PASCL circuit is same. From the result we conclude that proposed 2PASCL technology is advantageous to application in low power digital systems, pacemakers and sensors. The circuits are simulated at 180nm technology mode.
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
Soft-Switching and Low Ripple Interleaved Boost Converter with Photo-Voltaic ...Premier Publishers
In this paper novel interleaved boost converter (IBC) with snubber circuit is presented. It is compared with conventional boost and IBC. In the proposed topology current stress on each switch is one fourth of input current. Simulation comparison is done for 1hp universal motor and it is proved that proposed converter gives near to the designed values of output voltage, current and power. Ripples in boost, IBC and proposed IBC system are compared. Ripples of the parameter voltage, current and power are reduced with snubber. Also proposed system with hard switching efficiency is about 92% and its efficiency is increased to 93.37% with soft switching.
IRJET- Single Switched Capacitor High Gain Boost Quasi-Z Source ConverterIRJET Journal
This document describes a proposed single switched capacitor high gain boost quasi-Z source converter. The converter aims to achieve the benefits of both quasi-Z source converters and switched capacitor converters. It maintains low current stress on the switch, low voltage stress on the diodes at the output, and provides high voltage gain across the load using similar components as other step-up DC-DC converters. Simulation and experimental results are presented to verify the characteristics of the proposed converter, such as achieving maximum efficiencies of 92-94% theoretically and practically.
DESIGN AND IMPLEMENTATION OF 10 BIT, 2MS/s SPLIT SAR ADC USING 0.18um CMOS TE...VLSICS Design
This paper focuses on Design and Implementation of 10 Bit, 2MS/s successive approximation Register (SAR) Analog to digital converter (ADC) using Split DAC architecture. This SAR ADC architecture is
designed and simulated using GPDK 0.18um CMOS technology. It consists of different blocks like sample
and hold, comparator, Successive Approximation Register (SAR) and Split Digital to analog converter(DAC). For each block of SAR ADC power is calculated. DAC is an important component within the SAR ADC. The charge redistribution DAC in a Split capacitor configuration has a total capacitance which is96.87% smaller compared to a conventional binary weighted design. Hence Split DAC gives an optimizedarchitecture and it consumes less power. Optimized design of DAC architecture ensures the accuracy ofthe components, which improves the performance of SAR ADC. Comparator constructed from resistances,capacitance and dependent voltage sources instead of MOS transistors. Dynamic range for SAR ADC
using split DAC is 60.19dB. The supply voltage is 1.2V. The total Power consumed by SAR ADC using
Split array DAC is 95.65114uW and SAR ADC using binary weighted capacitor DAC is 211.19084uW.
This document discusses transferred electron devices and the Gunn diode. It begins with an overview of carrier transfer mechanisms in semiconductors and how an external electric field can enable interband and intraband transitions. Negative differential conductivity, which is important for amplification, arises when the conductivity decreases with increasing electric field due to transfer of carriers between valleys. The document then focuses on the Gunn diode, the operating principles, materials used, and mathematical modeling of negative conductivity. It covers formation of domains under high fields and their effect on current. Different modes of Gunn diode operation and example applications are also summarized.
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
Hybrid Two Quasi Z-Source Converter for Photovoltaic ApplicationPremier Publishers
This paper presents a Hybrid Two Quasi Z-source (HTQZS) DC-DC converter for photovoltaic applications. These are mainly employed to full fill the demand of the voltage boost in photovoltaic applications from the lower value voltage. The traditional z source networks have some limitations in voltage boosting, so the modified z source means the different combination of the LC components is combined to form the hybrid quasi z source networks. This hybrid two quasi z source dc-dc converters can be applied for the dc-ac, ac-ac, and ac-dc conversions. The structure of the proposed converter is simpler. This converter adds the benefits to the traditional z source converter. This converter draws the continuous input current. The converter simulated is the combination of two different quasi z source networks. This converter uses the duty cycle less than the traditional z source network and gives the more gain than that. PV panel used as source to converter and then the output is inverted and step up.
The document describes using particle swarm optimization (PSO) to control an interline power flow controller (IPFC) installed on a power transmission system. An IPFC uses voltage source converters to inject active and reactive power into transmission lines, allowing control of power flows. The document presents a MATLAB/Simulink model of an IPFC on a 4-bus system. Optimal parameters for the IPFC (magnitude and angle of injected voltages) are determined using PSO to minimize transmission line losses. Simulations apply this method to the IEEE 30-bus test system. PSO helps find optimal IPFC settings to efficiently control power flows in the multi-line transmission system.
Design of a Low Power and Area Efficient Flip Flop With Embedded Logic Moduleiosrjce
As number of modules per chip is increasing, number of transistors in a chip increases resulting in
increase in area and power dissipation. Area and power dissipation problems can be most effectively addressed
if the basic building blocks of the circuit are designed for lower power dissipation and occupy less space. FlipFlop,
which is basic building block, plays a major role in design of complex systems. From the open literature,
Semi Dynamic Flip-Flop (SDFF) and Dual Dynamic Flip-Flops (DDFF) are classic structures which are
efficient for incorporating complex logic functions. In this paper, a new low power and area efficient flip-flop
with Embedded Logic Module (ELM) is proposed. The proposed Flip-Flop reduces 50% to 60% of power
dissipation as compared to conventional flip-flops and delay up to 86% is also reduced. Serial in Parallel out
(SIPO) shift register is designed with the proposed flip-flop which exhibit low power dissipation. The
simulations are done in MENTOR GRAPHICS, Schematic editor, Generic GDK, 130nm technology.
This paper deals with comparison of responses of PI and Proportional Resonant controlled DC to AC Converter systems. The objective of this work is to regulate the output of Dual Active Bridge DC to DC converter (DABDAC). The input DC is converted into high frequency AC using Half bridge inverter. It is stepped up by using step up transformer and then it is rectified. The DC is converted into Low frequency AC using a Half bridge inverter. The open loop DABDAC system, closed loop PI based DABDAC system an Proportional Resonant Controller (PRC)based DABDAC system are designed, modeled and simulated using MATLAB Simulink. The results of PR controlled system are compared with those of PI controlled system. The results indicate that the proposed PRC-DABDAC has better time domain response than PI controlled DABDAC system. The proposed DABDAC system has advantages like high gain and steady state error in output voltage.
This document discusses using video compression techniques to compress multichannel neural signals. It proposes using a multiwavelet transform to decorrelate the signals, followed by vector quantization to exploit correlations between electrodes. Motion estimation and compensation are also used to reduce redundancy between successive neural frames by determining motion vectors, similar to how video compression analyzes frame-to-frame motion. The goal is to significantly reduce the large amounts of neural data for easier wireless transmission without degrading quality.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
This document proposes a new negative edge triggered flip-flop circuit called the Switching Transistor Based D Flip-Flop (STDFF) that reduces power consumption and area compared to conventional D flip-flops. The STDFF uses only 8 transistors compared to other designs, reducing power usage by 85% and area by 40%. Simulations show the STDFF operates correctly as a negative edge triggered flip-flop with reduced delay. It is proposed that this low power design is suitable for battery-powered mobile devices.
This document describes the design of a low power multiserial to Ethernet gateway for unmanned aerial vehicle data acquisition systems. The gateway uses an FPGA and Ethernet controller chip to interface with multiple serial devices and transmit the data over Ethernet. The FPGA implements UART modules to interface with sensors and an ADC. It collects data from the serial devices and sends it to the Ethernet module packed in Ethernet frames. This simplifies wiring and allows the data to be transmitted to the ground station computer over Ethernet for processing and storage.
Design and Implementation of Low Power 16-bit Carry-lookahead Adder using Adi...IRJET Journal
This document describes the design and implementation of a low power 16-bit carry-lookahead adder using two-phase clocked adiabatic static CMOS (2PASCL) logic. 2PASCL circuits can recover energy stored at output nodes during state transitions, providing power savings over conventional CMOS. The authors designed inverters, NAND, NOR, XOR gates and 4, 8, 16-bit carry-lookahead adders using 2PASCL logic in Cadence. Simulation results showed the 2PASCL designs consumed less power than equivalent static CMOS designs. Layouts were also produced for the 4, 8, 16-bit adders. Power analysis confirmed the 2PASCL adders achieved significant
This document discusses hybrid supercapacitors, which combine characteristics of electrochemical and double layer supercapacitors. It aims to study hybrid supercapacitor design, equivalent circuit modeling, and experimental evaluation. The key points are:
1) Hybrid supercapacitors have higher energy density and power density than conventional supercapacitors due to their combination of materials.
2) An experimental hybrid supercapacitor was constructed with a nickel hydroxide positive electrode and activated carbon negative electrode in KOH electrolyte.
3) The hybrid supercapacitor's equivalent circuit model and parameters were analyzed based on its internal structure and components. Experimental charging tests validated the fast charging capability of the hybrid supercapacitor.
Improving the Stability of Cascaded DC Power Supply System by Adaptive Active...IJMER
Abstract: When all links are changes in the cascade is the corner of the shape in the dc division
energy orbit (DEO). When resistances are intermission betwixt one by one stylish changes in that
would possibly end up so the cascaded orbits are unsteady. They are antecedent we can place in a
nearer to the useful in the cascaded orbit can be got in compelled to vary the supply they have load
changes in the internal structure of the same regions in the electrical device they can be opposed in
a quality of the characteristic of dc DEO. Throughout the Associate in nursing adaptation active
device in the (AACC) we can know another determined in the cascaded orbit. Therefore the AACC
was connected by side by side in the cascaded orbit’s they can mediate in between the carries and
completely a requirement of a notice then they carries the voltage with none modification in this
subsystems. Then it will have a stylish to the customary have basic units to measuring in the dc
DEO. When the AACC is additionally a similar bus device to cut back the output resistance of the
supply device, therefore averting in a interiority have their load changes in the input resistance, of
the cascaded orbit have their solutions then they becomes constant. We have important carrier
device it will computing in the AACC adaptation in line with they have output energy to the
cascaded orbit, they have energy vesting in the AACC that’s way they will reduced and therefore
they have a lot of energy in a reacting to the orbit so it is a best in the orbit of a submissive device.
What\'s many, since no capacitance have a requirement among an AACC, when the cascaded orbits
have their quantity of it slowly it will extend in time. They have activity fundamental truth to stop
their magnificence thought in the AACC are mentioned throughout of this project, it can have four
thousand eight hundred and zero watts cascaded orbit was contain a strive of process to move in a
full-bridge changes they can be styli shed and evaluated. So when the simulation solutions have to
clear the performance of the arrangement of AACC.
Designing Conservative Reversible N-Bit Binary Comparator for Emerging Quantu...VIT-AP University
The quantum-dot cellular automata (QCA) has more advantages than CMOS regarding area and power. This
work targets a conservative reversible comparator and its realization in QCA. In this work, we construct a
conservative reversible comparator with an optimal value of reversible metrics. In state to design, three conservative
reversible gates, namely PPC, PPNG-1 and PPNG-2 (PP = parity-preserving, C = comparator, N = new,
G = gate), are proposed. Furthermore, the quantum equivalent of 1-bit and 2-bit comparator is presented. The
proposed concept has been implemented through an algorithm for the n-bit comparator. Also, PPC workability
is tested in QCA. The PPC has been performing 1-bit comparator result with minimum area, cell complexity,
and latency, which is found to be 0.52 m2, 387 and 1 respectively. In addition, the complete energy dissipation
analysis to explore such as a thermal layout map of PPC is also presented in this paper. Further, average
energy dissipation v’s kink energy, maximum energy dissipation v’s kink energy, minimum energy dissipation
v’s kink energy and average output node polarization v’s temperature are provided in this paper. The proposed
comparator forwards an improved ratio of 33.33% in gate count and ranging from 27.27% to 29.35% in garbage
outputs than its counterparts circuits, which ensure more scalable.
Dynamic model of A DC-DC quasi-Z-source converter (q-ZSC)IJECEIAES
Two quasi-Z-source DC-DC converters (q-ZSCs) with buck-boost converter gain were recently proposed. The converters have advantages of continuous gain curve, higher gain magnitude and buck-boost operation at efficient duty ratio range when compared with existing q-ZSCs. Accurate dynamic models of these converters are needed for global and detailed overview by understanding their operation limits and effects of components sizes. A dynamic model of one of these converters is proposed here by first deriving the gain equation, state equations and state space model. A generalized small signal model was also derived before localizing it to this topology. The transfer functions (TF) were all derived, the poles and zeros analyzed with the boundaries for stable operations presented and discussed. Some of the findings include existence of right-hand plane (RHP) zero in the duty ratio to output capacitor voltage TF. This is common to the Z-source and quasi-Z-source topologies and implies control limitations. Parasitic resistances of the capacitors and inductors affect the nature and positions of the poles and zeros. It was also found and verified that rather than symmetric components, use of carefully selected smaller asymmetric components L1 and C1 produces less parasitic voltage drop, higher output voltage and current under the same conditions, thus better efficiency and performance at reduced cost, size and weight.
Selection of Passive Component for Cockroft Walton Voltage Multiplier: A Low ...IRJET Journal
This document summarizes a research paper on selecting passive components for a Cockroft-Walton voltage multiplier circuit to generate high voltages for educational laboratories. It describes criteria for selecting the number of stages, capacitors, and diodes in the circuit based on the required output voltage and allowable ripple. Simulation results show the effect of these selections on ripple voltage at different stages. The selection approach aims to minimize ripple at the final stage by reducing it at earlier stages, requiring non-equal capacitor values. This circuit can generate up to 100kV for laboratory experiments in a low-cost manner.
This paper presents a new simplified cascade multiphase DC-DC buck power converter suitable for low voltage and large current applications. Cascade connection enables very low voltage ratio without using very small duty cycles nor transformers. Large current with very low ripple content is achieved by using the multiphase technique. The proposed converter needs smaller number of components compared to conventional cascade multiphase DC-DC buck power converters. This paper also presents useful analysis of the proposed DC-DC buck power converter with a method to optimize the phase and cascade number. Simulation and experimental results are included to verify the basic performance of the proposed DC-DC buck power converter.
Design and Implementation of Low Power Multiplier Using Proposed Two Phase Cl...IJECEIAES
This paper presents a design and implementation of 2*2 array and 4*4 array multiplier using proposed Two Phase Clocked Adiabatic Static CMOS logic (2PASCL) circuit. The proposed 2PASCL circuit is based on adiabatic energy recovery principle which consumes less power. The proposed 2PASCL uses two sinusoidal power clocks which are 180 0 phase shifted with each other. The measurement result of 2*2 array proposed 2PASCL multiplier gives 80.16 % and 97.67 %power reduction relative to reported 2PASCL and conventional CMOS logic and the measurement result of 4*4 array proposed 2PASCL multiplier demonstrate 32.88 % and 82.02 %power reduction compared to reported 2PASCL and conventional CMOS logic. Another advantage of the proposed circuit is that it gives less power though the number of transistors in proposed and reported 2PASCL circuit is same. From the result we conclude that proposed 2PASCL technology is advantageous to application in low power digital systems, pacemakers and sensors. The circuits are simulated at 180nm technology mode.
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
Soft-Switching and Low Ripple Interleaved Boost Converter with Photo-Voltaic ...Premier Publishers
In this paper novel interleaved boost converter (IBC) with snubber circuit is presented. It is compared with conventional boost and IBC. In the proposed topology current stress on each switch is one fourth of input current. Simulation comparison is done for 1hp universal motor and it is proved that proposed converter gives near to the designed values of output voltage, current and power. Ripples in boost, IBC and proposed IBC system are compared. Ripples of the parameter voltage, current and power are reduced with snubber. Also proposed system with hard switching efficiency is about 92% and its efficiency is increased to 93.37% with soft switching.
IRJET- Single Switched Capacitor High Gain Boost Quasi-Z Source ConverterIRJET Journal
This document describes a proposed single switched capacitor high gain boost quasi-Z source converter. The converter aims to achieve the benefits of both quasi-Z source converters and switched capacitor converters. It maintains low current stress on the switch, low voltage stress on the diodes at the output, and provides high voltage gain across the load using similar components as other step-up DC-DC converters. Simulation and experimental results are presented to verify the characteristics of the proposed converter, such as achieving maximum efficiencies of 92-94% theoretically and practically.
DESIGN AND IMPLEMENTATION OF 10 BIT, 2MS/s SPLIT SAR ADC USING 0.18um CMOS TE...VLSICS Design
This paper focuses on Design and Implementation of 10 Bit, 2MS/s successive approximation Register (SAR) Analog to digital converter (ADC) using Split DAC architecture. This SAR ADC architecture is
designed and simulated using GPDK 0.18um CMOS technology. It consists of different blocks like sample
and hold, comparator, Successive Approximation Register (SAR) and Split Digital to analog converter(DAC). For each block of SAR ADC power is calculated. DAC is an important component within the SAR ADC. The charge redistribution DAC in a Split capacitor configuration has a total capacitance which is96.87% smaller compared to a conventional binary weighted design. Hence Split DAC gives an optimizedarchitecture and it consumes less power. Optimized design of DAC architecture ensures the accuracy ofthe components, which improves the performance of SAR ADC. Comparator constructed from resistances,capacitance and dependent voltage sources instead of MOS transistors. Dynamic range for SAR ADC
using split DAC is 60.19dB. The supply voltage is 1.2V. The total Power consumed by SAR ADC using
Split array DAC is 95.65114uW and SAR ADC using binary weighted capacitor DAC is 211.19084uW.
This document discusses transferred electron devices and the Gunn diode. It begins with an overview of carrier transfer mechanisms in semiconductors and how an external electric field can enable interband and intraband transitions. Negative differential conductivity, which is important for amplification, arises when the conductivity decreases with increasing electric field due to transfer of carriers between valleys. The document then focuses on the Gunn diode, the operating principles, materials used, and mathematical modeling of negative conductivity. It covers formation of domains under high fields and their effect on current. Different modes of Gunn diode operation and example applications are also summarized.
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
Hybrid Two Quasi Z-Source Converter for Photovoltaic ApplicationPremier Publishers
This paper presents a Hybrid Two Quasi Z-source (HTQZS) DC-DC converter for photovoltaic applications. These are mainly employed to full fill the demand of the voltage boost in photovoltaic applications from the lower value voltage. The traditional z source networks have some limitations in voltage boosting, so the modified z source means the different combination of the LC components is combined to form the hybrid quasi z source networks. This hybrid two quasi z source dc-dc converters can be applied for the dc-ac, ac-ac, and ac-dc conversions. The structure of the proposed converter is simpler. This converter adds the benefits to the traditional z source converter. This converter draws the continuous input current. The converter simulated is the combination of two different quasi z source networks. This converter uses the duty cycle less than the traditional z source network and gives the more gain than that. PV panel used as source to converter and then the output is inverted and step up.
The document describes using particle swarm optimization (PSO) to control an interline power flow controller (IPFC) installed on a power transmission system. An IPFC uses voltage source converters to inject active and reactive power into transmission lines, allowing control of power flows. The document presents a MATLAB/Simulink model of an IPFC on a 4-bus system. Optimal parameters for the IPFC (magnitude and angle of injected voltages) are determined using PSO to minimize transmission line losses. Simulations apply this method to the IEEE 30-bus test system. PSO helps find optimal IPFC settings to efficiently control power flows in the multi-line transmission system.
Design of a Low Power and Area Efficient Flip Flop With Embedded Logic Moduleiosrjce
As number of modules per chip is increasing, number of transistors in a chip increases resulting in
increase in area and power dissipation. Area and power dissipation problems can be most effectively addressed
if the basic building blocks of the circuit are designed for lower power dissipation and occupy less space. FlipFlop,
which is basic building block, plays a major role in design of complex systems. From the open literature,
Semi Dynamic Flip-Flop (SDFF) and Dual Dynamic Flip-Flops (DDFF) are classic structures which are
efficient for incorporating complex logic functions. In this paper, a new low power and area efficient flip-flop
with Embedded Logic Module (ELM) is proposed. The proposed Flip-Flop reduces 50% to 60% of power
dissipation as compared to conventional flip-flops and delay up to 86% is also reduced. Serial in Parallel out
(SIPO) shift register is designed with the proposed flip-flop which exhibit low power dissipation. The
simulations are done in MENTOR GRAPHICS, Schematic editor, Generic GDK, 130nm technology.
This paper deals with comparison of responses of PI and Proportional Resonant controlled DC to AC Converter systems. The objective of this work is to regulate the output of Dual Active Bridge DC to DC converter (DABDAC). The input DC is converted into high frequency AC using Half bridge inverter. It is stepped up by using step up transformer and then it is rectified. The DC is converted into Low frequency AC using a Half bridge inverter. The open loop DABDAC system, closed loop PI based DABDAC system an Proportional Resonant Controller (PRC)based DABDAC system are designed, modeled and simulated using MATLAB Simulink. The results of PR controlled system are compared with those of PI controlled system. The results indicate that the proposed PRC-DABDAC has better time domain response than PI controlled DABDAC system. The proposed DABDAC system has advantages like high gain and steady state error in output voltage.
This document discusses using video compression techniques to compress multichannel neural signals. It proposes using a multiwavelet transform to decorrelate the signals, followed by vector quantization to exploit correlations between electrodes. Motion estimation and compensation are also used to reduce redundancy between successive neural frames by determining motion vectors, similar to how video compression analyzes frame-to-frame motion. The goal is to significantly reduce the large amounts of neural data for easier wireless transmission without degrading quality.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
This document proposes a new negative edge triggered flip-flop circuit called the Switching Transistor Based D Flip-Flop (STDFF) that reduces power consumption and area compared to conventional D flip-flops. The STDFF uses only 8 transistors compared to other designs, reducing power usage by 85% and area by 40%. Simulations show the STDFF operates correctly as a negative edge triggered flip-flop with reduced delay. It is proposed that this low power design is suitable for battery-powered mobile devices.
This document describes the design of a low power multiserial to Ethernet gateway for unmanned aerial vehicle data acquisition systems. The gateway uses an FPGA and Ethernet controller chip to interface with multiple serial devices and transmit the data over Ethernet. The FPGA implements UART modules to interface with sensors and an ADC. It collects data from the serial devices and sends it to the Ethernet module packed in Ethernet frames. This simplifies wiring and allows the data to be transmitted to the ground station computer over Ethernet for processing and storage.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
This document summarizes a research paper that analyzed attribute association in heart disease using data mining techniques. The paper proposed a new measure called AA(I) to quantify the strength of association among attributes in a dataset. The measure was applied to both frequent and infrequent itemsets. The dataset contained 1897 subjects characterized by 21 attributes related to demographics, medical history, and lab tests. Analysis found that risk of cardiovascular disease was higher in males aged 56-65. The proposed association measure could help predict diseases like heart attacks by identifying relationships between comorbid attributes. Future work aims to test the measure on larger health datasets and compare its performance to other algorithms.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
This document summarizes a research paper on color image enhancement using an adaptive filter. It proposes a new algorithm that uses an adaptive filter to obtain the background image from a video based on color information. It then performs adaptive adjustment on the luminance image to get a locally enhanced image. Finally, it applies color restoration to obtain the enhanced color image. The algorithm aims to better preserve color information and reduce halo effects compared to techniques using discrete wavelet transforms. Experimental results show the adaptive filter produces clearer details and more natural colors in enhanced images and video frames.
This document summarizes a study on the effects of elevated temperatures on the compressive and splitting tensile strengths of ultra-high strength concrete. Cubes and cylinders of M100 grade concrete were exposed to temperatures between 50-250°C for durations of 1-4 hours. Testing found that compressive and splitting tensile strengths initially increased with temperature up to 100°C but then decreased with further increases in temperature. The maximum strengths were observed when specimens were heated to 100°C for 1 hour. Understanding how high-strength concrete properties change after fire exposure can help determine the load capacity of damaged structures.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
This document summarizes a research paper that proposes a secure communal verification and key exchange scheme for mobile communications. The scheme uses nested one-time secrets, with an outer secret shared between a user and the home location register, and an inner secret shared between a user and the current visited location register. This allows for efficient verification when a user does not change locations, reducing computation costs. The scheme aims to improve security and performance over existing verification schemes for mobile networks. It uses different verification mechanisms like timestamps, one-time secrets, and nonces depending on the situation to optimize efficiency.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
This document discusses using the Expectation Maximization clustering algorithm for text summarization. It begins with an introduction to text summarization and natural language processing. It then describes implementing Expectation Maximization clustering on text that has undergone natural language processing steps like splitting, tokenization, part-of-speech tagging, and parsing. This clusters similar sentences based on their similarity values from the distance matrix. The clustered sentences can then be used to generate a summary by selecting the most representative sentences.
LAS GRANDES TRANSFORMACIONES SOCIOECÓNOMICAS DE LA ESPAÑA ACTUAL (1978-2008)...CCOBAEZA
Este documento resume las grandes transformaciones socioeconómicas de España desde 1978 hasta 2008. Describe cómo mejoraron las condiciones de vida de los españoles, con mayor consumo y bienestar material. También analiza cambios demográficos como el aumento de la propiedad de viviendas y vehículos. Examina la evolución de sectores como la industria, la agricultura y los servicios durante este período.
La Gestión para la innovación tecnológica en el uso de recursos digitales en ...RIBDA 2009
Este documento presenta un resumen de una investigación sobre el uso y manejo de la información por parte de la comunidad académica de la Universidad Nacional Autónoma de México. Describe el cálculo de un tamaño muestral de 366 usuarios y los resultados generales de aplicar instrumentos estadísticos a la muestra. Concluye que la propuesta y desarrollo de un modelo para la gestión de recursos digitales debe garantizar la calidad académica y formación de usuarios en el manejo de estos recursos.
The students in P3 B, the class of the beans, made cinnamon and vanilla cookies. They learned the full process of making the cookies which involved presenting ingredients, measuring ingredients like flour, sugar, butter, cinnamon and vanilla, mixing the ingredients together, forming dough balls and letting them rest in the refrigerator. On Sant Jordi, they had a community breakfast in the playground where they did workshops and were later given stories to enjoy.
Implementation of Area Effective Carry Select AddersKumar Goud
Abstract: In the design of Integrated circuit area occupancy plays a vital role because of increasing the necessity of portable systems. Carry Select Adder (CSLA) is a fast adder used in data processing processors for performing fast arithmetic functions. From the structure of the CSLA, the scope is reducing the area of CSLA based on the efficient gate-level modification. In this paper 16 bit, 32 bit, 64 bit and 128 bit Regular Linear CSLA, Modified Linear CSLA, Regular Square-root CSLA (SQRT CSLA) and Modified SQRT CSLA architectures have been developed and compared. However, the Regular CSLA is still area-consuming due to the dual Ripple-Carry Adder (RCA) structure. For reducing area, the CSLA can be implemented by using a single RCA and an add-one circuit instead of using dual RCA. Comparing the Regular Linear CSLA with Regular SQRT CSLA, the Regular SQRT CSLA has reduced area as well as comparing the Modified Linear CSLA with Modified SQRT CSLA; the Modified SQRT CSLA has reduced area. The results and analysis show that the Modified Linear CSLA and Modified SQRT CSLA provide better outcomes than the Regular Linear CSLA and Regular SQRT CSLA respectively. This project was aimed for implementing high performance optimized FPGA architecture. Modelsim 10.0c is used for simulating the CSLA and synthesized using Xilinx PlanAhead13.4. Then the implementation is done in Virtex5 FPGA Kit.
Keywords: Field Programmable Gate Array (FPGA), efficient, Carry Select Adder (CSLA), Square-root CSLA (SQRTCSLA).
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
This document discusses the design of an energy efficient full adder cell using double pass transistor asynchronous adiabatic logic (DPTAAL). It first provides background on asynchronous circuits and adiabatic logic for low power applications. It then describes an existing DPTAAL full adder cell design and proposes a new design that uses a carry save adder to reduce addition of 3 numbers to 2 numbers. The document concludes that the new asynchronous adiabatic full adder cell design consumes less energy than conventional logic designs for frequencies from 100-200MHz, confirming its feasibility for low power applications.
The document discusses the design of an energy efficient carry save adder using asynchronous adiabatic logic. It first discusses existing work on using double pass transistor logic with asynchronous adiabatic logic to design an energy efficient full adder cell. It then proposes using a carry save adder which can add 3 n-bit numbers using only 2 numbers of additions, reducing delay and improving performance. The document discusses the design of a static energy recovery full adder cell and use of double pass transistor logic to avoid signal degradation. It also provides background on asynchronous adiabatic logic which aims to reduce power dissipation by reusing stored energy.
The paper presents a low Power consumption plays a vital role in the present day VLSI technology. Power consumption of an electronic device can be reduced by adopt changed design styles. Multipliers play a most important role in high concert systems. This project focus on a novel energy efficient technique called adiabatic logic which is based on energy renewal principle and power is compared by designing a multiplier. CMOS technology plays a main role in designing low power consuming devices, compared to different logic family CMOS has less power dissipation. Adiabatic logic method is assumed to be an attractive solution for low power electronic applications. By using Adiabatic techniques energy dissipation in PMOS network can be minimized and selection of energy stored at load capacitance can be recycled instead of dissipated as heat. Tanner EDA tools are used for simulation.
SIMULTANEOUS OPTIMIZATION OF STANDBY AND ACTIVE ENERGY FOR SUB-THRESHOLD CIRC...VLSICS Design
Increased downscaling of CMOS circuits with respect to feature size and threshold voltage has a result of
dramatically increasing in leakage current. So, leakage power reduction is an important design issue for
active and standby modes as long as the technology scaling increased. In this paper, a simultaneous active
and standby energy optimization methodology is proposed for 22 nm sub-threshold CMOS circuits. In the
first phase, we investigate the dual threshold voltage design for active energy per cycle minimization. A
slack based genetic algorithm is proposed to find the optimal reverse body bias assignment to set of noncritical
paths gates to ensure low active energy per cycle with the maximum allowable frequency at the
optimal supply voltage. The second phase, determine the optimal reverse body bias that can be applied to
all gates for standby power optimization at the optimal supply voltage determined from the first phase.
Therefore, there exist two sets of gates and two reverse body bias values for each set. The reverse body bias
is switched between these two values in response to the mode of operation. Experimental results are
obtained for some ISCAS-85 benchmark circuits such as 74L85, 74283, ALU74181, and 16 bit RCA. The
optimized circuits show significant energy saving ranged (from 14.5% to 42.28%) and standby power
saving ranged (from 62.8% to 67%).
SIMULTANEOUS OPTIMIZATION OF STANDBY AND ACTIVE ENERGY FOR SUB-THRESHOLD CIRC...VLSICS Design
Increased downscaling of CMOS circuits with respect to feature size and threshold voltage has a result of dramatically increasing in leakage current. So, leakage power eduction is an important design issue for active and standby modes as long as the technology scaling increased. In this paper, a simultaneous active and standbyrgy optimization methodology is proposed for 22 nm sub-threshold CMOS circuits. In thefirst phase, we investigate the dual threshold voltage design for active energy per cycle minimization. A slack based genetic algorithm is proposed to find the optimal reverse body bias assignment to set of noncritical paths gates to ensure low active energy per cycle with the maximum allowable frequency at the optimal supply voltage. The second phase, determine the optimal reverse body bias that can be applied to
all gates for standby power optimization at the optimal supply voltage determined from the first phase. Therefore, there exist two sets of gates and two reverse body bias values for each set. The reverse body bias is switched between these two values in response to the mode of operation. Experimental results are obtained for some ISCAS-85 benchmark circuits such as 74L85, 74283, ALU74181, and 16 bit RCA. The optimized circuits show significant energy saving ranged (from 14.5% to 42.28%) and standby power saving ranged (from 62.8% to 67%).
Design of High Speed Low Power 15-4 Compressor Using Complementary Energy Pat...CSCJournals
This paper presents the implementation of a novel high speed low power 15-4 Compressor for high speed multiplication applications using single phase clocked quasi static adiabatic logic namely CEPAL (Complementary Energy Path Adiabatic Logic). The main advantage of this static adiabatic logic is the minimization of the 1/2CVth2 energy dissipation occurring every cycle in the multi-phase power-clocked adiabatic circuits. The proposed Compressor uses bit sliced architecture to exploit the parallelism in the computation of sum of 15 input bits by five full adders. The newly proposed Compressor is also centered around the design of a novel 5-3 Compressor that attempts to minimize the stage delays of a conventional 5-3 Compressor that is designed using single bit full adder and half adder architectures. Firstly, the performance characteristics of CEPAL 15-3 Compressor with 14 transistor and 10 transistor adder designs are compared against the conventional static CMOS logic counterpart to identify its adiabatic power advantage. The analyses are carried out using the industry standard Tanner EDA design environment using 250 nm technology libraries. The results prove that CEPAL 14T 15-4 Compressor is 68.11% power efficient, 75.31% faster over its static CMOS counterpart.
Design and Analysis of Multi Vt and Variable Vt based Pipelined Adder for Lo...VLSICS Design
Majority of Digital Signal Processing (DSP) applications require arithmetic blocks such as multipliers and adders for hardware realization of complex algorithms. Power consumption of arithmetic blocks need to be minimized by use of low power techniques. In this paper, an experimental setup is developed to identify the sources of power dissipation and remedies that can be adopted to minimize power dissipation in arithmetic blocks. Use of low power techniques such as Multi Vt, variable Vt, pipelining, geometry scaling and use of appropriate load capacitance have been used to reduce power dissipation. A 4-bit pipelined adder is designed and the power dissipation is reduced to 4.17µW from 9.6µW. The designed pipelined adder can be used for DSP applications.
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Design and Analysis of Multi Vt and Variable Vt based Pipelined Adder for Low...VLSICS Design
Majority of Digital Signal Processing (DSP) applications require arithmetic blocks such as multipliers and adders for hardware realization of complex algorithms. Power consumption of arithmetic blocks need to be minimized by use of low power techniques. In this paper, an experimental setup is developed to identify the sources of power dissipation and remedies that can be adopted to minimize power dissipation in arithmetic blocks. Use of low power techniques such as Multi Vt, variable Vt, pipelining, geometry scaling and use of appropriate load capacitance have been used to reduce power dissipation. A 4-bit pipelined adder is designed and the power dissipation is reduced to 4.17µW from 9.6µW. The designed pipelined adder can be used for DSP applications.
An Ultra-Low Power Robust Koggestone Adder at Sub-Threshold Voltages for Impl...VLSICS Design
The growing demand for energy constrained applications and portable devices have created a dire need for ultra-low power circuits. Implantable biomedical devices such as pacemakers need ultra-low power circuits for a better battery life for uninterrupted biomedical data processing. Circuits operating in subthreshold region minimize the energy per operation, thus providing a better platform for energy constrained implantable biomedical devices. This paper presents 8, 16 and 32-bit ultra-low power robust Kogge-Stone adders with improved performance. These adders operate at subthreshold supply voltages which can be used for low power implantable bio-medical devices such as pacemakers. To improve the performance of these adders in sub-threshold region, forward body bias technique and multi-threshold transistors are used. The adders are designed using NCSU 45nm bulk CMOS process library and the simulations were performed using HSPICE circuit simulator. Quantitative power-performance analysis is performed at slow-slow (SS), typical-typical (TT) and fast-fast (FF) corners clocked at 50 KHz for temperature ranging from 25̊C to 120̊C. For a supply voltage 0.3V, all the adders had the least PDP. Using 0.3V as the supply voltage, multi threshold voltage and forward body biasing techniques were applied to
further improve the performance of the adders. The PDP obtained using the forward body biasing technique shows an effective improvement compared to high threshold voltage and multi threshold voltage techniques. The forward biasing technique maintains a balance between delay reduction and increase in average power, thus reducing the power delay product when compared to the other two techniques.
AN ULTRA-LOW POWER ROBUST KOGGESTONE ADDER AT SUB-THRESHOLD VOLTAGES FOR IMPL...VLSICS Design
The growing demand for energy constrained applications and portable devices have created a dire need for
ultra-low power circuits. Implantable biomedical devices such as pacemakers need ultra-low power
circuits for a better battery life for uninterrupted biomedical data processing. Circuits operating in subthreshold
region minimize the energy per operation, thus providing a better platform for energy
constrained implantable biomedical devices. This paper presents 8, 16 and 32-bit ultra-low power robust
Kogge-Stone adders with improved performance. These adders operate at subthreshold supply voltages
which can be used for low power implantable bio-medical devices such as pacemakers. To improve the
performance of these adders in sub-threshold region, forward body bias technique and multi-threshold
transistors are used. The adders are designed using NCSU 45nm bulk CMOS process library and the
simulations were performed using HSPICE circuit simulator. Quantitative power-performance analysis is
performed at slow-slow (SS), typical-typical (TT) and fast-fast (FF) corners clocked at 50 KHz for
temperature ranging from 25̊C to 120̊C. For a supply voltage 0.3V, all the adders had the least PDP. Using
0.3V as the supply voltage, multi threshold voltage and forward body biasing techniques were applied to
further improve the performance of the adders. The PDP obtained using the forward body biasing
technique shows an effective improvement compared to high threshold voltage and multi threshold voltage
techniques. The forward biasing technique maintains a balance between delay reduction and increase in
average power, thus reducing the power delay product when compared to the other two techniques.
GENERIC SYSTEM VERILOG UNIVERSAL VERIFICATION METHODOLOGY BASED REUSABLE VERI...VLSICS Design
In this paper, we present Generic System Verilog Universal Verification Methodology based Reusable Verification Environment for efficient verification of Image Signal Processing IP’s/SoC’s. With the tight schedules on all projects it is important to have a strong verification methodology which contributes to First Silicon Success. Deploy methodologies which enforce full functional coverage and verification of corner cases through pseudo random test scenarios is required. Also, standardization of verification flow is needed. Previously, inside imaging group of ST, Specman (e)/Verilog based Verification Environment for IP/Subsystem level verification and C/C++/Verilog based Directed Verification Environment for SoC Level Verification was used for Functional Verification. Different Verification Environments were used at IP
level and SoC level. Different Verification/Validation Methodologies were used for SoC Verification across multiple sites. Verification teams were also looking for the ways how to catch bugs early in the design cycle? Thus, Generic System Verilog Universal Verification Methodology (UVM) based Reusable Verification Environment is required to avoid the problem of having so many methodologies and provides a standard unified solution which compiles on all tools.
SIMULTANEOUS OPTIMIZATION OF STANDBY AND ACTIVE ENERGY FOR SUB-THRESHOLD CIRC...VLSICS Design
Increased downscaling of CMOS circuits with respect to feature size and threshold voltage has a result of
dramatically increasing in leakage current. So, leakage power reduction is an important design issue for
active and standby modes as long as the technology scaling increased. In this paper, a simultaneous active
and standby energy optimization methodology is proposed for 22 nm sub-threshold CMOS circuits. In the
first phase, we investigate the dual threshold voltage design for active energy per cycle minimization. A
slack based genetic algorithm is proposed to find the optimal reverse body bias assignment to set of noncritical paths gates to ensure low active energy per cycle with the maximum allowable frequency at the
optimal supply voltage. The second phase, determine the optimal reverse body bias that can be applied to
all gates for standby power optimization at the optimal supply voltage determined from the first phase.
Therefore, there exist two sets of gates and two reverse body bias values for each set. The reverse body bias
is switched between these two values in response to the mode of operation. Experimental results are
obtained for some ISCAS-85 benchmark circuits such as 74L85, 74283, ALU74181, and 16 bit RCA. The
optimized circuits show significant energy saving ranged (from 14.5% to 42.28%) and standby power
saving ranged (from 62.8% to 67%).
IMPLEMENTATION OF LOW POWER ADIABATIC SRAMVLSICS Design
In the featuring VLSI era, compact electronic devices are popular. The reliability and durability of such compact devices relies on low power utilization. The purpose of this project was to implement a low power adiabatic Static Random Access Memory (SRAM), with the following objectives - To reduce the power waste by means of stepwise charging using tank capacitors which is an adiabatic way of generating power
clock. This method is capable of recuperating the electrical energy back to the source. Further to examine the Static Noise Margin (SNM) – a parameter which gives detailed information about the cell stability – in
contrast with conventional 6T, 7T and 8T topologies of SRAM under 180 nm technology. Finally, SNM variations with respect to process parameters are also discussed. All the implementations and analysis were made using CADENCE tool and MATLAB tool.
IMPLEMENTATION OF LOW POWER ADIABATIC SRAMVLSICS Design
In the featuring VLSI era, compact electronic devices are popular. The reliability and durability of such compact devices relies on low power utilization. The purpose of this project was to implement a low power adiabatic Static Random Access Memory (SRAM), with the following objectives - To reduce the power waste by means of stepwise charging using tank capacitors which is an adiabatic way of generating power
clock. This method is capable of recuperating the electrical energy back to the source. Further to examine the Static Noise Margin (SNM) – a parameter which gives detailed information about the cell stability – in contrast with conventional 6T, 7T and 8T topologies of SRAM under 180 nm technology. Finally, SNM
variations with respect to process parameters are also discussed. All the implementations and analysis were made using CADENCE tool and MATLAB tool.
Low power architecture of logic gates using adiabatic techniquesnooriasukmaningtyas
The growing significance of portable systems to limit power consumption in ultra-large-scale-integration chips of very high density, has recently led to rapid and inventive progresses in low-power design. The most effective technique is adiabatic logic circuit design in energy-efficient hardware. This paper presents two adiabatic approaches for the design of low power circuits, modified positive feedback adiabatic logic (modified PFAL) and the other is direct current diode based positive feedback adiabatic logic (DC-DB PFAL). Logic gates are the preliminary components in any digital circuit design. By improving the performance of basic gates, one can improvise the whole system performance. In this paper proposed circuit design of the low power architecture of OR/NOR, AND/NAND, and XOR/XNOR gates are presented using the said approaches and their results are analyzed for powerdissipation, delay, power-delay-product and rise time and compared with the other adiabatic techniques along with the conventional complementary metal oxide semiconductor (CMOS) designs reported in the literature. It has been found that the designs with DC-DB PFAL technique outperform with the percentage improvement of 65% for NOR gate and 7% for NAND gate and 34% for XNOR gate over the modified PFAL techniques at 10 MHz respectively.
IMPLEMENTATION OF LOW POWER ADIABATIC SRAMVLSICS Design
In the featuring VLSI era, compact electronic devices are popular. The reliability and durability of such compact devices relies on low power utilization. The purpose of this project was to implement a low power adiabatic Static Random Access Memory (SRAM), with the following objectives - To reduce the power waste by means of stepwise charging using tank capacitors which is an adiabatic way of generating power clock. This method is capable of recuperating the electrical energy back to the source. Further to examine the Static Noise Margin (SNM) – a parameter which gives detailed information about the cell stability – in contrast with conventional 6T, 7T and 8T topologies of SRAM under 180 nm technology. Finally, SNM variations with respect to process parameters are also discussed. All the implementations and analysis were made using CADENCE tool and MATLAB tool.
1. P. Ashok Kumar, B. Vijaya Bhaskhar / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 2, Issue4, July-August 2012, pp.1867-1870
Design Of Adiabatic Logic Based Low Power Carry Select Adder
P. ASHOK KUMAR, B. VIJAYA BHASKHAR
Department of ECE, St. Theresa College of Engg. and Tech., Andhra Pradesh, India
Associate Professor, Department of ECE, St. Theresa College of Engg. and Tech., Andhra Pradesh, India
ABSTRACT
Adders are of fundamental importance in In both Lynch-Swartzlander’s and Kantabutra’s
a wide variety of digital systems. Many fast adders adders the sum bits are computed by means of carry-
exist, but adding fast using low area and power is select blocks, which are able to perform their
still challenging. This paper presents a new bit operations in parallel with the carry-tree.
block structure that computes propagate signals This paper presents two new families of
called “carry strength” in a ripple fashion. Several adders, both based on a new bit carry Select &
new adders based on the new carry select Adder adiabatic structure that computes propagate signals
structure are proposed. Comparison with well- called “carry-strength” in a ripple fashion. The first
known conventional adders demonstrates that the family of adders is a family of new carry-select
usage of carry-strength signals allows high-speed adders that are significantly faster than traditional
adders to be realised at significantly lower cost carry-select adders while not much larger. The
and consuming lower power than previously second family of adders is a family of hybrid look-
possible. As well as in this paper we are ahead adders similar to those presented in [5, 6] but
concentrating on the heat dissipation & we are significantly smaller and still comparable in speed.
reducing the current using adiabatic logic.
II. EVALUATION METHODOLOGY
Keywords – Adiabatic, Application Specific In our new type of carry-select adder, the
Integrated Circuit (ASIC), Area Efficient, CSLA, new block structure eliminates the delay due to the
Low Power. rippling at the end of the life of a long-range carry
signal. The main idea is that for each bit position k in
a block Bj we compute whether the carry-in to
position k comes from the carry-in to block Bj, or
I. INTRODUCTION whether this carry is internally generated in block Bj.
The importance of a fast, low-cost binary To this purpose we will use a new type of bit block,
adder in a digital system is difficult to overestimate. in which we will compute propagate signals that start
Not only are adders used in every arithmetic at the LSB of the block and end at every bit position.
operation, they are also needed for computing the We find it helpful to call the complements of these
physical address in virtually every memory fetch “carry-strength” signals, because they indicate for
operation in most modern CPUs. Adders are also each bit position whether the carry-in to that position
used in many other digital systems including originates within the same bit block.
telecommunications systems in places where a full- In basic arithmetic computation, adder still
fledged CPU would be superfluous. Many styles of plays an important role though many people focus on
adders exist. Ripple adders are the smallest but also more complex computation such as multiplier,
the slowest. More recently, carry-skip adders [1, 2, 3] divider, cordic circuits. Although several algorithms
are gaining popularity due to their high speed and and architectures are implemented in literature, there
relatively small size. Normally, in an N-bit carry-skip is not a general architecture for measuring
adder divided into a proper number of M-bit blocks performance equally. Much architecture is tested
[1, 4], a long-range carry signal starts at a generic under different conditions which possibly result in
block Bi, rippling through some bits in that block, variant performance even implemented with the same
then skips some blocks, and ends in a block Bj. If the algorithm.
carry does not end at the LSB of Bj then rippling CLA is proved to have good performance
occurs in that block and an additional delay is needed using in high speed adder, so in many papers this
to compute the valid sum bits. Carry-look-ahead and architecture are used commonly. STCLA – Spanning
carry-select adders [1] are very fast but far larger and Tree Using CLA uses a tree of 4-bit Manchester
consume much more power than ripple or carry-skip Carry-Look ahead chains (MCC) to generate carry
adders. Two of the fastest known addition circuits are for different bit position. RCLCSA – Recursive
the Lynch-Swartzlander’s [5] and Kantabutra’s [6] CLA/CSA Adder uses the same conception as
hybrid carry-look-ahead adders. They are based on STCLA except the lengths of its carry chains are
the usage of a carry tree that produces carries into variant, not fixed. HSAC – High Speed Adder Using
appropriate bit positions without back propagation. In CLA uses Ling’s adder which solves the transition of
order to obtain the valid sum bits as soon as possible, carry propagation delay.
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2. P. Ashok Kumar, B. Vijaya Bhaskhar / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 2, Issue4, July-August 2012, pp.1867-1870
Adder using different implementation is the increasing with the clock frequency. The adiabatic
most critical issue. For example, STCLA and technique prevents such losses: the charge does not
RCLCSA use dynamic CMOS while HSAC uses owe from the supply voltage to the load capacitance
static CMOS. Here, we want to implement a general and then to ground, but it owes back to a trapezoidal
architecture for measuring this three different or sinusoidal supply voltage and can be reused. Just
algorithm which means we can use both dynamic losses due to the resistance of the switches needed for
CMOS and static CMOS to implement these the logic operation still occur. In order to keep these
algorithms for equal comparison. At last, I will offer losses small, the clock frequency has to be much
my new architecture improved from the original lower than the technological limit. In the literature, a
paper. multitude of adiabatic logic families are proposed.
Let me talk about the original Each different implementation shows some particular
implementation. It’s based on the Adiabatic adder. advantages, but there are also some basic drawbacks
But it takes advantage of the characteristics of CMOS for these circuits. The goal of this paper is to compare
circuit. Generally, we don’t use “bar” (inverted) as different adiabatic logic families and to investigate
we conduct every equation . But in reality, “bar” is their robustness against technological parameter
automated added at the output of logic circuits. So, variations. For this purpose three adiabatic logic
they use this special characteristic to reduce the carry families are evaluated and the impact of parameter
propagation time variations on the power dissipation is determined.
Both intertie (and global) and intra-die (or local)
III. POSITIVE FEEDBACK ADIABATIC LOGIC parameter variations of different components in the
The structure of PFAL logic is shown in Fig. same sub-circuit are considered. The most important
1. Two n-trees realize the logic functions. This logic factor is the threshold voltage variation, especially
family also generates both positive and negative for sub-micrometer processes with reduced supply
outputs. The two major differences with respect to voltage. This was also found for low voltage CMOS
ECRL are that the latch is made by two pMOSFETs circuits, cf., where the fundamental yield factor was
and two nMOSFETs, rather than by only two the gate delay variation (in CMOS the power
pMOSFETs as in ECRL, and that the functional dissipation is not significantly dependent on the
blocks are in parallel with the transmission threshold voltage). For adiabatic circuits the timing
pMOSFETs. Thus the equivalent resistance is smaller conditions are not critical, because the clock
when the capacitance needs to be charged. The ratio frequency is particularly low, and therefore the
between the energy needed in a cycle and the outputs can always follow the clocked supply
dissipated one can be seen in Fig.3. During the voltage. Here the yield critical requirement is the
recovery phase, the loaded capacitance gives back power dissipation that has a very low nominal value.
energy to the power supply and the supplied energy Hence it exhibits large relative deviations due to
decreases. parameter variations that can lead to the violation of
the specifications.
The general PFAL gate consists of a two
cross coupled inverters and two functional blocks F
and F’ (complement of F) driven by normal and
complemented inputs which realizes both normal and
complemented outputs. Both the functional blocks
implemented with n channel MOS transistors. The
equations used to implement PFAL adder and the
corresponding sum and carry implementations.
The logical organization of conventional and
adiabatic adders is constructed by the replication of 2
and 4, 4bit blocks for %bit and 16-bit adder,
respectively. Each 4bit block may be viewed as
Fig. 1 Basic Schematic of PFAL consisting of a carry unit, a sum generation unit, and
a sum selection unit. (In practice, the three parts are
of course not necessarily so distinctly separated.) The
IV. POWER DISSIPATION IN ADIABATIC
carries and both types of sum bits are produced using
LOGIC GATES look-ahead functions as much as possible. The
A limiting factor for the exponentially adiabatic adder results after the substitution of the
increasing integration of microelectronics is conventional CMOS adder’s blocks with the
represented by the power dissipation. Though CMOS corresponding adiabatic. Regarding the delay for an
technology provides circuits with very low static n-bit adiabatic carry select adder, which is
power dissipation, during the switching operation constructed by mbit blocks (m<n), we obtain:
currents are generated, due to the discharge of load
capacitances that cause a power dissipation tdelay = 2t+N(2tinv+t)
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Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 2, Issue4, July-August 2012, pp.1867-1870
where 2t, is the delay from the computation of the Fig.3 PFAL Carry Block
partial sum P, and Gi and, N(t+2tinv) with N=n/m,
the delay of carry propagation through the m-bit
blocks. The design of this adder involved rethinking
of the circuit according to the principle of the
adiabatic switching and no changes were held in the
above equations. Also, to best of our knowledge a
similar adiabatic conditional sum adder hasn’t been
introduced until now. Finally, following similar
substitutions, for the conditional sum adder whose
structure resembles that of carry select adder, we can
result in another low power adiabatic adder.
The schematic and simulated waveform of
the carry select adder is shown. The energy stored at
output can be retrieved by the reversing the current
source direction during discharging process. Hence
adiabatic switching technique offers the less energy
dissipation in PMOS network and reuses the stored
energy in the output load capacitance by reversing
the current source direction.
Fig.4 Proposed Adiabatic CSA
Fig.2 PFAL Sum Block
Fig.5 Proposed PFAL CSA Layout with area
Fig.6 Proposed Circuit Power Results
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4. P. Ashok Kumar, B. Vijaya Bhaskhar / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 2, Issue4, July-August 2012, pp.1867-1870
V. Conclusion and block carry-look-ahead adders”, Proc.
The new implementation is based on the of Int’l Symposium on Computer
original architecture, so it can be used in both static Arithmetic,1991, pp.154-164.
CMOS and dynamic CMOS circuits. And through [4]. NAGENDRA, C., IRWIN, M.J., OWENS, R.M.:
this architecture, we can reduce power and area “Area-time-power tradeoffs in parallel
consumption but sacrifice some timing (which can be adders”, IEEE Trans. CAS-II, 43, (10), pp.
neglected). By this implementation, we prove that the 689-702.
new architecture is really better than the traditional [5]. T. LYNCH, E.E. SWARTZLANDER, “A
HSAC. After a brief review of the literature, we spanning-tree carry-look-ahead adder”,
realize that improving adder is very difficult because IEEE Trans. on Comp., Vol. 41, n°8, Aug.
of the transistor level. If we want to get higher 1992.
performance we must reduce the complexity in [6]. KANTABUTRA, “A RECURSIVE CARRY-LOOK
transistor level. AHEAD/CARRY-SELECT HYBRID ADDER”,
IEEE TRANS. ON COMP., VOL. 42, N°12, DEC.
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