The quantum-dot cellular automata (QCA) has more advantages than CMOS regarding area and power. This
work targets a conservative reversible comparator and its realization in QCA. In this work, we construct a
conservative reversible comparator with an optimal value of reversible metrics. In state to design, three conservative
reversible gates, namely PPC, PPNG-1 and PPNG-2 (PP = parity-preserving, C = comparator, N = new,
G = gate), are proposed. Furthermore, the quantum equivalent of 1-bit and 2-bit comparator is presented. The
proposed concept has been implemented through an algorithm for the n-bit comparator. Also, PPC workability
is tested in QCA. The PPC has been performing 1-bit comparator result with minimum area, cell complexity,
and latency, which is found to be 0.52 m2, 387 and 1 respectively. In addition, the complete energy dissipation
analysis to explore such as a thermal layout map of PPC is also presented in this paper. Further, average
energy dissipation v’s kink energy, maximum energy dissipation v’s kink energy, minimum energy dissipation
v’s kink energy and average output node polarization v’s temperature are provided in this paper. The proposed
comparator forwards an improved ratio of 33.33% in gate count and ranging from 27.27% to 29.35% in garbage
outputs than its counterparts circuits, which ensure more scalable.
The CMOS faces challenges related to the increment in leakage-current to power-consumption. QCA is a promising alternative to overcome these challenges successfully. On the other hand, reversible logic plays a significant role in quantum-computing. Keeping this technique in mind, a conservative-reversible flip flops and counter are explored here which will bring QCA and reversible computing together in a singleplatform. In synthesizing, a reversible-conservative-quantum-cellular-automata (R-CQCA) is proposed. The proposed D, T, JK and dual-edge master-slave flip-flops advocate an improvement of 20%, 46.6%,
50%, and 36.66% respectively than its counterpart in quantum-cost. Further, the 100% fault-coverage
by stuck-fault is framed in R-CQCA, which can be useful for a tester to maintain data-integrity. Also, the R-CQCA layout is implemented in QCA, which achieve some parameters such as cell-complexity of 177, leakage-energy-dissipation of 0.1055 eV, and size of 0.24 mm2. Moreover, R-CQCA is better than FRG, RM, PPRG and MX-cqca regarding QCA-primitives are reported here.
SIMULTANEOUS OPTIMIZATION OF STANDBY AND ACTIVE ENERGY FOR SUB-THRESHOLD CIRC...VLSICS Design
Increased downscaling of CMOS circuits with respect to feature size and threshold voltage has a result of dramatically increasing in leakage current. So, leakage power reduction is an important design issue for active and standby modes as long as the technology scaling increased. In this paper, a simultaneous active and standby energy optimization methodology is proposed for 22 nm sub-threshold CMOS circuits. In the first phase, we investigate the dual threshold voltage design for active energy per cycle minimization. A
slack based genetic algorithm is proposed to find the optimal reverse body bias assignment to set of noncritical
paths gates to ensure low active energy per cycle with the maximum allowable frequency at the optimal supply voltage. The second phase, determine the optimal reverse body bias that can be applied to all gates for standby power optimization at the optimal supply voltage determined from the first phase.
Therefore, there exist two sets of gates and two reverse body bias values for each set. The reverse body bias is switched between these two values in response to the mode of operation. Experimental results are obtained for some ISCAS-85 benchmark circuits such as 74L85, 74283, ALU74181, and 16 bit RCA. The optimized circuits show significant energy saving ranged (from 14.5% to 42.28%) and standby power
saving ranged (from 62.8% to 67%)
Novel Tree Structure Based Conservative Reversible Binary Coded Decimal Adder...VIT-AP University
Reversible logic has been recognized as one of the most promising technique for the realization of the quantum circuit. In this paper, a cost effective conservative, reversible binary coded decimal
(BCD) adder is proposed for the quantum logic circuit. Towards the realization of BCD adder, few novel gates, such as Half-Adder/Subtraction (HAS-PP), Full-Adder/Subtraction (FAS-PP) and Overflow-detection (OD-PP) based on parity preserving logic are synthesized which incurs 7, 10 and
13 quantum cost respectively. Coupling these gates a novel tree-based methodology is proposed to
implement the required BCD Adder. Also, the BCD adder design has been optimized to achieve the optimum value of quantum cost. In addition, the proposed BCD circuit is extended to n-bit adder using replica based techniques. Experimental result establishes the novelty of the proposed logic,
which outperforms the conventional circuits in terms of logic synthesis and testability. The limitation
of detecting the missing gate and missing control point of the quantum circuit of overflow detection
is finally tackled this work by the proposed OD-PP with the application of the minimum test vector. In addition, reversible circuits of control inputs based testable master-slave D-FF is intended. The noted work on the testable sequential circuit presented here is to develop circuit using minimum test vectors and can find diverse application in the testing paradigm
A novel vedic divider based crypto-hardware for nanocomputing paradigm: An ex...VIT-AP University
Restoring and non-restoring divider has become widely applicability in the era of digital computing application due to its computation speed. In this paper, we have proposed the design of divider of different architecture for the computation of Vedic sutra based. The design of divider in the Vedic mode results in
high computation throughput due to its replica architecture, where latency is minimized in each of the replica stages. The proposed novel divider based symmetric key crypto-hardware architecture for lightweight embedded devices and the results obtained for this architecture by the analysis using the QCADesigner tool. For the physical environment in QCA computing paradigm are achieved through optimization the
architecture of cell by using the robust design computing architecture. For the extended perspective of lower
divider to higher divider and to synthesize, target outcomes by using efficient architecture.
Low-Cost Synthesis Approach for Reversible Authenticator Circuits in QCA Envi...VIT-AP University
Quantum-dot Cellular Automata (QCA) based reversible logic circuit has an enormous benefit over CMOS based logic circuit. As a promising technology for Nanoelectronics computing, reversible-QCA has gained more and more attention from researchers around the world. In this paper, a reversible authenticator circuit based on QCA was implemented. This article presents a Nano-authenticator circuit to verify the authenticated and unauthenticated inputs. The proposed QCA designs have been implemented in a different manner from existing designs, which are primarily based on a coplanar design approach. The efficiency of QCA design has been investigated based on parameters such as cell count, area, and latency. Furthermore, missing an additional cell defect of the reversible authenticator has been analyzed, and covers the fault tolerance of 60.41% and 75%, respectively. In addition, the proposed Feynman gate in QCA environment achieves 76.35% area, 12.5% cell count and 95.55% average energy dissipation improvement as compared to the existing layout. Moreover, the new reversible authentication circuit achieves 87.75% cost and 43.54% area improvement in comparison with the previous state-of-art design.
Programmable reversible logic is growing for a potential logic design type
concerning execution around advanced nanotechnology as well as quantum computing
with minimum effect upon circuit temperature production. Current improvements in
reversible logic utilizing additionally quantum computer calculations permit enhanced
computer structure plus arithmetical logic unit layouts. Since reversible circuits
continue to be fairly unique, the most significant study effect is found on the synthesis
of these circuits. Quantum-dot cellular automata (QCA) can be a promising part of
investigating at reversible computing. QCA-based design of the reversible 1-bit full
adder is using the Toffoli and Feynman gates have been achieved in this study. We
develop an improved reversible full adder with overflow detection to enhance
reliability. This component promises to complete the fundamental mathematical
functions of addition, subtraction alongside overflow detection, comparison, along with
logic procedures such as significance. Thus our design is very efficient and versatile
alongside lower quantity of lines as well as quantum cost. This work understands and
nurtures the necessity of reversible full adder for future revolutionary computing
technologies. In this paper, a reversible 1-bit full adder is proposed and compared with
other reversible full adders. Proposed gate performs better than existing methods and
ensures maximum logical operations like the full adder, full with less quantum cost
where other existing gates are not viable.
Adiabatic Logic Based Low Power Carry Select Adder for future TechnologiesIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
Implementation of Effective Code Converters using Reversible Logic Gates IJERA Editor
The development in the field of nanometer technology leads to minimize the power consumption of logic
circuits. Reversible logic design has been one of the promising technologies gaining greater interest due to less
dissipation of heat and low power consumption. In the digital design, the code converters are widely used
process. So, the reversible logic gates and reversible circuits for realizing code converters like as Binary to
Gray code, Gray to Binary code, BCD to Excess 3 code, Excess 3 to BCD codes using reversible logic gates is
proposed. Designing of reversible logic circuit is challenging task, since not enough number of gates are
available for design. Reversible processor design needs its building blocks should be reversible in this view the
designing of reversible code converters became essential one. In the digital domain, data or information is
represented by a combination of 0’s and 1’s. A code is basically the pattern of these 0’s and 1’s used to
represent the data. Code converters are a class of combinational digital circuits that are used to convert one type
of code in to another. The proposed design leads to the reduction of power consumption compared with
conventional logic circuits
The CMOS faces challenges related to the increment in leakage-current to power-consumption. QCA is a promising alternative to overcome these challenges successfully. On the other hand, reversible logic plays a significant role in quantum-computing. Keeping this technique in mind, a conservative-reversible flip flops and counter are explored here which will bring QCA and reversible computing together in a singleplatform. In synthesizing, a reversible-conservative-quantum-cellular-automata (R-CQCA) is proposed. The proposed D, T, JK and dual-edge master-slave flip-flops advocate an improvement of 20%, 46.6%,
50%, and 36.66% respectively than its counterpart in quantum-cost. Further, the 100% fault-coverage
by stuck-fault is framed in R-CQCA, which can be useful for a tester to maintain data-integrity. Also, the R-CQCA layout is implemented in QCA, which achieve some parameters such as cell-complexity of 177, leakage-energy-dissipation of 0.1055 eV, and size of 0.24 mm2. Moreover, R-CQCA is better than FRG, RM, PPRG and MX-cqca regarding QCA-primitives are reported here.
SIMULTANEOUS OPTIMIZATION OF STANDBY AND ACTIVE ENERGY FOR SUB-THRESHOLD CIRC...VLSICS Design
Increased downscaling of CMOS circuits with respect to feature size and threshold voltage has a result of dramatically increasing in leakage current. So, leakage power reduction is an important design issue for active and standby modes as long as the technology scaling increased. In this paper, a simultaneous active and standby energy optimization methodology is proposed for 22 nm sub-threshold CMOS circuits. In the first phase, we investigate the dual threshold voltage design for active energy per cycle minimization. A
slack based genetic algorithm is proposed to find the optimal reverse body bias assignment to set of noncritical
paths gates to ensure low active energy per cycle with the maximum allowable frequency at the optimal supply voltage. The second phase, determine the optimal reverse body bias that can be applied to all gates for standby power optimization at the optimal supply voltage determined from the first phase.
Therefore, there exist two sets of gates and two reverse body bias values for each set. The reverse body bias is switched between these two values in response to the mode of operation. Experimental results are obtained for some ISCAS-85 benchmark circuits such as 74L85, 74283, ALU74181, and 16 bit RCA. The optimized circuits show significant energy saving ranged (from 14.5% to 42.28%) and standby power
saving ranged (from 62.8% to 67%)
Novel Tree Structure Based Conservative Reversible Binary Coded Decimal Adder...VIT-AP University
Reversible logic has been recognized as one of the most promising technique for the realization of the quantum circuit. In this paper, a cost effective conservative, reversible binary coded decimal
(BCD) adder is proposed for the quantum logic circuit. Towards the realization of BCD adder, few novel gates, such as Half-Adder/Subtraction (HAS-PP), Full-Adder/Subtraction (FAS-PP) and Overflow-detection (OD-PP) based on parity preserving logic are synthesized which incurs 7, 10 and
13 quantum cost respectively. Coupling these gates a novel tree-based methodology is proposed to
implement the required BCD Adder. Also, the BCD adder design has been optimized to achieve the optimum value of quantum cost. In addition, the proposed BCD circuit is extended to n-bit adder using replica based techniques. Experimental result establishes the novelty of the proposed logic,
which outperforms the conventional circuits in terms of logic synthesis and testability. The limitation
of detecting the missing gate and missing control point of the quantum circuit of overflow detection
is finally tackled this work by the proposed OD-PP with the application of the minimum test vector. In addition, reversible circuits of control inputs based testable master-slave D-FF is intended. The noted work on the testable sequential circuit presented here is to develop circuit using minimum test vectors and can find diverse application in the testing paradigm
A novel vedic divider based crypto-hardware for nanocomputing paradigm: An ex...VIT-AP University
Restoring and non-restoring divider has become widely applicability in the era of digital computing application due to its computation speed. In this paper, we have proposed the design of divider of different architecture for the computation of Vedic sutra based. The design of divider in the Vedic mode results in
high computation throughput due to its replica architecture, where latency is minimized in each of the replica stages. The proposed novel divider based symmetric key crypto-hardware architecture for lightweight embedded devices and the results obtained for this architecture by the analysis using the QCADesigner tool. For the physical environment in QCA computing paradigm are achieved through optimization the
architecture of cell by using the robust design computing architecture. For the extended perspective of lower
divider to higher divider and to synthesize, target outcomes by using efficient architecture.
Low-Cost Synthesis Approach for Reversible Authenticator Circuits in QCA Envi...VIT-AP University
Quantum-dot Cellular Automata (QCA) based reversible logic circuit has an enormous benefit over CMOS based logic circuit. As a promising technology for Nanoelectronics computing, reversible-QCA has gained more and more attention from researchers around the world. In this paper, a reversible authenticator circuit based on QCA was implemented. This article presents a Nano-authenticator circuit to verify the authenticated and unauthenticated inputs. The proposed QCA designs have been implemented in a different manner from existing designs, which are primarily based on a coplanar design approach. The efficiency of QCA design has been investigated based on parameters such as cell count, area, and latency. Furthermore, missing an additional cell defect of the reversible authenticator has been analyzed, and covers the fault tolerance of 60.41% and 75%, respectively. In addition, the proposed Feynman gate in QCA environment achieves 76.35% area, 12.5% cell count and 95.55% average energy dissipation improvement as compared to the existing layout. Moreover, the new reversible authentication circuit achieves 87.75% cost and 43.54% area improvement in comparison with the previous state-of-art design.
Programmable reversible logic is growing for a potential logic design type
concerning execution around advanced nanotechnology as well as quantum computing
with minimum effect upon circuit temperature production. Current improvements in
reversible logic utilizing additionally quantum computer calculations permit enhanced
computer structure plus arithmetical logic unit layouts. Since reversible circuits
continue to be fairly unique, the most significant study effect is found on the synthesis
of these circuits. Quantum-dot cellular automata (QCA) can be a promising part of
investigating at reversible computing. QCA-based design of the reversible 1-bit full
adder is using the Toffoli and Feynman gates have been achieved in this study. We
develop an improved reversible full adder with overflow detection to enhance
reliability. This component promises to complete the fundamental mathematical
functions of addition, subtraction alongside overflow detection, comparison, along with
logic procedures such as significance. Thus our design is very efficient and versatile
alongside lower quantity of lines as well as quantum cost. This work understands and
nurtures the necessity of reversible full adder for future revolutionary computing
technologies. In this paper, a reversible 1-bit full adder is proposed and compared with
other reversible full adders. Proposed gate performs better than existing methods and
ensures maximum logical operations like the full adder, full with less quantum cost
where other existing gates are not viable.
Adiabatic Logic Based Low Power Carry Select Adder for future TechnologiesIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
Implementation of Effective Code Converters using Reversible Logic Gates IJERA Editor
The development in the field of nanometer technology leads to minimize the power consumption of logic
circuits. Reversible logic design has been one of the promising technologies gaining greater interest due to less
dissipation of heat and low power consumption. In the digital design, the code converters are widely used
process. So, the reversible logic gates and reversible circuits for realizing code converters like as Binary to
Gray code, Gray to Binary code, BCD to Excess 3 code, Excess 3 to BCD codes using reversible logic gates is
proposed. Designing of reversible logic circuit is challenging task, since not enough number of gates are
available for design. Reversible processor design needs its building blocks should be reversible in this view the
designing of reversible code converters became essential one. In the digital domain, data or information is
represented by a combination of 0’s and 1’s. A code is basically the pattern of these 0’s and 1’s used to
represent the data. Code converters are a class of combinational digital circuits that are used to convert one type
of code in to another. The proposed design leads to the reduction of power consumption compared with
conventional logic circuits
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
A charge recycling three phase dual rail pre charge logic based flip-flopVLSICS Design
Providing resistance against side channel attacks especially differential power analysis (DPA) attacks,
which aim at disclosing the secret key of cryptographic algorithm is one of the biggest challenges of
designers of cryptographic devices. In this paper design of novel data flip-flop compatible with three-phase
dual-rail logic (TDPL), called Charge recycling TDPL flip-flop is investigated. The new flip-flop uses
inverters that uses the charge recycling technique where charge stored on high output node during
evaluation phase is used to partially charge the low output node in subsequent pre-charge phases. As a
result less charge comes from the power supply thus lowering the power consumption. Simulation results in
Cadence Virtuoso 45 nm CMOS process show improvement in power consumption in inverter up to 60%
while CRTDPL flip-flop consumes around 50% less power compared to TDPL flip-flop.
Improving energy efficiency has always been the prime objective of the custom and automated digital circuit design techniques. However, as the field of design automation has matured over the last few decades, there have been no new automated design techniques, that can provide considerable improvements in circuit power, delay. Although emerging nano-devices are expected to replace the existing MOSFET devices, they are far from being as mature as semiconductor devices and their full potential and promises are many years away from being practical. The research described in this dissertation consists of four main parts. First is a new circuit architecture of a differential threshold logic flip-flop called PNAND. The PNAND gate is an edge-triggered multi-input sequential cell whose next state function is a threshold function of its inputs. Second a new approach, called hybridization, that replaces flip-flops and parts of their logic cones with PNAND cells is described. The resulting hybrid circuit, which consists of conventional logic cells and PNANDs, is shown to have significantly less power consumption, smaller area, less standby power and less power variation. Third, a new architecture of a field programmable array, called field programmable threshold logic array (FPTLA), in which the standard lookup table (LUT) is replaced by a PNAND is described. The FPTLA is shown to have as much as 50% lower energy delay product compared to conventional FPGA using well known FPGA modeling tool called VPR. Fourth, a novel clock skewing technique that makes use of the completion detection feature of the differential mode flip-flops is described.
Design and Implementation of Low Power Multiplier Using Proposed Two Phase Cl...IJECEIAES
This paper presents a design and implementation of 2*2 array and 4*4 array multiplier using proposed Two Phase Clocked Adiabatic Static CMOS logic (2PASCL) circuit. The proposed 2PASCL circuit is based on adiabatic energy recovery principle which consumes less power. The proposed 2PASCL uses two sinusoidal power clocks which are 180 0 phase shifted with each other. The measurement result of 2*2 array proposed 2PASCL multiplier gives 80.16 % and 97.67 %power reduction relative to reported 2PASCL and conventional CMOS logic and the measurement result of 4*4 array proposed 2PASCL multiplier demonstrate 32.88 % and 82.02 %power reduction compared to reported 2PASCL and conventional CMOS logic. Another advantage of the proposed circuit is that it gives less power though the number of transistors in proposed and reported 2PASCL circuit is same. From the result we conclude that proposed 2PASCL technology is advantageous to application in low power digital systems, pacemakers and sensors. The circuits are simulated at 180nm technology mode.
Combination of Immune Genetic Particle Swarm Optimization algorithm with BP a...paperpublications3
Abstract:In this paper, merging Immune Genetic Particle Swarm Optimization algorithm (IGPSO) with BP algorithm to optimize BP Neural Network parameter i.e., BPIGPSO amalgamation to solve optimal reactive power dispatch algorithm. The basic perception is that first training BP neural network with IGPSO to find out a comparatively optimal solution, then take the network parameter at this time as the preliminary parameter of BP algorithm to carry out the training, finally searching the optimal solution. The proposed BPIGPSO has been tested on standard IEEE 57 bus test system and simulation results show clearly the better performance of the proposed algorithm in reducing the real power loss.
Keywords:BP neural network, Immune Genetic Particle Swarm Optimization algorithm, Optimal Reactive Power, Transmission loss.
Design of magnetic dipole based 3D integration nano-circuits for future elect...VIT-AP University
Nano Magnetic Logic (NML) has been attracting application in optical computing, nanodevice formation, and low power. In this paper nanoscale architecture such as the decoder, multiplexer, and comparator are implemented on perpendicular-nano magnetic logic (pNML) technology. All these architectures with the superiority of minimum complexity and minimum delay are pointed. The proposed architectures have been designed using pNML in MagCAD tool, simulated with modelsim platform and correctness shown by simulation waveform. The correctness of these designs can be verified easily when Verilog code is generated from MagCAD tool. The performance of the proposed comparator towards default parameters shows the area of 2.4336 μm2 and critical path of 1.5E-7 sec. As a higher order, the realization of a 4-to-1 multiplexer in NML has also been included in this work.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Energy Efficient Design of Multiplexer Using Adiabatic logicIJEEE
the increasing prominence of portable systems and the need to limit the power consumption in very high density VLSI chips have led to rapid and innovative developments in low power design during the recent years. The CMOS technology provides circuits with very low static power dissipation, during the switching operation currents are generated, due to the discharge of load capacitances that cause power dissipation increasing with the clock frequency. The adiabatic technique prevents such losses, the charge does not flow from the supply voltage to the load capacitance and then to ground, but it flows back to a trapezoidal or sinusoidal supply voltage and can be reused.In this paper a low 2:1 multiplexer is designed using positive feedback adiabatic logic. The design is simulated at .12µm technology using Microwind 3.1. Simulated results shows that proposed design saves 38% energy as compare to conventional CMOS design.
High Speed Time Efficient Reversible ALU Based Logic Gate Structure on Vertex...IJERD Editor
Programmable reversible logic is emerging as a prospective logic design style for implementation in modern nanotechnology and quantum computing with minimal impact on circuit heat generation. Recent advances in reversible logic using and quantum computer algorithms allow for improved computer architecture and arithmetic logic unit designs. In this paper, the two novel 4*4 reversible logic gates (MRG and PAOG) are used with minimal delay, and may be configured to produce a variety of logical calculations on fixed output lines based on programmable select input lines. The proposed ALU design is verified and its advantages over the only existing ALU design are quantitatively analyzed. The proposed design is synthesized using Xilinx ISE software and simulated using MODEL SIM 6.5b.
DESIGN OF PARITY PRESERVING LOGIC BASED FAULT TOLERANT REVERSIBLE ARITHMETIC ...VLSICS Design
Reversible Logic is gaining significant consideration as the potential logic design style for implementation
in modern nanotechnology and quantum computing with minimal impact on physical entropy .Fault
Tolerant reversible logic is one class of reversible logic that maintain the parity of the input and the
outputs. Significant contributions have been made in the literature towards the design of fault tolerant
reversible logic gate structures and arithmetic units, however, there are not many efforts directed towards
the design of fault tolerant reversible ALUs. Arithmetic Logic Unit (ALU) is the prime performing unit in
any computing device and it has to be made fault tolerant. In this paper we aim to design one such fault
tolerant reversible ALU that is constructed using parity preserving reversible logic gates. The designed
ALU can generate up to seven Arithmetic operations and four logical operations.
IMPLEMENTATION OF EFFICIENT ADDER USING MULTI VALUE LOGIC TECHNIQUEJournal For Research
The digital logic circuits are restricted for the requirement of interconnections. This difficulty overcomes by using a big set of signals over the same chip area. Multiple-valued logic (MVL) designs contain more importance from that perspective. This paper gives the fabrication of a multiple-valued half adder and full adder circuits. This technique advantageous for large scale circuits due to which large power dissipation with increased speed can lead to the development of extremely low energy circuit’s use for the high performance required for number of applications. Multiple-valued logic (MVL) designs are gaining more advantageous from the design of a multiple-valued half adder and full adder circuits. The presented adders are design in Multiple-Valued voltage-Mode Logic (MV-VML). In quaternary half adder, quaternary logic levels are exploited for the intention of addition. Addition operation is executed with minimum number of gates and less depth of net. The design is targeted for the 0.18 μm CMOS technology. Circuit is design by using Advanced Design System software {ADS software}. In this paper we try to find area, power and speed of the design HAq / FAq without any need of conversion, and compare to existing binary circuits [HAb / FAb].
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Quantum-dot Cellular Automata (QCA) is an alternative innovation to the
Complementary Metal Oxide Semiconductor (CMOS) because CMOS has scaling
limitations that lead to high leakage power. QCA is structured on quantum cells, whose
sizes are on the nanoscale. This component causes faults in QCA circuits. Converting
a code into another that is programmed in logic arrays becomes important in the
physical realization of the circuits. There are many methods to resolve this problem in
circuits. A code converter is a solution to convert one code into another. In this paper,
QCA-based “4-bit binary-to-gray” and “4-bit gray-to-binary code converters” are
suggested. The offered layout prospects to a decrease in energy expenditure and can
be utilized in many fields for shielding data from outsiders and increasing information
flexibility. We executed a relative analysis of the suggested design with present earlier
designs and turned out that the suggested layout is productive on condition that
complexity, cell count, area intake, and clocking. This paper offers a streamlined design
and layout concerning code converters depending on QCA. These structures are
designed with the QCADesigner, simulator and the simulation results are examined.
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A modular approach for testable conservative reversible multiplexer circuit f...VIT-AP University
Quantum technology has an attractive application nowadays for its minimizing the energy dissipation, which is a prominent
part of any system-level design. In this article, the significant module of a multiplexer, an extended to n:1 is framed with
prominent application in the control unit of the processor. The proposed multiplexer modules are framed by the algorithm,
which is extended perspective based. Further, quantum cost and gate count are less to ensure the efficient quantum computing
framed. In addition, the QCA computing framework is an attempt to synthesize the optimal primitives in conservative
reversible multiplexer in nano-electronic confine application. The developed lemmas is framed to prove the optimal parameters
in the reversible circuit. Compared with existing state-of-art-works, the proposed modular multiplexer, the gate count,
quantum cost and unit delay are optimal.
Implementation of Non-restoring Reversible Divider Using a Quantum-Dot Cellul...VIT-AP University
The CMOS-based integrated circuit may scale down to nanometer range. The primary challenge is to further downscale the device and high-energy dissipation. Reversible logic does not dissipate energy and no information loss. In this
way, the state-of-the-art technology such as QCA was forced toward high-speed
computing with negligible energy dissipation in the physical foreground. This work
targets the design of non-restoring reversible divider circuit and its implementation in QCA. We have utilized few 2 × 2 FG and 4 × 4 HNG gates as the block construction and also show the QCA implementation having cost-efficient approach. Further, the divider circuit has synthesized with FG and HNG gates
and QCA implementation. This divider circuit inherits many benefits such as fewer
garbage outputs, reduce quantum cost are achieved, and also reduced QCA primitives
can be improved by using efficient QCA layout scheme. Simulation investigations have been verified by QCA Designer. The proposed non-restoring divider also compares the reversible metrics results with some of other existing works.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
A charge recycling three phase dual rail pre charge logic based flip-flopVLSICS Design
Providing resistance against side channel attacks especially differential power analysis (DPA) attacks,
which aim at disclosing the secret key of cryptographic algorithm is one of the biggest challenges of
designers of cryptographic devices. In this paper design of novel data flip-flop compatible with three-phase
dual-rail logic (TDPL), called Charge recycling TDPL flip-flop is investigated. The new flip-flop uses
inverters that uses the charge recycling technique where charge stored on high output node during
evaluation phase is used to partially charge the low output node in subsequent pre-charge phases. As a
result less charge comes from the power supply thus lowering the power consumption. Simulation results in
Cadence Virtuoso 45 nm CMOS process show improvement in power consumption in inverter up to 60%
while CRTDPL flip-flop consumes around 50% less power compared to TDPL flip-flop.
Improving energy efficiency has always been the prime objective of the custom and automated digital circuit design techniques. However, as the field of design automation has matured over the last few decades, there have been no new automated design techniques, that can provide considerable improvements in circuit power, delay. Although emerging nano-devices are expected to replace the existing MOSFET devices, they are far from being as mature as semiconductor devices and their full potential and promises are many years away from being practical. The research described in this dissertation consists of four main parts. First is a new circuit architecture of a differential threshold logic flip-flop called PNAND. The PNAND gate is an edge-triggered multi-input sequential cell whose next state function is a threshold function of its inputs. Second a new approach, called hybridization, that replaces flip-flops and parts of their logic cones with PNAND cells is described. The resulting hybrid circuit, which consists of conventional logic cells and PNANDs, is shown to have significantly less power consumption, smaller area, less standby power and less power variation. Third, a new architecture of a field programmable array, called field programmable threshold logic array (FPTLA), in which the standard lookup table (LUT) is replaced by a PNAND is described. The FPTLA is shown to have as much as 50% lower energy delay product compared to conventional FPGA using well known FPGA modeling tool called VPR. Fourth, a novel clock skewing technique that makes use of the completion detection feature of the differential mode flip-flops is described.
Design and Implementation of Low Power Multiplier Using Proposed Two Phase Cl...IJECEIAES
This paper presents a design and implementation of 2*2 array and 4*4 array multiplier using proposed Two Phase Clocked Adiabatic Static CMOS logic (2PASCL) circuit. The proposed 2PASCL circuit is based on adiabatic energy recovery principle which consumes less power. The proposed 2PASCL uses two sinusoidal power clocks which are 180 0 phase shifted with each other. The measurement result of 2*2 array proposed 2PASCL multiplier gives 80.16 % and 97.67 %power reduction relative to reported 2PASCL and conventional CMOS logic and the measurement result of 4*4 array proposed 2PASCL multiplier demonstrate 32.88 % and 82.02 %power reduction compared to reported 2PASCL and conventional CMOS logic. Another advantage of the proposed circuit is that it gives less power though the number of transistors in proposed and reported 2PASCL circuit is same. From the result we conclude that proposed 2PASCL technology is advantageous to application in low power digital systems, pacemakers and sensors. The circuits are simulated at 180nm technology mode.
Combination of Immune Genetic Particle Swarm Optimization algorithm with BP a...paperpublications3
Abstract:In this paper, merging Immune Genetic Particle Swarm Optimization algorithm (IGPSO) with BP algorithm to optimize BP Neural Network parameter i.e., BPIGPSO amalgamation to solve optimal reactive power dispatch algorithm. The basic perception is that first training BP neural network with IGPSO to find out a comparatively optimal solution, then take the network parameter at this time as the preliminary parameter of BP algorithm to carry out the training, finally searching the optimal solution. The proposed BPIGPSO has been tested on standard IEEE 57 bus test system and simulation results show clearly the better performance of the proposed algorithm in reducing the real power loss.
Keywords:BP neural network, Immune Genetic Particle Swarm Optimization algorithm, Optimal Reactive Power, Transmission loss.
Design of magnetic dipole based 3D integration nano-circuits for future elect...VIT-AP University
Nano Magnetic Logic (NML) has been attracting application in optical computing, nanodevice formation, and low power. In this paper nanoscale architecture such as the decoder, multiplexer, and comparator are implemented on perpendicular-nano magnetic logic (pNML) technology. All these architectures with the superiority of minimum complexity and minimum delay are pointed. The proposed architectures have been designed using pNML in MagCAD tool, simulated with modelsim platform and correctness shown by simulation waveform. The correctness of these designs can be verified easily when Verilog code is generated from MagCAD tool. The performance of the proposed comparator towards default parameters shows the area of 2.4336 μm2 and critical path of 1.5E-7 sec. As a higher order, the realization of a 4-to-1 multiplexer in NML has also been included in this work.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Energy Efficient Design of Multiplexer Using Adiabatic logicIJEEE
the increasing prominence of portable systems and the need to limit the power consumption in very high density VLSI chips have led to rapid and innovative developments in low power design during the recent years. The CMOS technology provides circuits with very low static power dissipation, during the switching operation currents are generated, due to the discharge of load capacitances that cause power dissipation increasing with the clock frequency. The adiabatic technique prevents such losses, the charge does not flow from the supply voltage to the load capacitance and then to ground, but it flows back to a trapezoidal or sinusoidal supply voltage and can be reused.In this paper a low 2:1 multiplexer is designed using positive feedback adiabatic logic. The design is simulated at .12µm technology using Microwind 3.1. Simulated results shows that proposed design saves 38% energy as compare to conventional CMOS design.
High Speed Time Efficient Reversible ALU Based Logic Gate Structure on Vertex...IJERD Editor
Programmable reversible logic is emerging as a prospective logic design style for implementation in modern nanotechnology and quantum computing with minimal impact on circuit heat generation. Recent advances in reversible logic using and quantum computer algorithms allow for improved computer architecture and arithmetic logic unit designs. In this paper, the two novel 4*4 reversible logic gates (MRG and PAOG) are used with minimal delay, and may be configured to produce a variety of logical calculations on fixed output lines based on programmable select input lines. The proposed ALU design is verified and its advantages over the only existing ALU design are quantitatively analyzed. The proposed design is synthesized using Xilinx ISE software and simulated using MODEL SIM 6.5b.
DESIGN OF PARITY PRESERVING LOGIC BASED FAULT TOLERANT REVERSIBLE ARITHMETIC ...VLSICS Design
Reversible Logic is gaining significant consideration as the potential logic design style for implementation
in modern nanotechnology and quantum computing with minimal impact on physical entropy .Fault
Tolerant reversible logic is one class of reversible logic that maintain the parity of the input and the
outputs. Significant contributions have been made in the literature towards the design of fault tolerant
reversible logic gate structures and arithmetic units, however, there are not many efforts directed towards
the design of fault tolerant reversible ALUs. Arithmetic Logic Unit (ALU) is the prime performing unit in
any computing device and it has to be made fault tolerant. In this paper we aim to design one such fault
tolerant reversible ALU that is constructed using parity preserving reversible logic gates. The designed
ALU can generate up to seven Arithmetic operations and four logical operations.
IMPLEMENTATION OF EFFICIENT ADDER USING MULTI VALUE LOGIC TECHNIQUEJournal For Research
The digital logic circuits are restricted for the requirement of interconnections. This difficulty overcomes by using a big set of signals over the same chip area. Multiple-valued logic (MVL) designs contain more importance from that perspective. This paper gives the fabrication of a multiple-valued half adder and full adder circuits. This technique advantageous for large scale circuits due to which large power dissipation with increased speed can lead to the development of extremely low energy circuit’s use for the high performance required for number of applications. Multiple-valued logic (MVL) designs are gaining more advantageous from the design of a multiple-valued half adder and full adder circuits. The presented adders are design in Multiple-Valued voltage-Mode Logic (MV-VML). In quaternary half adder, quaternary logic levels are exploited for the intention of addition. Addition operation is executed with minimum number of gates and less depth of net. The design is targeted for the 0.18 μm CMOS technology. Circuit is design by using Advanced Design System software {ADS software}. In this paper we try to find area, power and speed of the design HAq / FAq without any need of conversion, and compare to existing binary circuits [HAb / FAb].
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Quantum-dot Cellular Automata (QCA) is an alternative innovation to the
Complementary Metal Oxide Semiconductor (CMOS) because CMOS has scaling
limitations that lead to high leakage power. QCA is structured on quantum cells, whose
sizes are on the nanoscale. This component causes faults in QCA circuits. Converting
a code into another that is programmed in logic arrays becomes important in the
physical realization of the circuits. There are many methods to resolve this problem in
circuits. A code converter is a solution to convert one code into another. In this paper,
QCA-based “4-bit binary-to-gray” and “4-bit gray-to-binary code converters” are
suggested. The offered layout prospects to a decrease in energy expenditure and can
be utilized in many fields for shielding data from outsiders and increasing information
flexibility. We executed a relative analysis of the suggested design with present earlier
designs and turned out that the suggested layout is productive on condition that
complexity, cell count, area intake, and clocking. This paper offers a streamlined design
and layout concerning code converters depending on QCA. These structures are
designed with the QCADesigner, simulator and the simulation results are examined.
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A modular approach for testable conservative reversible multiplexer circuit f...VIT-AP University
Quantum technology has an attractive application nowadays for its minimizing the energy dissipation, which is a prominent
part of any system-level design. In this article, the significant module of a multiplexer, an extended to n:1 is framed with
prominent application in the control unit of the processor. The proposed multiplexer modules are framed by the algorithm,
which is extended perspective based. Further, quantum cost and gate count are less to ensure the efficient quantum computing
framed. In addition, the QCA computing framework is an attempt to synthesize the optimal primitives in conservative
reversible multiplexer in nano-electronic confine application. The developed lemmas is framed to prove the optimal parameters
in the reversible circuit. Compared with existing state-of-art-works, the proposed modular multiplexer, the gate count,
quantum cost and unit delay are optimal.
Implementation of Non-restoring Reversible Divider Using a Quantum-Dot Cellul...VIT-AP University
The CMOS-based integrated circuit may scale down to nanometer range. The primary challenge is to further downscale the device and high-energy dissipation. Reversible logic does not dissipate energy and no information loss. In this
way, the state-of-the-art technology such as QCA was forced toward high-speed
computing with negligible energy dissipation in the physical foreground. This work
targets the design of non-restoring reversible divider circuit and its implementation in QCA. We have utilized few 2 × 2 FG and 4 × 4 HNG gates as the block construction and also show the QCA implementation having cost-efficient approach. Further, the divider circuit has synthesized with FG and HNG gates
and QCA implementation. This divider circuit inherits many benefits such as fewer
garbage outputs, reduce quantum cost are achieved, and also reduced QCA primitives
can be improved by using efficient QCA layout scheme. Simulation investigations have been verified by QCA Designer. The proposed non-restoring divider also compares the reversible metrics results with some of other existing works.
SIMULTANEOUS OPTIMIZATION OF STANDBY AND ACTIVE ENERGY FOR SUB-THRESHOLD CIRC...VLSICS Design
Increased downscaling of CMOS circuits with respect to feature size and threshold voltage has a result of
dramatically increasing in leakage current. So, leakage power reduction is an important design issue for
active and standby modes as long as the technology scaling increased. In this paper, a simultaneous active
and standby energy optimization methodology is proposed for 22 nm sub-threshold CMOS circuits. In the
first phase, we investigate the dual threshold voltage design for active energy per cycle minimization. A
slack based genetic algorithm is proposed to find the optimal reverse body bias assignment to set of noncritical paths gates to ensure low active energy per cycle with the maximum allowable frequency at the
optimal supply voltage. The second phase, determine the optimal reverse body bias that can be applied to
all gates for standby power optimization at the optimal supply voltage determined from the first phase.
Therefore, there exist two sets of gates and two reverse body bias values for each set. The reverse body bias
is switched between these two values in response to the mode of operation. Experimental results are
obtained for some ISCAS-85 benchmark circuits such as 74L85, 74283, ALU74181, and 16 bit RCA. The
optimized circuits show significant energy saving ranged (from 14.5% to 42.28%) and standby power
saving ranged (from 62.8% to 67%).
SIMULTANEOUS OPTIMIZATION OF STANDBY AND ACTIVE ENERGY FOR SUB-THRESHOLD CIRC...VLSICS Design
Increased downscaling of CMOS circuits with respect to feature size and threshold voltage has a result of
dramatically increasing in leakage current. So, leakage power reduction is an important design issue for
active and standby modes as long as the technology scaling increased. In this paper, a simultaneous active
and standby energy optimization methodology is proposed for 22 nm sub-threshold CMOS circuits. In the
first phase, we investigate the dual threshold voltage design for active energy per cycle minimization. A
slack based genetic algorithm is proposed to find the optimal reverse body bias assignment to set of noncritical
paths gates to ensure low active energy per cycle with the maximum allowable frequency at the
optimal supply voltage. The second phase, determine the optimal reverse body bias that can be applied to
all gates for standby power optimization at the optimal supply voltage determined from the first phase.
Therefore, there exist two sets of gates and two reverse body bias values for each set. The reverse body bias
is switched between these two values in response to the mode of operation. Experimental results are
obtained for some ISCAS-85 benchmark circuits such as 74L85, 74283, ALU74181, and 16 bit RCA. The
optimized circuits show significant energy saving ranged (from 14.5% to 42.28%) and standby power
saving ranged (from 62.8% to 67%).
SIMULTANEOUS OPTIMIZATION OF STANDBY AND ACTIVE ENERGY FOR SUB-THRESHOLD CIRC...VLSICS Design
Increased downscaling of CMOS circuits with respect to feature size and threshold voltage has a result of dramatically increasing in leakage current. So, leakage power eduction is an important design issue for active and standby modes as long as the technology scaling increased. In this paper, a simultaneous active and standbyrgy optimization methodology is proposed for 22 nm sub-threshold CMOS circuits. In thefirst phase, we investigate the dual threshold voltage design for active energy per cycle minimization. A slack based genetic algorithm is proposed to find the optimal reverse body bias assignment to set of noncritical paths gates to ensure low active energy per cycle with the maximum allowable frequency at the optimal supply voltage. The second phase, determine the optimal reverse body bias that can be applied to
all gates for standby power optimization at the optimal supply voltage determined from the first phase. Therefore, there exist two sets of gates and two reverse body bias values for each set. The reverse body bias is switched between these two values in response to the mode of operation. Experimental results are obtained for some ISCAS-85 benchmark circuits such as 74L85, 74283, ALU74181, and 16 bit RCA. The optimized circuits show significant energy saving ranged (from 14.5% to 42.28%) and standby power saving ranged (from 62.8% to 67%).
Approach to design a high performance fault-tolerant reversible ALUVIT-AP University
In the digital circuit design, the primary factors are low power and a high packing density. The reversible logic circuit in quantum-dot cellular
automata (QCA) framework is hoped to be effective in addressing the factor of power consumption at nanoscale regime. Fault tolerant circuits are suited of interruption of errors at the outputs. This manuscript focuses the design of ALU in QCA-based and propose new parity preserving gate. It has been introduced that new reversible gate, namely, universal parity preserving gate (UPPG), to
optimise the ALU circuits. An algorithm and lemmas are shown in designing ALU. The ALU generates a number of arithmetic and logical function with using only less architectural complexity. Most importantly circuit design
focuses on optimising the gate count and quantum cost. In addition to optimisation, the workability of UPPG gate is tested by QCA and the simulation result obtained ensures the correctness of the design.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
International Journal of Engineering and Science Invention (IJESI) inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online
This paper investigates about the possibility to reduce power consumption in Neural Network using approximated computing techniques. Authors compare a traditional fixed-point neuron with an approximated neuron composed of approximated multipliers and adder. Experiments show that in the proposed case of study (a wine classifier) the approximated neuron allows to save up to the 43% of the area, a power consumption saving of 35% and an improvement in the maximum clock frequency of 20%.
IJCER (www.ijceronline.com) International Journal of computational Engineerin...ijceronline
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Study and Performance Analysis of MOS Technology and Nanocomputing QCAVIT-AP University
One of the critical issues in VLSI circuit is High Power dissipation. Quantumdot Cellular Automata (QCA) which is widely utilized in nanocomputing era. QCA has Landauer clocked based synthesis approach and it has clocked based
information flow. This manuscript analysis and design a combinational digital circuits in an emerging QCA framework. The design is evaluated and formulated in terms of area, latency and power dissipation. QCA Designer tool has been taken for the design of quantum cell-based combinational circuits
and simulation purpose. Moreover, it is believed based on experimental analysis that the QCA based combination circuits will make a contribution to high computing speed and low power paradigm.
Area-Delay Efficient Binary Adders in QCAIJERA Editor
In this paper, a novel quantum-dot cellular automata (QCA) adder design is presented that decrease the number
of QCA cells compared to previously method designs. The proposed one-bit QCA adder is based on a new
algorithm that requires only three majority gates and two inverters for the QCA addition. A novel 128-bit adder
designed in QCA was implemented. It achieved speed performances higher than all the existing. QCA adders,
with an area requirement comparable with the low RCA and CFA established. The novel adder operates in the
RCA functional, but it could propagate a carry signal through a number of cascaded MGs significantly lower
than conventional RCA adders. In adding together, because of the adopted basic logic and layout strategy, the
number of clock cycles required for completing the explanation was limited. As transistors reduce in size more
and more of them can be accommodated in a single die, thus increasing chip computational capabilities.
However, transistors cannot find much smaller than their current size. The quantum-dot cellular automata
approach represents one of the possible solutions in overcome this physical limit, even though the design of
logic modules in QCA is not forever straightforward.
A Novel Design of 4 Bit Johnson Counter Using Reversible Logic Gatesijsrd.com
In recent years, reversible logic circuits have attracted considerable attention in improving some fields like nanotechnology, quantum computing, cryptography, optical computing and low power design of circuits due to its low power dissipating characteristic. In this paper we proposed the design of 4-bit Johnson counter which uses reversible gates and derived quantum cost, constant inputs, garbage output and number of gates to implement it.
Designing of an Energy-Efficient Nanoelectronics Architecture for Binary Comp...VIT-AP University
Quantum-dot cellular automata is a nanoscale computation circuit design approach which computes bits via charges
among quantum-dot in the quantum cell of QCA. This technology has promises the feature of energy efficient and high
density in the era of high-speed nanotechnology. This article contributes a new nanoscale design of binary comparator
with less latency, area, and clock utilized. The proposed comparator architecture is robust and enjoys wire crossing
without any crossover, which needs only normal and rotated cells. All the simulation results and calculated parameters
are based on the QCADesigner tool. QCAPro tool based approach has been used to perform the energy dissipation
estimation of the new comparator architecture. A better primitives results as compared to state-of-art technology has
been achieved and good contribution in this area.
The impact of quantum computing has been widely recognised in the engineering domain. The age of quantum computing has arrived, and with it comes the ability to easily solve exponential problems. This book is written by me to meet current academic demands. The book is designed to address the most important aspects of the subject of Quantum Computing. The publication of the book "Quantum Computing" is the culmination of numerous years of research and teaching in academia. It is given in a way that is straightforward to comprehend. The undergraduates, and graduate students may all benefit from reading this book. We have given our very best effort to bring you accurate book material.
The book explains the fundamentals of this topic in simple, straightforward language. The most efficient approach to go through this book is to grasp the underlying fundamental as well as mathematical concepts. The chapters are meant to stand on their own. This book is not intended to be theoretical; rather, it will serve to familiarise you with the fundamental of quantum computing, like applications, multiple-qubit systems, quantum state transformations, quantum gates and quantum circuits, tools for quantum computing, bell states, quantum Parallelism, quantum Algorithms: Shor’s Algorithm, Grover’s Algorithm, Quantum Hardware and software, Quantum Cryptography and Security, Quantum Error Rates and Quantum Noise, Quantum Fourier Transform, Quantum Machine Learning and so on.
The model questions and multiple-choice questions that are provided at the end of the book have been chosen to improve readers' understanding, as well as their performance in exams and key employment.
We warmly welcome and would be very appreciative of any comments or recommendations, that will help us enhance the overall quality of the book.
Cost-effective architecture of decoder circuits and futuristic scope in the e...VIT-AP University
The goal of Very Large Scale Integration (VLSI) over the past several decades has been the miniaturisation of chip size, along with increased computing speed and decreased power consumption. Miniaturization of size, high computing speed, and low power consumption does not appear to be able to meet the demand of consumers at this time. Quantum dot cellular automata is a more promising methodology that has the potential to optimise power, speed, and area at the nano-computing scale. In the field of nanocomputing, combinational circuit design has seen a significant amount of research and development effort. This article presents a comprehensive review as well as a proposed design of a decoder that has an accurate clocking mechanism and the best design. In terms of cell count, total area, cell area, area coverage, latency, QCA cost, and quantum cost, the novel 2-to-4 decoder achieves values of 87, 0.10, 0.0281, 28.1, 2.5, 0.625, 0.25, which is better than the prior work. Comparing the 2-to-4 decoder design to a standard design, the improvement is 72.64 %, 80 %, 72.71 %, 28.1 %, 64.28 %, 97,44 and 92.85 % in cell count, total area, cell area, area coverage, latency, QCA cost, and Quantum cost, respectively.
Efficient architecture for arithmetic designs using perpendicular NanoMagneti...VIT-AP University
As the process of scaling down continues at a rapid pace, there is a growing need for an alternative semiconductor device to replace CMOS. One of the alternatives that attracted a lot of attention is called nanomagnetic logic (NML). This is because NML delivers a high device density in addition to a non-volatility of stored information, beyond-CMOS technologies, and device work at room temperature. It is necessary to lower the circuit density and increase the speed of circuits like adders. Using emerging NML logic, we created a full-adder, and ripple carry adder (RCA) with a minimum area. As a result, the invented multilayer-based decimal design makes use of RCA, and full-adder, for innovative 3D topology. We used an NML framework built with perpendicular nanomagnetic (pNML) layers to simulate the characteristics of these devices. With the adder designs that have been offered the latency values are relatively low while performing exhaustive testing. Using pNML technology, a decimal adder has been constructed for the first time in the literature. In addition, simulations are carried out with the help of the Modelsim simulator. During the process of nanomagnetic designing consideration is given to both of these aspects as latency and area. To create an NML circuit, the tool MagCAD is employed. Results are better using the pNML environment-based full adder, RCA and decimal adder.
An in-depth study of the electrical characterization of supercapacitors for r...VIT-AP University
The Energy Storage System (ESS) is geared toward sophisticated systems with increased operating time for a variety of real-time applications such as an electric vehicle, a WSN (Wireless Sensor Network), a Capa bus, and so
on. Its primary focus is on supplying these kinds of systems with additional capacity in recent development, and
this will continue to be its primary focus. Because of their exceptionally high specific power, rapid charging, and
low ESR (Effective Series Resistance), electric double-layer (EDLC) capacitors or supercapacitors are encouraged
for use because they can be integrated more easily with battery technology that can be used in electric vehicles
and other electronic devices. The supercapacitor calls for a precise and accurate characterization in order to
facilitate the development of improved applications and more effective energy storage devices and technologies.
In this article, we studied various supercapacitor electrode components, electrolytic solutions, analogous circuit
models, electrical energy storage properties, and some real-time supercapacitor applications in the automotive,
manufacturing, construction, and consumer electronics industries. In addition, we have discussed on hybrid
material that was just recently developed with the goal of enhancing the conductivity and effectiveness of supercapacitors. Aside from this, we have discussed about the behaviour of supercapacitors in terms of how their behaviour is dependent on current and voltage with detailed analysis.
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Content Addressable Memory Design in 3D pNML for Energy-Aware Sustainable Com...VIT-AP University
As the semiconductor industry strives for downsizing and high speed, it is confronted with
increasing scaling uncertainty as devices decrease to the nanoscale. Nano-magnetic logic (NML) is an alternative approach to synthesize the digital logic circuits with high-density and lowpower
consumption. We introduced an optimal design of content addressable memory (CAM)
memory based on perpendicular nano-magnetic logic (pNML). The main aim of this implementation
is to synthesize CAM memory in terms of latency and other design parameters. The implementation of the design is a multilayer approach, which is optimal. The synthesis approach
and optimization are perfectly scalable across layout construction of designs. Here a new logic gate in pNML technology is designed which is mainly used for matching of two input numbers. According to insight, both memory unit and a matching unit in the pNML are introduced in the state-of-the-artwork for the ¯rst time to synthesize design in high-speed pNML application. MAGCAD tool is used for the design of all the proposed pNML layouts.
Performance Evaluation & Design Methodologies for Automated 32 Bit CRC Checki...VIT-AP University
For design methodology of CRC or cyclic redundancy check is very used technique for error checking and shows the transmission reliability we are using the HDLC block. HDLC block is very useful in data communication these block operated in data link layer. For design methodology of CRC is to generate the CRC polynomial using XOR’s gate and shift register these polynomial are implement on software Xilinx Plan Ahead 13.1 and verify for simulation result for random testing of CRC bit on receiver side same result are obtained to show that it is more reliable.
Sensor Energy Optimization Using Fuzzy Logic in Wireless Sensor NetworkingVIT-AP University
Wireless sensor networks is challenging in that it requires an enormous breadth of knowledge from an enormous variety of disciplines. A lot of study has been done to minimize the energy used in routing and number of protocols has been developed. These protocols can be classified as - Hierarchical, data centric, location based and Network flow protocols. In this paper, we are particularly focusing on hierarchical protocols. In such types of protocols, the energy efficient clusters are formed with a hierarchy of cluster heads. Each cluster has its representative cluster head which is responsible for collecting and aggregating the data from its respective cluster and then transmitting this data to the Base Station either directly or through the hierarchy of other cluster heads. Fuzzy logic has been successfully applied in various areas including communication and has shown promising results. However, the potentials of fuzzy logic in wireless sensor networks still need to be explored. Optimization of wireless sensor networks involve various tradeoffs, for example, lower transmission power vs. longer transmission duration, multi-hop vs. direct communication, computation vs. communication etc. Fuzzy logic is well suited for application having conflicting requirements. Moreover, in WSN, as the energy metrics vary widely with the type of sensor node implementation platform, using fuzzy logic has the advantage of being easily adaptable to such changes.
Novel conservative reversible error control circuits based on molecular QCAVIT-AP University
Quantum-dot cellular automata are a prominent part of the nanoscale regime. They
use a quantum cellular based architecture which enables rapid information process with high
device density. This paper targets the two kinds of novel error control circuits such as Hamming
code, parity generator and checker. To design the HG-PP (HG = Hamming gate, PP = parity
preserving), NG-PP (NG = new gate) are proposed for optimising the circuits. Based on the
proposed gates and a few existing gates, the Hamming code and parity generator and checker
circuits are constructed. The proposed gates have been framed and verified in QCA. The
simulation outcomes signify that their framed circuits are faultless. In addition to verification,
physical reversible is done. The reversible major metrics such as gate count, quantum cost, unit
delay, and garbage outputs, uses best optimisation results compared to counterparts. They can be utilised as a low power error control circuit applied in future communication systems.
Analysis on Fault Mapping of Reversible Gates with Extended Hardware Descript...VIT-AP University
Quantum-dot cellular automata is a modern computing paradigm, conceived in feature of nanometer
scale with high integration density, and significant low power. For the QCA technology, making these
high-density design means an increase in the complexity which in turn leads to growth in the number of faults. The defect model presented in this paper categorized into two types, which include single missing and additional cell considering for QCA fault. Proposed gates have been designed in the
QCA and verified. The proposed Fredkin gate design has been compared with an existing design,
and 43% and 70% improvement in cell count and area respectively are revealed. Also, the Toffoli
design in QCA which achieve some parameters such as cell complexity of 39, and the average fault tolerance of 53.5%. The polarization value for both single cells missing an addition cell missing has been studied to explain the logic signal strength effect physically. A QCA framework for the 3-input
Ex-OR, 2:1 multiplexer, Fredkin, and Toffoli gate for the fault problem in which reliability analysis based on Hardware description language for QCA devices (HDLQ) is discussed and verified on the fault pattern look-up table.
A Novel and Efficient Design for Squaring Units by Quantum-Dot Cellular AutomataVIT-AP University
Quantum cell automata (QCA) are the best possible alternative to the
conventional CMOS technology due to its low power consumption, less area and high-speed operation. This paper describes synthesizable QCA implementation of squaring. Vedic sutras used for squaring are defined over algorithm construction. Based on the concept of the Vedic sutra, this paper has carried out 2-bit square and
4-bit square, projective to affine logic gates construction. Importantly for miniaturization
of devices, the QCA based square is the operation on which the area of
circuits relies on. This means that significantly lower QCA parameters can be used in
the square than in other competitive square circuits such as Wallace, Dadda, serial parallel,
and Baugh-Wooley.
A Redundant Adder Architecture in Ternary Quantum-Dot Cellular AutomataVIT-AP University
Now researchers are moving toward emerging technologies to replace the
conventional CMOS technology. Quantum-dot cellular automata (QCA) are one of
them for high-performance computing circuits. Ternary QCA is one of the finest
research areas in this domain for replacement of binary logic. In this paper, we
proposed a new redundant adder architecture using Ternary QCA technology. Our proposed architecture has 233 numbers of cells with an area of 0.35 μm2. All the proposed ternary logic layouts are implemented in TQCA designer tool.
An Explicit Cell-Based Nesting Robust Architecture and Analysis of Full AdderVIT-AP University
Moving towards micrometre scale to nanometre scale device shrinks down emerging nanometre technology such as quantum-dot cellular automata as a nesting
success. The introduced architecture is robust where the explicit design of full adder
and full subtraction uses for Ex-OR design. A new architecture of Ex-OR based on one majority gate is proposed, which its most optimized architecture and its placement of cells from the novel design. The analysis based on simulation showed that the
introduced Ex-OR and full adder makes only 11 and 46 cells count, respectively. In
proposed Ex-OR design, first output is received with no any latency which can be a
suitable design for implementation of the high-speed full adder design. In addition,
power estimation results are obtained after simulation of proposed designs in QCAPro
tool. Therefore, the novel designs improve the energy dissipation parameters such as mean leakage energy dissipation, mean switching energy dissipation and total energy dissipation 75, 11.28 and 82.19% in comparison with the most robust design in existing.
Concept and Algorithm of Quantum Computing During Pandemic Situation of COVID-19VIT-AP University
We are observing in this pandemic situation of COVID-19 the world in
very challenging and to solve this complex problem in quick time. Today, we are facing a difficult complex problem such as Coronavirus. This Coronavirus affects human life. Quantum computing is the only support that can give us quick results by processing the Coronavirus compound at high computation speed. Whatever present circuits in VLSI domain, we cannot perform the high-speed computation and not tackle the complex case as present COVID-19. In this article, we have been discussed about quantumcomputing era during the pandemic situation ofCOVID-19. Further, this paper presents fundamental about quantum properties such as superpo-
sition, entanglement, and quantum programming tools such as Qiskit (IBM), pyQuil
(Google), ProjectQ (ETH), Revkit, and RCvewier + . We have presented quantum
circuit and its decomposed circuit of such gates as Toffoli, Fredkin, Peres, and new
fault tolerance. In addition, we proposed algorithm as transforming cascade to the
quantumcircuitwhich is extended for verification based.All these concepts presented here will be very useful to researcher, academician, and industry person to tackle this
pandemic situation of COVID-19.
A Novel Parity Preserving Reversible Binary-to-BCD Code Converter with Testab...VIT-AP University
The reversible logic circuit is popular due to its quantum gates involved
where quantum gates are reversible and noted down feature of no information loss.
In this paper, parity preserving reversible binary-to-BCD code converter is
designed, and effect of reversible metrics is analyzed such as gate count, ancilla
input, garbage output, and quantum cost. This design can build blocks of basic
existing parity preserving reversible gates. The building blocks of the code converter
reversible circuit constructed on Toffoli gate based as well as elemental gate
based such as CNOT, C-V, and C-V+ gates. In addition, qubit transition analysis of
the quantum circuit in the regime of quantum computing has been presented. The heuristic approach has been developed in quantum circuit construction and the
optimized quantum cost for the circuit of binary-to-BCD code converter. Logic functions validate the development of quantum circuit. Moving the testability aim
are figured in the quantum logic circuit testing such as single missing gate and single missing control point fault.
Immunizing Image Classifiers Against Localized Adversary Attacksgerogepatton
This paper addresses the vulnerability of deep learning models, particularly convolutional neural networks
(CNN)s, to adversarial attacks and presents a proactive training technique designed to counter them. We
introduce a novel volumization algorithm, which transforms 2D images into 3D volumetric representations.
When combined with 3D convolution and deep curriculum learning optimization (CLO), itsignificantly improves
the immunity of models against localized universal attacks by up to 40%. We evaluate our proposed approach
using contemporary CNN architectures and the modified Canadian Institute for Advanced Research (CIFAR-10
and CIFAR-100) and ImageNet Large Scale Visual Recognition Challenge (ILSVRC12) datasets, showcasing
accuracy improvements over previous techniques. The results indicate that the combination of the volumetric
input and curriculum learning holds significant promise for mitigating adversarial attacks without necessitating
adversary training.
Vaccine management system project report documentation..pdfKamal Acharya
The Division of Vaccine and Immunization is facing increasing difficulty monitoring vaccines and other commodities distribution once they have been distributed from the national stores. With the introduction of new vaccines, more challenges have been anticipated with this additions posing serious threat to the already over strained vaccine supply chain system in Kenya.
Quality defects in TMT Bars, Possible causes and Potential Solutions.PrashantGoswami42
Maintaining high-quality standards in the production of TMT bars is crucial for ensuring structural integrity in construction. Addressing common defects through careful monitoring, standardized processes, and advanced technology can significantly improve the quality of TMT bars. Continuous training and adherence to quality control measures will also play a pivotal role in minimizing these defects.
Industrial Training at Shahjalal Fertilizer Company Limited (SFCL)MdTanvirMahtab2
This presentation is about the working procedure of Shahjalal Fertilizer Company Limited (SFCL). A Govt. owned Company of Bangladesh Chemical Industries Corporation under Ministry of Industries.
TECHNICAL TRAINING MANUAL GENERAL FAMILIARIZATION COURSEDuvanRamosGarzon1
AIRCRAFT GENERAL
The Single Aisle is the most advanced family aircraft in service today, with fly-by-wire flight controls.
The A318, A319, A320 and A321 are twin-engine subsonic medium range aircraft.
The family offers a choice of engines
Event Management System Vb Net Project Report.pdfKamal Acharya
In present era, the scopes of information technology growing with a very fast .We do not see any are untouched from this industry. The scope of information technology has become wider includes: Business and industry. Household Business, Communication, Education, Entertainment, Science, Medicine, Engineering, Distance Learning, Weather Forecasting. Carrier Searching and so on.
My project named “Event Management System” is software that store and maintained all events coordinated in college. It also helpful to print related reports. My project will help to record the events coordinated by faculties with their Name, Event subject, date & details in an efficient & effective ways.
In my system we have to make a system by which a user can record all events coordinated by a particular faculty. In our proposed system some more featured are added which differs it from the existing system such as security.
Final project report on grocery store management system..pdfKamal Acharya
In today’s fast-changing business environment, it’s extremely important to be able to respond to client needs in the most effective and timely manner. If your customers wish to see your business online and have instant access to your products or services.
Online Grocery Store is an e-commerce website, which retails various grocery products. This project allows viewing various products available enables registered users to purchase desired products instantly using Paytm, UPI payment processor (Instant Pay) and also can place order by using Cash on Delivery (Pay Later) option. This project provides an easy access to Administrators and Managers to view orders placed using Pay Later and Instant Pay options.
In order to develop an e-commerce website, a number of Technologies must be studied and understood. These include multi-tiered architecture, server and client-side scripting techniques, implementation technologies, programming language (such as PHP, HTML, CSS, JavaScript) and MySQL relational databases. This is a project with the objective to develop a basic website where a consumer is provided with a shopping cart website and also to know about the technologies used to develop such a website.
This document will discuss each of the underlying technologies to create and implement an e- commerce website.
Overview of the fundamental roles in Hydropower generation and the components involved in wider Electrical Engineering.
This paper presents the design and construction of hydroelectric dams from the hydrologist’s survey of the valley before construction, all aspects and involved disciplines, fluid dynamics, structural engineering, generation and mains frequency regulation to the very transmission of power through the network in the United Kingdom.
Author: Robbie Edward Sayers
Collaborators and co editors: Charlie Sims and Connor Healey.
(C) 2024 Robbie E. Sayers
About
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Technical Specifications
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
Key Features
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface
• Compatible with MAFI CCR system
• Copatiable with IDM8000 CCR
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
Application
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
COLLEGE BUS MANAGEMENT SYSTEM PROJECT REPORT.pdfKamal Acharya
The College Bus Management system is completely developed by Visual Basic .NET Version. The application is connect with most secured database language MS SQL Server. The application is develop by using best combination of front-end and back-end languages. The application is totally design like flat user interface. This flat user interface is more attractive user interface in 2017. The application is gives more important to the system functionality. The application is to manage the student’s details, driver’s details, bus details, bus route details, bus fees details and more. The application has only one unit for admin. The admin can manage the entire application. The admin can login into the application by using username and password of the admin. The application is develop for big and small colleges. It is more user friendly for non-computer person. Even they can easily learn how to manage the application within hours. The application is more secure by the admin. The system will give an effective output for the VB.Net and SQL Server given as input to the system. The compiled java program given as input to the system, after scanning the program will generate different reports. The application generates the report for users. The admin can view and download the report of the data. The application deliver the excel format reports. Because, excel formatted reports is very easy to understand the income and expense of the college bus. This application is mainly develop for windows operating system users. In 2017, 73% of people enterprises are using windows operating system. So the application will easily install for all the windows operating system users. The application-developed size is very low. The application consumes very low space in disk. Therefore, the user can allocate very minimum local disk space for this application.
2. Designing Conservative Reversible N-Bit Binary Comparator for Emerging QCA Nano Circuits Misra et al.
ARTICLE
quantum cost compared to the state of the art circuits.
To the best of our state of the art reviews, there is no such
conservative reversible comparator in QCA computing.
In this paper, we introduce a more scalable version of
the modular approach based conservative reversible com-
parator (CRC). Here, we have separated the CRC into
three modules. The first module, utilize PPC gate, the sec-
ond module utilizes PPPNG-2 and BVPPG and the third
module utilizes PPNG-2. Further, we demonstrate a more
scalable circuit of n-bit CRC. This circuit is motivated by
the same size of the n-bit CRC.5
The major constraints for
this circuit are more gate count, quantum cost and realized
in conventional CMOS technology. The presented CRC in
this article achieves the optimal values of reversible met-
rics such as gate count, garbage outputs, and quantum cost.
In the optimization, there is an achievement of all the met-
rics improves. The primary interest in this work is both
in logic reversible synthesis prospect as well as a physi-
cally reversible prospect. The physical reversibility check-
ing in emerging nanoscale, Quantum cellular automata
(QCA) because reversible logic has prospective application
in logic design in QCA.6
The PPC gate layout in QCA is
forming a 1-bit comparator results with the strong value
of polarization in simulation waveform and only 1 latency
reported here.
In this paper, we attempt to construct a CRC in
QCA framework. The major outlines of this workaround
reversible-QCA circuit can be concise as follows:
• We have proposed scalable conservative reversible gates
(PPC, PPNG-1, and PPNG-2), for reversible computing
application.
• We present the architecture level representation of 1-bit,
2-bit and n-bit CRC around proposed conservative gates.
• We have compared proposed circuit with other n-bit
CRC that used the previous circuit.
• We estimate and analyze the scalability of 2-bit com-
parator than its existing, 33.33% improvement regarding
gate count.
• We implement the smaller robust structure of PPC in
QCA framework. During simulation, the result is ensured
by comparison with the truth table of PPC.
• We dissect the QCA layout of PPC, the similar QCA
layout of the 1-bit comparator is utilized.
• We estimate the gate used with a 1-bit comparator and
present latency of 66.66% over counterparts circuits.
• We dissect the thermal-layout map of PPC using
QCAPro version 1.3. The physical reversibility is trying to
maintain by according to the thermal layout. The design of
the PPC is concluded by physically irreversible, but logi-
cally reversible.
• We extracted the energy dissipation related parameters
from exhaustive studies. To indicate the low power feature
in this work.
• We estimate the average output node cell polarization
value over a different temperature range. By simulation,
setup results proved that average output polarization value
decrease slowly with the increase in the temperature.
The article is organized as follows: Section 2 gives an
overview of the state of the art and the basics of reversible
logic and QCA. Section 3, three new reversible gates are
introduced with minimum quantum cost. Section 4, we
elaborate the circuit of the binary n-bit comparator. Also
details, the algorithm presented. Section 5 presents the
QCA design of PPC gate and details of simulation setup
results. Section 6, elaborate the energy dissipation analy-
sis. Section 7, estimation of temperature versus polariza-
tion is reported. The conclusion and reference are shown
in Sections 8 and 9.
2. BASICS AND STATE-OF-THE-ART
This section includes the basics of reversible logic, con-
servative reversible logic, QCA, and kink energy.
2.1. Reversible Logic Gate
The reversible logic gate has numbers of input signals
equals to the number of output signals and there is
a bijective-mapping between its input and output lines.
In reversible computing technology, minimizing the gate
count, garbage outputs, constant inputs and quantum cost
are main demand of syntheses. The circuit constructed
from reversible gates will be using feedback, acyclic, fan-
outs and loops are not allowed.7
The reversible logic is
adopted with two elucidates as follows:
(a) Logical reversibility: In this amends the mapping of
input to output logic is bijective, means for every dis-
tinct input yields a distinct output logic and inputs can be
retrieved by output logic.
(b) Physical reversibility: The physical reversibility
should run backward without the dissipation of power. The
both links of logical reversibility and physical reversibility
will be established, no heat dissipates.
2.2. Conservative Reversible Logic Gate
The concept of conservative reversible logic is to design,
gates that prevent fault propagation. A reversible gate is
known as conservative (parity preserving) gate, if it pre-
serves two elucidates as follow:
(a) Input vector Iv is mapped with output vector Ov such
that bijective mapping between them.
(b) Input and output hamming weight is the same.
Several conservative reversible gates have been pre-
sented up to now, which can be employed for constructing
the reversible logic circuit.8
The restriction of this type of
gates does not construct the CRC circuits with an optimal
value of reversible metrics. The reversible gates used in
the construction of CRC are existing 5 × 5 BVPPG gate
and some our proposed gates. In this work, one conser-
vative reversible BVPPG gate has been employed and we
will examine them. The BVPPG has five inputs and five
2 J. Nanoeng. Nanomanuf., 6, 1–16, 2016
3. Misra et al. Designing Conservative Reversible N-Bit Binary Comparator for Emerging QCA Nano Circuits
ARTICLE
Fig. 1. Existing CR, BVPPG, (a) Schematic presentation, (b) Quantum equivalent realization, its QC = 10.
outputs.9
The input and output are indicated as IV (A, B,
C, D) and Ov (P, Q, R, S). Schematic of BVPPG is
depicted in Figure 1(a), whereas quantum equivalent real-
ization in Figure 1(b).
2.3. QCA
QCA cells consist of four quantum dots positioned at the
corners of the square-shaped cell and two free electrons
bounded within the cell. In QCA design there is no con-
cept of wire; instead of this, QCA cells are joined to form
a grid-like structure which resembles like a wire. QCA
principle promises lower power because four clock control
the information flow.10
All clock zones (Clock 0, Clock 1,
Clock 2 and Clock 3) must be synchronized, the clock
zone has four phases namely: Release, Relax, Switch and
Hold (Fig. 1(a)). The QCA inverter and buffer signal of
input are synthesized by the alternate placement of cells
by tapping off a normal wire, depicted in Figure 1(b). The
basic QCA structures are the inverter and majority voter
gate (Figs. 1(c, e)). The electron can settle with two stable
polarization (P = −1, Binary logic ‘0’ and P = +1, Binary
logic ‘1’), depicted in Figure 1(d).
2.4. Kink Energy
In the situation, when two adjacent cells have opposite
polarization, energy increases, and that increased energy
is known as kink energy (Always greater than ground
energy). More appropriately, minimum energy is termed
for same polarization state and maximum for different
polarization state.11 12
It is estimated by electrostatic inter-
action between the quantum dots in the adjacent cells.
Mathematically, it is the difference between maximum and
minimum electrostatic energy, drawn in Eq. (1).
Ek = Ea b
Pa=Pb − Ea b
Pa=Pb (1)
QCA cell has four dots that depict four sites, the kink
energy of two adjacent cells ‘a’ and ‘b’ can be drawn in
Eq. (2).
Ekink
a b =
qaqb
4 0 r ri −rj
(2)
The denoted symbol as r = relative permittivity, 0 = free
space permittivity, qa and qb are electronic charges of cells
‘an’ and ‘b’ respectively and ra −rb = Distance between
two cells.
To perform correct functionality, the excitation energy
must be greater than KbT. The number of cells with the
same clocking does not show correct functionality. The
restriction of a number of cells to avoid unexpected kink,
following mathematical Eq. (3) is drawn.
N ≤ eE
kink/KbT (3)
The denoted symbol as N = Number of QCA cells,
Kb = Boltzmann constant, Ekink = Kink energy, and
T = Temperature.
2.5. State-of-the-Art-Work
Reversible logic circuit syntheses have attracted consid-
erable attention in recent years due to its low power.13
Many researchers have covered the optimization of the cir-
cuit from the appearance of gate counts, constant inputs,
garbage outputs and quantum cost. Recently, in Ref. [5];
attractive contributions are caused towards syntheses and
optimization of CRC circuit. Most of the researcher in
Refs. [14–21] used the CMOS technology for simulation
and few;22
used the QCA for such simulation. A proper
circuit construction and the optimal value of reversible
metrics are essential to estimate the performance of a
CRC. In Ref. [5]; researchers have constructed the 2-bit
CRC circuit having 6 gate count, 11 garbage outputs and
Clock3Clock2Clock1Clock0
Switch Hold Release Relax
T/4 T/2 3T/4 T
(a)
(b)
(d)
(e)
I1
I2
I3
OUT
P=‘–1’,
Binary ‘0’
P=‘+1’,
Binary‘1’
450
A
A
A
A’
A’
A’
A’
Input A
Out A’
Out A
(c)
900
900
Fig. 2. Basics of QCA, (a) clocking, (b) wire crossing, (c) inverter,
(d) polarization of cell, (e) majority voter.
J. Nanoeng. Nanomanuf., 6, 1–16, 2016 3
4. Designing Conservative Reversible N-Bit Binary Comparator for Emerging QCA Nano Circuits Misra et al.
ARTICLE
Table I. Preliminaries work on reversible comparator.
Comparator circuit Gates utilized Rlogic+PP Logical+Physical reversible Technology adopted Capacity
[5] AG, FTSEG Both Only logical reversible Conventional CMOS 1-bit, 2-bit, n-bit
[14] PG, CNOT, Only reversible Only logical reversible Missing 1-bit, 2-bit, 3-bit, 4-bit,
8-bit, 16-bit, 64-bit
[16] BJSS, HLNS, FG Only reversible Only logical reversible Conventional CMOS 1-bit, 2-bit, n-bit
[18] RC-I, RC-II, PG,TS-3 Only reversible Only logical reversible Conventional CMOS 1-bit, 2-bit, 8-bit,64-bit
and n-bit
[20] CPG, TVG, F2G Both Only logical reversible Verilog HDL 1-bit, 4-bit
[21] ZRQG, Only reversible Only logical reversible Missing 1-bit, 4-bit, n-bit
[22] TR, FG, Only reversible Both QCA 1-bit
31 quantum cost, which is more optimized. We examined
the circuits in Ref. [5]; and compared with our CRC cir-
cuit, as the attempt was to the optimal value of reversible
metrics such as gate count, garbage outputs, and quan-
tum cost. Thus to the best of our state of the art reviews,
researchers have not yet applied the CRC circuit to QCA
technology. In this section, we are highlighting the state
of the art work with their pros and cons.
2.5.1. Fault-Tolerant Reversible Comparator
In 2015, Bose et al. design a parity-preserving based cir-
cuit of 1-bit, 2-bit, and an n-bit reversible comparator.19
The 2-bit comparator circuit utilizes 6 gate count, 11
garbage output, and 31 quantum cost. Conventional CMOS
technology tests the workability of the circuit with missing
technology nodes.
2.5.2. Reversible Comparator
Initially, a novel reversible comparator was designed
by Thapliyal et al. 2010.4
Its design was resembled
to tree based. The circuit constructed 8-bit and 64-bit,
but it is not a modular approach to constructing n-bit
comparator.
2.5.3. Reversible Comparator
In 2014, Babu et al. designed a compact, low power com-
parator that is composed of 6 numbers of gates, 5 garbage
outputs and 21 quantum cost of the 2-bit comparator and
also designed n-bit comparator, but its design was not
conservative.5
This circuit was mainly depicted with con-
ventional CMOS technology by using Micro wind DSCH-
3.5 tool. The simulation results of 2-bit based comparator
circuit brought forward 0.27 ns delay, 70.5 m2
circuit
area, and 202.58 w power respectively.
2.5.4. Reversible Comparator
In 2014 Qi et al. proposed parity preserving the design
of 4-bit comparator, that utilize 15 gate count, 32 garbage
outputs, and 95 quantum cost.10
The 4-bit comparator cir-
cuit results are validated by Verilog HDL-based on the
coding on Altera Quartus II. The validations and verifica-
tion are normal gate-level.
2.5.5. Reversible Comparator Design Using QCA
Das et al. proposed 1-bit comparator in the QCA
framework;29
in 2015. A 1-bit comparator circuit was
designed in the first attempt by using FG and TR gate
and it’s energy efficient with the high number of reversible
primitives (gate count, garbage outputs, quantum cost) as
well as QCA primitives (clock cycle delay, cell area and
clock utilized). However, the designing approach target
only non-conservative reversible.
Due to the influence of all these works, inspire me
to design CR, comparator circuit and to optimize the
reversible metrics as well as QCA primitives. Further,
the verification of circuits in nano-scale based QCA. To
the best of the state of the art reviews, no such design
of conservative reversible comparator in QCA computing.
The preliminary designs of existing works are presented
in Table I.
3. THE PROPOSED CONSERVATIVE
REVERSIBLE GATES
Reliability, power consumption, high performance and
optimization are essential factors in reversible computing.
In recent conservative, reversible is adopted for the dig-
ital logic circuit. It preserves parity on both sides of the
input and output signals, and drawn significant attention in
response to the data integrity and continue operation.23 24
In this work, a three novel conservative reversible gate
(CRG) is proposed with minimum quantum cost, and set-
ting proper input lines to produce required output lines for
CRC circuit.
3.1. The Proposed PPC Gate
A 5×5 CRG named PPC gate is proposed in this work and
is depicted in Figure 3(a). The corresponding truth table
of PPC is drawn in Table II. It can be confirmed from the
truth table that the bijective mapping established, hence
this gate is reversible. Figure 3(b) presents the quantum
equivalent circuit of PPC. The quantum cost of PPC gate
is 9, since it consists of 6 XOR gates, 2 controlled-V, and
1 controlled-V+
gate. The hardware complexity is as arise
8 +2 .
4 J. Nanoeng. Nanomanuf., 6, 1–16, 2016
5. Misra et al. Designing Conservative Reversible N-Bit Binary Comparator for Emerging QCA Nano Circuits
ARTICLE
Fig. 3. Proposed CR, PPC: (a) Schematic diagram, (b) Quantum equivalent realization.
When programmed the third, fourth and fifth inputs
of the PPC gate as high, low and low respectively. The
required outputs of the PPC will occur.
P = A⊕B⊕1 = A⊕B
Table II. The truth table of the PPC gate.
A B C D E P Q R S T
0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0 0 1
0 0 0 1 0 0 0 1 1 1
0 0 0 1 1 0 0 1 1 0
0 0 1 0 0 1 0 0 0 0
0 0 1 0 1 1 0 0 0 1
0 0 1 1 0 1 0 1 1 1
0 0 1 1 1 1 0 1 1 0
0 1 0 0 0 1 1 1 0 0
0 1 0 0 1 1 1 1 0 1
0 1 0 1 0 1 1 0 1 1
0 1 0 1 1 1 1 0 1 0
0 1 1 0 0 0 1 1 0 0
0 1 1 0 1 0 1 1 0 1
0 1 1 1 0 0 1 0 1 1
0 1 1 1 1 0 1 0 1 0
1 0 0 0 0 1 0 0 1 1
1 0 0 0 1 1 0 0 1 0
1 0 0 1 0 1 0 1 0 0
1 0 0 1 1 1 0 1 0 1
1 0 1 0 0 0 0 0 1 1
1 0 1 0 1 0 0 0 1 0
1 0 1 1 0 0 0 1 0 0
1 0 1 1 1 0 0 1 0 1
1 1 0 0 0 0 1 0 0 1
1 1 0 0 1 0 1 0 0 0
1 1 0 1 0 0 1 1 1 0
1 1 0 1 1 0 1 1 1 1
1 1 1 0 0 1 1 0 0 1
1 1 1 0 1 1 1 0 0 0
1 1 1 1 0 1 1 1 1 0
1 1 1 1 1 1 1 1 1 1
R = A·B⊕B⊕0 = B· A⊕1 = AB
S = A·B⊕A⊕0 = A· B⊕1 = AB
For this intention, we have minimized the gate counts
in the module-1 design of n-bit comparator. In this work,
we utilize one PPC to construct the module-1 of the n-
bit comparator as well as the 1-bit comparator (presented
in Section 4.2). The schematic presentation and quantum
equivalent realization of 1-bit comparator are depicted in
Figures 4(a and b).
3.2. The Proposed PPNG-1 Gate
A 4 × 4 PPNG-1 is presented in Figure 5(a) and its truth
table are drawn in Table III. It can be confirmed from
the truth table that the PPNG-1 is reversible because of
bijective mapping between input and output signals. The
quantum equivalent presentation in Figure 5(b), and dotted
rectangle box is equal to a 2×2 CNOT gate, the quantum
cost of PPNG-2 is 7 and its hardware complexity is as
arise 6 +4 +3 .
When programmed the third and fourth inputs of the
PPNG-1 gate as high and low respectively. The required
outputs of the PPNG-1 will occur.
Q = A⊕B
S = A· B⊕0 ⊕A· 1 ⊕0 = A·B⊕A·0 = AB
For this intention, we have minimized the garbage outputs
in the module-2 design of n-bit comparator (presented in
Section 4.2).
3.3. The Proposed PPNG-2 Gate
A 3 × 3 CRG named, PPNG-2 is proposed in this work
and depicted in Figure 6(a). The reversibility truth table is
drawn in the Table IV. The QC of the PPNG-2 is equal
to 3, and its hardware complexity is as arise 4 . There are
J. Nanoeng. Nanomanuf., 6, 1–16, 2016 5
6. Designing Conservative Reversible N-Bit Binary Comparator for Emerging QCA Nano Circuits Misra et al.
ARTICLE
Fig. 4. Two-input comparator with PPC gate: (a) Schematic diagram, (b) Quantum equivalent realization.
Fig. 5. The proposed PPNG-1 gate: (a) Schematic presentation, (b) Quantum equivalent realization.
very few CRG has such low value of quantum cost with
its unique feature.
When programmed the first and third inputs of the
PPNG-2 gate as low and high respectively. The required
outputs of the PPNG-2 will occur.
P = 0 ⊕B = B
R = B ⊕1 ⊕D = B ⊕D
Table III. The truth table of the PPNG-1 gate.
A B C D P Q R S
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 1 0 0
0 0 1 1 0 1 0 1
0 1 0 0 0 1 1 1
0 1 0 1 0 1 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 0 1 0
1 0 0 0 1 1 0 1
1 0 0 1 1 1 0 0
1 0 1 0 1 0 1 0
1 0 1 1 1 0 1 1
1 1 0 0 1 0 0 1
1 1 0 1 1 0 0 0
1 1 1 0 1 1 1 0
1 1 1 1 1 1 1 1
For this intention, we have minimized the garbage outputs
and required the output of the comparator in module 3
design of n-bit comparator. In this work, we utilize one
proposed PPNG-2 to construct the module-3 of the n-bit
comparator (presented in Section 4.2).
Lemma 1. Novel PPC gate is a conservative gate.
Proof A PPC gate is 5 × 5 type reversible gate. Let the
input vector is Iv(A, B, C, D) and the output vector is OV =
P = A⊕B⊕C , Q = B, R = AB⊕B⊕D , S = AB⊕
A ⊕ D , T = A ⊕ D ⊕ E . We know that parity of input
and parity of output was conserved in any conservative
gate.
The parity of input is A ⊕ B ⊕ C ⊕ D ⊕ E and parity
of output is
A⊕B⊕C ⊕B⊕ AB⊕B⊕D ⊕ AB⊕A⊕D
⊕ A⊕D⊕E
= A⊕B⊕C ⊕B⊕ AB⊕D ⊕ AB⊕D
⊕ A⊕D⊕E
= B⊕C ⊕ AB⊕A⊕D ⊕ AB⊕B⊕D
⊕ A⊕D⊕E
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Fig. 6. The proposed PPNG-2 gate: (a) Schematic presentation, (b) Quantum equivalent realization.
Table IV. The truth table of the PPNG-2.
A B C D P Q R S
0 0 0 0 0 0 0 0
0 0 0 1 0 1 1 1
0 0 1 0 0 0 1 0
0 0 1 1 0 1 0 1
0 1 0 0 1 1 1 0
0 1 0 1 1 0 0 1
0 1 1 0 1 1 0 0
0 1 1 1 1 0 1 1
1 0 0 0 1 0 0 0
1 0 0 1 1 1 1 1
1 0 1 0 1 0 1 0
1 0 1 1 1 1 0 1
1 1 0 0 0 1 1 0
1 1 0 1 0 0 0 1
1 1 1 0 0 1 0 0
1 1 1 1 0 0 1 1
= B ⊕C ⊕ A+B ⊕D⊕ A+B ⊕D⊕A⊕D⊕E
= B⊕C⊕A⊕D⊕E = A⊕B⊕C⊕D⊕E
Since we know AB ⊕ A = A + B, AB ⊕ B = A + B,
A⊕A = 0
Thus, the parity of the output is matched to the
parity of input. Hence, PPC gate is a conservative
gate.
4. THE PROPOSED DESIGNING APPROACH
FOR CR, n-BIT COMPARATOR
The proposed conservative reversible n-bit comparator,
based on three modules, named as module-1, module-2
and module-3. There are various circuits of the reversible
comparator in the state of art among which the latest cir-
cuits in Ref. [5]; are examined to be the optimal reversible
metrics. We influence on this circuit;5
and compared it
with our circuit, our achievement was to optimize all the
reversible metrics such as gate count, garbage outputs, and
quantum cost. In the next section, we cover this concept to
the schematic diagram, algorithms, detail description, and
lemmas.
4.1. Module-1 Design of Conservative Reversible
n-Bit Comparator
This section, we have explored the proposed gate to syn-
thesize a module-1. A 5 × 5 PPC gate has been uti-
lized to synthesize a module-1. The working princi-
ples of the proposed PPC are utilized MSB bit of two
n-bit numbers with Figure 7(a). The required output for
comparator design as, a first output for equal to, the
third output for less than and fourth outputs for greater
THAN.
4.2. Module-2 Design of Conservative
Reversible n-Bit Comparator
In this section, the construction of the module-2 using the
PPNG-1 and BVPPG gates. The motive of selection of
gates is optimizing the reversible metrics. Based on this
combination gates, a PPC-I around the module-2 is fin-
ished. Figure 7(b) depicts the circuit of PCC-1 (named as
P = parity, C = comparator, and C = cell). In considera-
tion with the rules of reversible logic syntheses that fan-in,
feedback and fan-out are not permitted, kept in mind to the
circuit construction. The working principles of the second
module are utilized (n–1) the bit of two numbers, as well
as previous module inputs Rn = Equal to and Pn = Greater
than. In fact, module-2 generate the equal and a greater
logic bit.
The QC of PPNG-1 gate is 7 and BVPPG gates is 10;
therefore, the QC of PCC-1 is equal to:
QC PCC−1 = QC 1 ×PPNG-1 +QC 1 ×BVPPG
= 7 +10 = 17
4.3. Module-3 Design of Conservative Reversible
n-Bit Comparator
For minimizing the quantum cost and unit delay in order
to cost effective design, we use the one PPNG-2 as a pro-
grammable way of inputs (A = 0, C = 1) as a module-3.
The working principle of the third module is to utilize two
outputs of previous module-2 (Pn and Rn , the process of
acquiring output from the previous module can take place
in a repeated way if the least significant bit (LSB) is not
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Fig. 7. (a) The proposed architecture of module-1. (b) The proposed architecture of module-2. (c) The proposed architecture of
module-3.
Table V. The truth table of 2-bit comparator.
Input Output
A2B2 A1B1 P (Greater than) Q (Less than) R (Equal to)
A2 > B2 x 1 0 0
A2 < B2 x 0 1 0
A2 = B2 A1 = B1 0 0 1
A2 = B2 A1 < B1 0 1 0
A2 = B2 A1 > B1 1 0 0
obtained. The less than logic obtain, if greater and equal
enter into the third module (utilize PPNG-2). It first checks
the greater than, equal to and if not any of these, it’s final
step is to synthesize the less than logic by this expres-
sion, {(Greater than) ⊕ (Equal to)}.’ In fact, module-3
Fig. 8. Proposed CR, 2-bit comparator (a) The presented architecture (b) Quantum equivalent realization.
generates the all logic bits of the comparator, as shown in
Figure 7(c).
4.4. Modules Based 2-Bit Conservative
Reversible Comparator
The 2-bit comparator computing the three required outputs
such as P (Greater than), Q (Less than) and R (Equal to),
from truth Table V, some logical calculation expressions
can be obtained as followed.
FG = A2 > B2 ⊕ A2 = B2 A1 > B1
FL = A2 < B2 ⊕ A2 = B2 A1 < B1
FE = A2 = B2 A1 = B1
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Fig. 9. The proposed architecture of CR, n-bit comparator.
According to the logical calculation expressions, a cir-
cuit employing three modules is depicted in Figure 8(a).
The circuit of 2-bit comparator has groups of inputs
(A1, B1 and (A2, B2 these inputs are applied to PPC
and PCC-1. The outputs (P2, R2 of PPC gate, are
associated with PCC-1. Similarly, the outputs (P1, R1
of PCC-1, are associated with PPNG-2 gate. The
required comparator logic is obtained from the PPNG-
2 gate, marked as P (Greater than), Q (Less than)
and R (Equal to). The quantum presentation of the
2-bit comparator is depicted in Figure 8(b). The
steps to design a 2-bit comparator are presented in
Algorithm 1.
Algorithm 1 (2-Bit Comparator Design).
(a) Take a 1 PPC gate will take inputs A2 B2 1 0 0
and synthesize outputs P1 = A2
¯B2 Q1 = AB R1 =
A1 ⊕B1 A2 B2
(b) Take a 1 PPC-1 cell will take inputs A1 B1 P1 R1
and synthesize outputs P0 = P1 ⊕ R1 A2B2 R0 =
R1 A2 ⊕B2
(c) For final selection of comparator output take one
PPNG-2 gate will accept inputs in the sequence
0 P0 1 R0 and synthesize outputs P = P0 Q =
P0 ⊕R0 R = R0 P0 ⊕R0
(d) Select appropriate comparator outputs, P (Greater
than) Q (Less than) and R (Equal to) and consider remain-
ing as garbage outputs.
4.5. Modules Based n-Bit Conservative
Reversible Comparator
The n-bit comparator required, one time module-1 (used
one PPC), (n − 1) time module-2 (used one BVPPG and
PPNG-2) and one module-3 (used one PPNG-2), depicted
in Figure 9. The n-bit comparator is designed by 1 PPC
gate which acquires two binary numbers An and Bn. It
produces three outputs Rn, Pn and Qn. These outputs are
associated with PCC-1, where previous of (n−1 the bits
of A and B are also feed. Now generated outputs are Pn−1
and Qn−1 associated with PPNG-2 gate. That presented
outputs of the PPNG-2 gate is the comparator outputs.
Algorithm 2 shows a formal presentation of the n-bit com-
parator design.
Algorithm 2 (Comparator-Design-Algorithm
(n-Bit)).
1. Input, Output: Input (A0, A1,……An) and B=(B0,B1,…Bn),
Output O=(P, Q, R) for comparator operation.
Begin
2. Level-1: Circuit takes on one PPC gate
a. Take two MSB of (n-1)th bit data from n-bit data
I(A,B) and synthesize three output
O(Pn-1, Qn-1, Rn-1)
3. Begin procedure
4. Step-1. If I1>I2 then
5. O4=Pn-1
6. if I1<I2 then
7. O3=Qn-1
8. Else O3=Rn-1
9. End if
End if
10. End procedure
11. Level-2: Circuit takes (n-1) PCC-1 cell
a. Take (n-2)
th
data from n-bit data bit I(A,B) and two
also take level-1 particular output I(Pn-1, Rn-1) and
synthesize two output (Pn-2, Rn-2)
12. Begin procedure
For i=n to 0
If i=n then
13. )2nB2nA(1nR1nP2nP1O −−−⊕−=−= ,
14. )2nB2nA(1nR2O −⊕−−=
15. End if
End loop
16. End procedure
17. Level-3: Circuit takes one PPNG-2 gate
a. Take LSB data bit from previously result output O
(P0,R0) and synthesize three output O(P,Q,R), where
R (Equal to), P (Greater than) and Q(Less than) for
appropriate Comparator logic operation.
18. Begin procedure
19. If i=0 then
20. O1=P, // Greater than
21. 0R0PQ3O ⊕== , // Less than
22. O4=R, // Equal to
23. End if
24. End procedure
25. End
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5. REVERSIBLE METRICS CALCULATION
OF THE PROPOSED CRC
In this section, we have present the comprehensive calcu-
lation of all the proposed CRC in terms of popular met-
rics. In the circuit construction of 2-bit and n-bit CRC, the
main concern is to keep reversible metrics as minimum
as possible. Several minimum reversible metrics for CRC
in regards quantum cost, garbage outputs, constant inputs,
and hardware complexity are presented by Lemmas 2, 3
and 4.
Lemma 2. A CRC circuit for 2-bit binary number com-
parator can be syntheses of at least 29 quantum cost,
9 garbage outputs, 8 constant input and (19 +8 +4
hardware complexity.
Proof. A 2-bit comparator has used three modules
(module-1, module-2 and module-3) in Figure 8. The QC
of module-1, module-2 and module-3 are 9, 17 and 3
respectively. Thus, the QC of 2-bit CRC is 29, because
QC 2-bit comparator
= 1QC module-1 +1QC module-2
+1QC module-3 = 9 +17 +3 = 29
The input to output mapping is bijective and conserve
the parity bit in the 2-bit comparator circuit. In this,
at least, 9 garbage outputs are required, which needed
8 constant inputs. The circuit structure of 2-bit compara-
tor utilizes module-1 that generates 3 garbage output,
module-2 that generates 5 garbage output and module-3
that generate 1 garbage output, depicted in Figure 7(b).
Thus, the GO is 9, because
GO 2-bit comparator
= 1GO module-1 +1GO module-2
+1GO module-3 = 3 +5 +1 = 9
The circuit of 2-bit comparator consists of modules
(module-1, module-2 and module-3), that required con-
stant input (CI) is 3, 3 and 2 respectively. Thus, the CI
is 8, because
CI 2-bit comparator
= 1CI module-1 +1CI module-2
+1CI module-3 = 3 +3 +2 = 8
Table VI. Reversible metrics comparison of n-bit CRC.
Size GC in %IR
order bit GC in [5] proposed w.r. to GC QC in [5] QC in proposed %IR w.r. to QC GO in [5] GO in proposed %IR w.r. to GO
2 6 4 33 33 31 29 6 45 11 8 27 27
4 12 8 69 63 8 69 25 18 28
8 24 16 145 131 9 65 53 38 28 30
16 48 32 297 267 10 10 109 77 29 35
32 96 64 601 539 10 31 221 158 28 50
64 192 128 1209 1083 10 42 445 318 28 53
128 384 256 2425 2171 10 47 893 638 28 53
256 768 512 4857 4347 10 50 1789 1278 28 85
Table VII. Comparison results of different n-bit comparator.
Design [5] [14] [16] [17] Proposed
n-bit
#GC (4n−2) (7n−4) (3n) (4n−2) 2n
# QC (19n−7) (16n−10) (13n−5) (14n) (17n−5)
# GO (7n−3) (5n−4) (4n−3) (5n−4) (5n−2)
In a 2-bit comparator, we use 1 module-1, 1 module-2,
and 1 module-3. The module-2 is acknowledged as a
combination of two gates (1 PPNG-1 + 1BVPPG) in
Figure 7(a). Thus, we can specify that the hardware com-
plexity (HC) as:
HCmodule−1 = 8 +2
HCmodule−2 = HCPPNG−1 +HCBVPPF
= 5 +6 +4 + 2 = 7 +6 +4
HCmodule−3 = 4
Thus, then requires hardware complexity for 2-bit CRC is
HC = HCPPC +HCPCC−1 +HCPPNG−2
= 8 +2 + 7 +6 +4 + 4
= 19 +8 +4
Lemma 3. The n-bit binary number of CRC circuit can be
syntheses by at least
GOn−bit ≥ 5n−2
GCn−bit ≥ 2n
QCn−bit ≥ 17n−5
Where GO, GC, QC be the necessary numbers of garbage
outputs, gate count, and quantum cost. Then
Proof. In 2-bit comparator, there are three outputs
(P, Q, R). Thus, it has at least 8 garbage output. Because
PPC at least 2 GO, PPC-1 cell at least 5 GO and PPNG-
2 at least 1 GO. The least number of GO in 2-bit
comparator is
GO2−bit = 8 = 5 ×2 −2
Hence, the result persists for 2- bit comparator.
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Fig. 10. (a) Comparison results of existing and proposed based on gate count, (b) Comparison results of existing and proposed based on Quantum
cost, (c) Comparison results of existing and proposed based on garbage output.
Suppose that, the result persists for the n-bit compara-
tor. Hence, a necessary number of garbage outputs is
GOn−bit = 5n−2 .
The 2-bit comparator logic synthesis by utilizing the
designs such as module-1, module-2, and module-3. The
total gate count is 1 + 2 + 1 = 4 = 2 × 2. Thus, the result
persists for 2-bit. Suppose that, the result persists for
the n-bit.
As a result, the least gate count for a n-bit comparator
is 2n.
According to the circuit of the 2-bit comparator. The
circuit consists of 3 modules (module-1, module-2 and
module-3), that requires 9, 17 and 3 quantum cost respec-
tively. So the least quantum cost of 2-bit comparator is
QC2−bit = 29 = 17 ×2 −5 .
Hence, the result persists for the 2-bit comparator.
Assume that, the result persists for the n-bit com-
pactor. The least quantum cost for n-bit comparator is
QCn−bit = 17n−5 .
Lemma 4. A n-bit comparator can be synthesized with
5 +7n + 6n−4 +4 n−1 , hardware complexity.
Proof. Theorem 3 is the evidence for 2-bit comparator
with (19 + 8 + 4 hardware complexity. In this state,
we have synthesized hardware complexity of n-bit com-
parator. Combining 1 module-1, (n − 1) module-2 and
1 module-3 for the n-bit comparator. Hence, the hardware
complexity for a n-bit comparator is
1× 8 +2 + n−1 7 +6 +4 +4
= 8 +7 n−7 +4 + 2 +6 n−6
+ 4 n−4 = 5+7n + 6n−4 +4 n−1
Therefore, a reversible n-bit comparator can be synthe-
sized with 5 + 7n + 6n − 4 + 4 n − 1 , hardware
complexity.
5.1. Comparison Between Various Circuits of
Reversible Comparator
Circuits for reversible comparator were presented in
Refs. [14–21]. It is demanding to perform better regard-
ing reversible metrics and size order extend for n-bit.
The proposed n-bit CRC is compared to counterparts.5
Note that the proposed CRC circuit has an optimal value
of reversible metrics than the existing CRC. It is verified in
Table VI the quantity, size increase, the improvement ratio
(IR) also increases. Hence, it can analyze that reversible
comparator is giving optimal reversible metrics as com-
pared to the best existing CRC.5
Table VII shows that
the existing CRC circuit requires (4n−2) gate count and
(19n−7) quantum cost. This work presented CRC circuit
require less reversible metrics such as (2n) gate counts
and (17n − 5) quantum cost. So our claim for the opti-
mal value of reversible metrics has been correct. In the
same way, garbage outputs of proposed CRC circuit that
our better reversible metrics. Figures 10(a–c) present the
comparison of the proposed CRC with the existing non-
conservative reversible comparator (NCRC) circuits. Gen-
erally, a conservative circuit is not cost effective than the
non-conservative circuits. Note that the proposed CRC per-
form better than the NCRC circuit, which is shown in
Figures 10(a–c). In the case of proposed 2-bit comparator
circuit synthesize by 4 gate count, 29 quantum cost and
8 garbage outputs, whereas the best-known conservative,
reversible comparator;5
requires 6 gate count, 31 quantum
cost, and 10 garbage outputs.
6. DESIGN OF REVERSIBLE PPC IN QCA
In this section, we present QCA layouts and simulation
results of PPC gate. It is suitable to give layout rules
as required for designing layouts in QCA in the next
part.
6.1. QCA Computing Design Rules Adopted in the
PPC Layout Design
(i) Taking coplanar (rotated) cells to reduce the clock
cycle delay.25
(ii) Using four clock zones to synthesizing the
results.
(iii) Using a proper sequence of the clock (clock0, clock1,
clock2, clock3 ).
(iv) Avoiding long wire and crossovers. Its advantage is
that it decreases the layout area and delay.26
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Fig. 11. PPC gate: (a) Logic diagram by Maj3, (b) Cell layout.
(v) The maximum 15 cells in layout design to operate
with one clock zone. It minimizes the thermodynamic phe-
nomenon.
(vi) For duplication of logic signal take the fan-out con-
cept but with different clock zone. It reduces the layout
area.
(vii) For computation, fixed polarization, normal cell and
rotated cell utilized.
6.2. QCA Layout of Reversible PPC and
Simulation Results
In an attempt to quantum information processing by using
reversible logic, we select QCA, more powerful than its
CMOS technology.25
The theorems of QCA are confi-
dent that they can provide high computing speed and high
device density. Researchers in demonstrated the robust
design (coplanar crossing) and it were focused that rotated
cells are more stable as compared to normal cells. That’s
why the rotating cell is utilized for cell layout design.
Proposed designs are simulated with QCA Designer, using
the simulation engine (Bistable approximation), with a
default parameter. We present the block diagram and cell
layout of PPC (In Fig. 11). The QCA simulation results of
PPC are presented in Figure 12(a). Here we show the QCA
primitives results for quantum information, 14 Majority
voter, 7 Inverter, 0.432 m2
(cell area) and 387 (cell
count).
The appropriate QCA majority gate expression can be
written for P node is:
P = M M A, B, C M A, B C C
= M AB+BC+AC AB+BC+AC C
= C AB+BC+AC + AB+BC+AC AB+BC+AC
+C AB+BC+AC
= C AB BC AC + AB BC
× AC AB+BC+AC +ABC
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(a)
(b)
Fig. 12. (a) Simulation result of PPC gate, (b) Simulation diagram of
the proposed 1-bit comparator.
= C AB+BC+AC + AB+BC+AC
× AB+BC+AC +ABC
= ABC+ABC+ABC+ABC= 1 2 4 7 =A⊕B⊕C
The majority logic format of the node R according to lay-
out of PPC can be written as:
R = M M M A B 0 D 0 M M A B 0 D 0 1
= M M AB D 0 M AB D 0 1
= M D A+B ABD 1
= D A+B ABD+ABD+ A+B D
= ABD+AD+BD = ABD+ A+B D
= AB D+ AB D = 1 2 5 7 = AB⊕D
As the equation of node S = AB ⊕ A ⊕ D = AB ⊕ D
requires EX-OR, AND, NOT gates for the realization of
the layout. These EX-OR, AND, NOT gates are synthe-
sized by majority gate. The synthesize majority equation
is drawn as:
Q = M M M A B 0 D 0 M M A B 0 D 0 1
= M M AB D 0 M AB D 0 1
= M D A+B ABD 1
= D A+B ABD+ABD+ A+B D
= ABD+AD+BD = ABD+ A+B D
= AB D+ AB D = 1 3 4 7 = AB⊕D
The input-output connection can be represented as a node
T = A ⊕ D ⊕ E. The majority logic arrangement accord-
ing to PPC cell layout can be represented by appropriate
synthesise majority expression as:
T = M M A, D, E M A, D, E E
= M AD+DE+AE AD+DE+AE E
= E AD+DE+AE + AD+DE+AE
× AD+DE+AE +E AD+DE+AE
= E AD DE AE + AD DE AE
× AD+DE+AE +ADE
= E AD+DE+AE + AD+DE+AE
× AD+DE+AE +ADE
= ADE+ADE+ADE+ADE
= 1 2 4 7 = A⊕D⊕E
Lemma 5. A 1-bit comparator utilizes 24.205% of area
usages.
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Proof. One PPC gate forms a 1-bit comparator
(In Fig. 7(a)). For total area calculation, QCA Designer
tool automatic gives the total area of PPC layout, which is
518,008 nm2
. However, in the case of the cell area, manual
manipulation is done. These manipulations are:
Cell area = Total number of cells used in the layout
× One individual cell area
= Total number of cells used in the layout
× One cell width×One cell height
= 387 × 18×18 =387×324=125 388 nm2
For area usages, the calculation is done by dividing the
cell area to total area by following way.
Area usage for proposed gate
= Cell area / Total area
= 125 388 / 518 008 = 24 205%
Therefore, 1-bit comparator utilizes 24.205% of area
usages.
Lemma 6. The 1-bit comparator requires the same layout
of PPC with 1 latency.
Proof. PPC can implement the 1-bit comparator results
as shown in Figure 7(a). In the layout (Fig. 11(a)) inputs
are set as C = 1 and D = E = 0 the output P, R and S
synthesize the comparator logic (In Fig. 12(b)). In the cell
layout design of the PPC the following clock is utilized
in the specific order (Clock 0, Clock 1, Clock 2, Clock 3,
Clock 0, ). The simulation result ensures that if A = B
means outputs, P = 1, and Q = R = 0, after 1 clock cycle
delay i.e., Equal logic synthesizer. When the comparator
input A = 0 and B = 1, then the output as P = Q = 0 and
R = 1, after 1 clock cycle delay i.e., Less logic synthesizer.
When A = 1 and B = 0, then the output as S = 1 and
P = R = 0, after 1 clock cycle delay i.e., Greater logic
synthesizer. Hence, the 1-bit comparator requires the same
layout of PPC with 1 latency.
In Table VIII specify the detail of reversible as well as
QCA primitives for the adopted coplanar crossover (used
rotated as well as a normal cell) in the proposed compara-
tor design and compared to recent preliminary design.22
According to parameter obtained, our circuits are more
suitable for conservative reversible-QCA approach.
Table VIII. Comparisons of 1-bit reversible comparator.
QCA primitives
Reversible metrics
Area
Design MV Latency ( m2
GC QC CI GO Conservative
[22] 1-bit 17 7 0.343 3 9 3 2 NO
Proposed 1-bit 14 3 0.432 1 9 3 2 YES
%IR 17.64 57.14 NI 66.66 NI NI NI
7. THE ENERGY DISSIPATION ANALYSIS OF
PROPOSED PPC GATE
To analyze the robustness and performance of the proposed
PPC gate at different kink energy (0.5 mev, 1 mev and
1.5 mev).27
The exhaustive technique is used for energy
estimation during an input switching vector in PPC gate.
The results are depicted in Table IX. This result shows that
the maximum energy dissipation, minimum energy dissi-
pation, average energy dissipation, average leakage and
average switching energy dissipation are 1.433, 0.2245,
0.78531, 0.22764, 0.55767 respectively at Ek = 0 5 mev,
likewise are 1.6172, 0.61914, 1.07908, 0.62527, 0.45381
respectively at Ek = 1 mev and 1.87115, 1.0498, 1.42932,
1.05777, 0.37154 respectively at Ek = 1 5 mev. By this
result, the average energy dissipation of the PPC gate
increases with the kink energy in a constant manner. For
this analyzing energy is conducted using QCAPro tool.
Energy dissipation versus kink energy plots for average
leakage, average switching and average energy dissipation
of PPC are drawn in Table VIII of the second row. For
instance, at a kink energy (0.5 mev, 1 mev and 1.5 mev),
maximum and minimum energy dissipation are drawn in
Table VIII of the third row. The estimation of power in
each cell at 0.5Ek is depicted in Table IX of the first
row. The worst power dissipated cells, encircled with black
must be made physically reversible, so to make it zero
power dissipation. All other remaining cells, which are
indicated with a light color, used in designing wire, the
majority and inverter are better regarding power dissipa-
tion. In the energy estimation, we have used the cell size
of 18 nm.
8. AVERAGE POLARIZATION ESTIMATION
VERSUS TEMPERATURE
The usual working of reversible 1-bit comparator is men-
tioned in the previous section. Temperature dependency
analysis of proposed PPC gate is also presented. How-
ever, temperature dependency analysis is done with a
coherent vector engine with default parameters. To test
the temperature dependencies of the QCA design of the
PPC are simulated in a different range of temperature
(1 to 10 0
K) and measure polarization at the differ-
ent output node (P, Q, R, S, T). For output node R
the Avg. Output node polarization at 1 0
K is calculated
as: (9.50e–001)–(−9.56e–001)/2 = 3.812. The obtained
polarization value ensure that the design has an accu-
rate functioning in a different range of temperature (1
to 10 K). Figure 13 depicts the average output node
polarization versus temperature for the proposed design
of the PPC gate. Therefore, the average polarization esti-
mation is efficient in the range of temperature (1 to
10 K). The maximum reaches temperature is a challenge
in QCA.27
14 J. Nanoeng. Nanomanuf., 6, 1–16, 2016
15. Misra et al. Designing Conservative Reversible N-Bit Binary Comparator for Emerging QCA Nano Circuits
ARTICLE
Table IX. Energy dissipation analysis.
Design PPC
QCA cell count 348
Thermal layout Ek At 0.5, Where Ek is the
maximum kink energy
Average energy dissipation for various
value (0.5, 1 and 1.5) of kink energy Ek
Max and min energy dissipation for various
value (0.5, 1 and 1.5) of kink energy Ek
9. DISCUSSION
We achieve the physical reversibility and estimation of
energy dissipation aspects of the QCA cell layout by using
QCAPro tool. The two main concerns of this analysis are:
Physical reversibility may be anticipated by the cover of
prerequisites that
(a) In thermal layout map good and worst condition iden-
tified by color map, few of the cells and gates are dissi-
pate large power, this is made by the QCAPro tool. The
major step in minimizing the energy dissipation of dark
hotspot to designers to achieve the fully physical reversible
system.
(b) By synchronizing all the four clock zones, the higher
the stability (Polarization value) in QCA design can be
achieved.
Therefore, our emphasis on the analysis of QCA cell lay-
out in QCAPro tool with a different value of kink energy.
However, analysis of energy dissipation applied to PPC.
Therefore, we analyzed the energy dissipation, to indicate
the low power feature in this work.
J. Nanoeng. Nanomanuf., 6, 1–16, 2016 15
16. Designing Conservative Reversible N-Bit Binary Comparator for Emerging QCA Nano Circuits Misra et al.
ARTICLE
Fig. 13. Temperature analysis of average output node polarization of
proposed PPC gate.
10. CONCLUSIONS
An effort has been made in optimizing the conservative
comparator circuit around QCA. The proposed comparator
circuit is successfully designed with three new conserva-
tive, reversible gates. These new reversible gates (PPC,
PPNG-1, and PPNG-2 gate) have low values of quan-
tum cost and novel comparator circuit is analyzed with
the existing circuits regarding gate count, garbage output,
and quantum cost, all the parameters is optimized. Also,
reversible 1-bit comparator simulation is performed suc-
cessfully by QCA Designer tool. The QCA design of 1-bit
comparator has been tested successfully and requires only
387 number of cells, 0.432 m2
area, and 24.205% area
usages. Also, we also tested average polarization versus
temperature of all the different nodes of the PPC in QCA
using coherence engine. This analysis shows that output
S node cell slumped after 7 K0
to 8 K0
then become
constant. The optimized reversible parameters and QCA
primitive results demonstrate and confirmed that our cir-
cuits dominate over the state of the art circuits. This com-
parator circuit will be useful for implementing the digital
devices, encryption devices, microprocessor and microcon-
troller systems and digital communication.
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