This document describes a hybrid full adder design using both CMOS and transmission gate technologies that achieves low power and high speed. The design is divided into modules: 1) an XOR-XNOR module using weak inverters to reduce power, 2) a sum generation module using transmission gates, and 3) a carry generation module using strong transmission gates to reduce delay. Simulation results show the hybrid full adder achieves a power dissipation of 2.94μW and delay of 61.4ps at 1.8V in a 180nm technology, with lower power at lower voltages. This design coupled weak inverters with strong transmission gates to achieve both low power and high speed.

1. Performance Analysis of Low-power High-Speed
Hybrid Full Adder
Thallam Keerthi, Electronics and Communication Department, M. Tech VLSI Design and Embedded Systems, RV
college of Engineering, Bangalore, India, e-mail ID: keerthi.thallam11@gmail.com
Abstract— Technical advancements and increasing demand
poses the strict constraint on power consumption, speed and
area. This paves the path for low power, high speed compact
circuit design. Since every logic design has both merits and
demerits. Combining the merits of the logic styles gives rise to the
hybrid design. This paper presents the hybrid full adder design
using CMOS (complementary metal oxide semiconductor)
technology and transmission gate technology. This circuit is
implemented using cadence virtuoso tool using 180nm
technology. Performance parameters like power, speed and
transistor area were compared with existing logic design styles
like static CMOS technology, dynamic CMOS technology, and
other hybrid models. For 180nm technology, at 1.8v power
supply, the power dissipation of full adder is extremely low (2.94
μW) and the delay is as low as 61.4ps. In this, weak inverters are
coupled with strong transmission gates, which results in very low
power, high speed and area efficient model.
Keywords— low power, High speed, cadence virtuoso, CMOS,
Transmission gates, 180-nm technology
Introduction:
It is time we explore the well-engineered deep submicron
CMOS technologies to address the challenging criteria of
these emerging low-power and high-speed digital
communication signal processing chips. The performance of
many applications as digital signal processing depends upon
the performance of the arithmetic circuits to execute complex
algorithms such as convolution, correlation, and digital
filtering. Fast arithmetic computation cells, including adders
and multipliers are the most frequent and widely used circuits
in very-large-scale integration (VLSI) systems. The
semiconductor industry has witnessed an explosive growth of
integration of sophisticated multimedia-based applications into
mobile electronic gadgetry for the last decade. However, the
critical concern in this arena is to reduce the increase in power
consumption beyond a certain range of operating frequency.
Moreover, with the explosive growth, the demand, and the
popularity of portable electronic products, the designers are
driven to strive for smaller silicon area, higher speed, longer
battery life, and enhanced reliability. Full adders are
fundamental cells in various circuits which is used for
performing arithmetic operations such as addition, subtraction,
multiplication, address calculation and MAC, etc..Enhancing
the performance of the full adders can significantly affect the
whole system performance.
There are standard implementations with various logic styles
that have been used in the past to design full-adder cells and
the same are used for comparison in this paper. Although they
all have similar function, the way of producing the
intermediate nodes and the transistor count is varied. Different
logic styles tend to favor one performance aspect at the
expense of the others. The logic style used in logic gates
basically influences the speed, size, power dissipation, and the
wiring complexity of a circuit. The circuit delay is determined
by the number of inversion levels, the number of transistors in
series, transistor sizes (i.e., channel widths), and the intra cell
wiring capacitances. Circuit size depends upon the number of
transistors, their sizes and on the wiring complexity. Some of
them use one logic style for the whole full adder while the
other use more than one logic style for their implementation.
Which is known as hybrid-logic design style.These designs
exploit the features of different logic styles to improve the
overall performance of the full adder.
A full adder with a CMOS logic design which is generally
used for robustness against voltage scaling uses 28 transistors.
The circuits which use this design style suffers from high
input capacitance which makes the response slow (delay is
more) and more buffers are required to drive the next stages.
When CPL (complementary pass transistor logic) is
considered, it has good voltage swing, but the power
consumption is high, so it is generally not preferred for lower
power applications and it uses thirty two transistors to
implement the full adder circuit which is not an area efficient
design. This paper also includes two hybrid logic designs one
pass transistors and transmission gates for the full adder
implementation. This implementation uses 14 transistors.
Another hybrid logic HPSC (Hybrid pass logic with static
CMOS output driver full adder) which uses 22 transistors
which causes an increase in the area and hence the time delay.
All these hybrid adders show the promising performance, but
good buffers are supposed to be added for the promising
performance in the cascaded structure. When using for the
high performance computations delay is one of the major
constraints.

2. I. REVIEW OF FULL ADDER DESIGN OF DIFFERENT
CMOS LOGIC STYLES
A. CMOS LOGIC:
The complementary CMOS full adder (C-CMOS) of Fig. 1(a)
is based on the regular CMOS structure with pMOS pull-up
and nMOS pull-down transistors. The series transistors in the
output stage form a weak driver. Therefore, additional buffers
at the last stage are required to provide the necessary driving
power to the cascaded cells. The advantage of complementary
CMOS style is its robustness against voltage scaling and
transistor sizing, which are essential to provide reliable
operation at low voltage and arbitrary transistor sizes
B. CPL:
The complementary pass transistor logic (CPL) full adder
with swing restoration is shown in Fig. 1(b). Its dual-rail
structure uses 32 transistors. The basic difference between the
pass-transistor logic and the complementary CMOS logic
styles is that the source side of the pass logic transistor
network is connected to some input signals instead of the
power lines. The advantage is that one pass-transistor network
(either pMOS or nMOS) is sufficient to implement the logic
function, which results in smaller number of transistors and
smaller input load. However, pass-transistor logic has an
inherent threshold voltage drop problem. The output is a weak
logic “1” when “1” is passed through a nMOS and is a weak
logic “0” when “0” is passed through a pMOS. Therefore,
output inverters are also used to ensure the drivability.
C. TGA (Transmission Gate Adder)
A transmission- gate adder (TGA) using CMOS transmission
gates is shown in Fig. 1(c). The Transmission gate logic
circuit is a special kind of pass-transistor logic circuit. It is
built by connecting a pMOS transistor and a nMOS transistor
in parallel, which are controlled by complementary control
signals. Both the pMOS and nMOS transistors will provide the
path to the input logic “1” or “0,” respectively, when they are
turned on simultaneously. Thus, there is no voltage drop
problem, whether the 1 or the 0 is passed through it. The main
disadvantage of transmission gate logic is that it requires
double the number of transistors of the standard pass-transistor
logic or more to implement the same circuit. Smaller transistor
count adder circuits have been proposed, most of which
exploit the non-full swing pass transistors with swing restored
transmission gate techniques.
Evidently, different logic styles tend to favor one performance
aspect at the expense of the other. Performance parameters
like voltage range, voltage swing, delay, power-delay product,
output skew, driving capability, and silicon area are analyzed.
As an illustration, we will present the design of a novel low-
voltage full adder with a hybrid logic style in the next section.
The unique features possessed by this hybrid full adder will be
analyzed.
II. MODULE DIVISION OF DESIGNED FULL ADDER
The designed full adder circuit is divided into 3 modules; first
module is the 2 variable XNOR - XOR module, second
module produces the sum output using the transmission gates
and third module generates the carry out signal. Each module
is separately designed to give the desired low voltage, high
speed and area efficient hybrid adder.
A. XOR MODULE (module 1):
Referred XOR module:
This methodology is based on non complementary input
signals. This module uses 8 transistors to generate the
simultaneous XOR-XNOR module. This has good voltage
swing, but when the input vector AB is “10”, both P3 and N3
are ON. The XOR output node will be pulled down by N3 and
XNOR output node will be pulled up by P3 whereas logic “1”
is being passed through pMOS transistor P1 in the XOR
network and logic “0” is passed through the nMOS transistor
N2 in the XNOR network. This leads to contention between
the two transistors. To avoid this situation, the newly added
transistors P3 and N3 are made weak. Since it uses the
feedback circuitry for the input vectors AB equal to “00” or
“11” initially either XNOR or XOR output would be correct
and the other would be in high impedance state, with feedback
output of XOR or XNOR respectively would be set. This
creates the delay. The presented module overcomes this delay
problem.
Presented XOR-XNOR Module:
XNOR module is responsible for most of the power
consumption of the entire adder circuit. This is module is
designed in such a way that it consumes less power. This is
achieved by reducing the inverter sizes (width) to the
maximum possible extent, so that it in turn reduces the current
or it could be said that it reduces the capacitance which is
directly related to the power. So, the power consumption is
reduced in this way. Mp1, Mn1, Mp2 and Mn2 are sufficient
to produce the XNOR output, but it has a bad voltage swing,
so the voltage restoration circuit using Mp3 and Mn3
transistors is done so that we can expect the full rail voltage at
the output.
B. Sum Generation:
The output of XOR and XNOR module have been taken and
connected to the transistors Mp4, Mp5, Mn4 and Mn5 to give
the proper output of sum. The output of module1 has good
voltage swing and module 2 functions properly for all input
vectors. So, proper functionality with good voltage swing is
expected.
Sum = A (XOR) B (XOR) Cin
Cout = (A*B)+(B*C)+(C*A)

3. Fig. 1(a) Std. CMOS implementation
(c)
Fig. 1(c) TGA (Transmission Gate Adder)
Fig. 1(b) CPL (Complementary Pass Transistor Logic)
Fig. 2(a) Transistor implementation of referred XOR_XNOR
module
Fig. 2(b): XNOR implementation of presented module.
Fig. 2(c): Carry out Generation Module

4. Fig. 3(a): Implementation of presented Hybrid Full Adder
Module.
Fig. 3(b): 14-transistor Hybrid Full Adder
Fig. 3(c) HPSC Hybrid Full Adder
.
C. Carry Generation Module:
This module is taken care so that the delay is less in the
circuit. Usually in the full adder circuit the critical path would
be the path from carry in to carry out. In this circuit carry in is
used only in the last module it has to pass through only one
transmission gate so the delay is less. And the transistors used
in transmission gate Mp7, Mn7, Mp8 and Mn8 are made
stronger by increasing the width of the transistor which in turn
decreases the delay since the propagation time is inversely
proportional to transistor width.
If, A = B, then Cout = B; else, Cout = Cin.
A(XNOR)B . This functionality is logic high only when A
equals B, At this time carry out can be considered as B.
III. PERFORMANCE ANALYSIS OF PRESENTED FULL ADDER
This full adder is simulated using cadence virtuoso tool using
180-nm technology. This has the average power consumption
of 2.94 and delay of 61.4ps for a stretch of 1microsecond at
1.8V supply.
A. Average Power consumption:
Average power consumption is the combination of static,
dynamic and short circuit power. We aim to optimize the total
power consumption. In this circuit the main power
consumption happens only in the sum module. So, power
consumption is optimized in these using weak (transistor
width is reduced) transistors for the inverter circuits. When the
transistor width is reduced capacitance decreases, which is
directly related to the power consumption.
Since the inverters used are implemented using CMOS logic,
static power dissipation would be almost negligible since only
one transistor is on at a time. Fixed capacitance is the
combination of drain capacitances of pMOS and nMOS. This
drain capacitances are parasitic capacitances. Dynamic power
contributes to the major part of the power consumption.
B. Delay Calculation:
The circuit delay is determined by the number of inversion
levels, the number of transistors in series, transistor sizes (i.e.,
channel widths), and the intra cell wiring capacitances. In this
full adder circuit the critical path would be the path from
carry-in to carry-out. Reduction of path between carry-in to
carry-out plays the vital role. In the presented circuit only one
transmission gate is present between carry-in and carry-out.
And further the delay is decreased by using the proper
transistor sizing. The equivalent circuit of transmission gate is
as follows:
Usually fast circuits are of large width, the width of the
transistors is increased to increase the speed of the response.
DC Voltage Power Consumption
1.8V 2.94μW
1.2V 1.456μW
0.9V 818.2nW

5. IV. REVIEW OF DIFFERENT FULL ADDER HYBRID DESIGNS
A.Presented Full Adder:
This full adder uses 16 transistors with the delay of 61.4ps and
power consumption is 2.94μW. It has a good voltage swing
maintained in the output.
The efficient coupling of strong transmission gates driven by
weak CMOS inverters leads to fast switching speeds (61.4 ps
at 1.8-V supply). This circuit shows the proper result for 0.9v
with power dissipation of 818.2nW, for 1.2V supply, the
power dissipation is 1.456μW.
B.14-Transistor Full Adder:
This uses 14 transistors for the implementation of hybrid full
adder, This is implemented using pass transistor logic and
transmission gates. It has a good logic swing but it has added
noise to it.
C. HPSC
This is a hybrid pass logic with static CMOS output drive full
adder. This is implemented using 22 transistors. It gives
proper voltage swing, but because of more area consumption
and more delay this is not preferred. The driving capability of
this hybrid adder is less when cascaded. So, proper buffers are
supposed to be used.
IV. SIMULATION RESULTS AT DIFFERENT VOLTAGE LEVELS:
At 1.8V DC supply:
At 0.9 V DC Voltage supply
At 1.2 V DC Voltage supply
V. CONCLUSION
In this paper, hybrid design for the 1-bit full adder has been
proposed. Comparison between different logic styles and
different hybrid full adders is made in terms of performance
parameters like power, delay. And the simulation is also
carried out. In these weak (channel width of transistor is
reduced) inverters has been coupled with strong (channel
width of transistor is increased) transmission gates in order to
decrease the power consumption and the delay. XOR-XNOR
contributes to the major power loss in the circuit, so the width
is reduced to the maximum possible extent to reduce
capacitance which reduces the power. By increasing the size
of transistors in the transmission gate the delay is reduced.
Simulation is carried out using Cadence Virtuoso tool in 180-
nm technology. Simulation is carried out at 1.8V, 1.2V and
0.9V; this gives the power consumption of 2.94μW, 1.456μW
and 818.2nW respectively and the delay of 61.4ps, 112.7ps,
154.6ps respectively. With this it is very evident that by using
the hybrid adder power efficient adder can be proposed.
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