Increased downscaling of CMOS circuits with respect to feature size and threshold voltage has a result of dramatically increasing in leakage current. So, leakage power eduction is an important design issue for active and standby modes as long as the technology scaling increased. In this paper, a simultaneous active and standbyrgy optimization methodology is proposed for 22 nm sub-threshold CMOS circuits. In thefirst phase, we investigate the dual threshold voltage design for active energy per cycle minimization. A slack based genetic algorithm is proposed to find the optimal reverse body bias assignment to set of noncritical paths gates to ensure low active energy per cycle with the maximum allowable frequency at the optimal supply voltage. The second phase, determine the optimal reverse body bias that can be applied to
all gates for standby power optimization at the optimal supply voltage determined from the first phase. Therefore, there exist two sets of gates and two reverse body bias values for each set. The reverse body bias is switched between these two values in response to the mode of operation. Experimental results are obtained for some ISCAS-85 benchmark circuits such as 74L85, 74283, ALU74181, and 16 bit RCA. The optimized circuits show significant energy saving ranged (from 14.5% to 42.28%) and standby power saving ranged (from 62.8% to 67%).
Designing Conservative Reversible N-Bit Binary Comparator for Emerging Quantu...VIT-AP University
The quantum-dot cellular automata (QCA) has more advantages than CMOS regarding area and power. This
work targets a conservative reversible comparator and its realization in QCA. In this work, we construct a
conservative reversible comparator with an optimal value of reversible metrics. In state to design, three conservative
reversible gates, namely PPC, PPNG-1 and PPNG-2 (PP = parity-preserving, C = comparator, N = new,
G = gate), are proposed. Furthermore, the quantum equivalent of 1-bit and 2-bit comparator is presented. The
proposed concept has been implemented through an algorithm for the n-bit comparator. Also, PPC workability
is tested in QCA. The PPC has been performing 1-bit comparator result with minimum area, cell complexity,
and latency, which is found to be 0.52 m2, 387 and 1 respectively. In addition, the complete energy dissipation
analysis to explore such as a thermal layout map of PPC is also presented in this paper. Further, average
energy dissipation v’s kink energy, maximum energy dissipation v’s kink energy, minimum energy dissipation
v’s kink energy and average output node polarization v’s temperature are provided in this paper. The proposed
comparator forwards an improved ratio of 33.33% in gate count and ranging from 27.27% to 29.35% in garbage
outputs than its counterparts circuits, which ensure more scalable.
Adiabatic Logic Based Low Power Carry Select Adder for future TechnologiesIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
New Approaches for Harmonic Reduction Using Cascaded H-Bridge and Level Modulesijiert bestjournal
This paper analyzes and compares two approaches for dc to ac power conversion i.e. inverter . First method uses cascaded H - Bridge Inverter and second uses new Multi - level Scheme having Level Modules and H - Bridge. The simulation is done in MATLAB Software. Also the hardware can be done by taking the AC supply from the mains and converts it into DC suppl y by using rectifier. MOSFET can be used for switching purpose. The Total Harmon ic Distortion in output load voltage,produced by both the approaches is compared. It is shown that THD produced in second scheme is better up to a certain stages of the first scheme. The Total Harmonic Distortion produced in output load voltage when casca ded H - Bridge is used is 12.64% while t he Total Harmonic Distortion produced in output load voltage when Level Modules and H - Bridge are used is 7.94%.
DESIGN & ANALYSIS OF A CHARGE RE-CYCLE BASED NOVEL LPHS ADIABATIC LOGIC CIRCU...VLSICS Design
This paper focuses on principles of adiabatic logic, its classification and comparison of various adiabatic logic designs. An attempt has been made in this paper to modify 2PASCL (Two Phase Adiabatic Static CMOS Logic) adiabatic logic circuit to minimize delay of the different 2PASCL circuit designs. This modifications in the circuits leads to improvement of Power Delay Product (PDP) which is one of the figure of merit to optimize the circuit with factors like power dissipation and delay of the circuit. This paper investigates the design approaches of low power adiabatic gates in terms of energy dissipation and uses of Simple PN diode instead of MOS diode which reduces the effect of Capacitances at high transition and power clock frequency. A computer simulation using SPECTRE from Cadence is carried out on different adiabatic circuits, such as Inverter, NAND, NOR, XOR and 2:1 MUX.
Design of a Low Power Combinational Circuit by using Adiabatic LogicIJERA Editor
A novel low power and Positive Feedback Adiabatic Logic (PFAL) combinational low power circuit is presented in this paper. The power consumption and general characteristics of the PFAL combinationallow power circuit arethen compared against two combinational low power circuit Efficient Charge Recovery Logic (ECRL), Conventional CMOS. The proposed PFAL combinational low power circuit design was proven to be superior to the other two designs in power dissipation and area. The combination of low power and low transistor count makes the new PFAL cell a viable option for low power design.
International Journal of Engineering Research and Applications (IJERA) is a team of researchers not publication services or private publications running the journals for monetary benefits, we are association of scientists and academia who focus only on supporting authors who want to publish their work. The articles published in our journal can be accessed online, all the articles will be archived for real time access.
Our journal system primarily aims to bring out the research talent and the works done by sciaentists, academia, engineers, practitioners, scholars, post graduate students of engineering and science. This journal aims to cover the scientific research in a broader sense and not publishing a niche area of research facilitating researchers from various verticals to publish their papers. It is also aimed to provide a platform for the researchers to publish in a shorter of time, enabling them to continue further All articles published are freely available to scientific researchers in the Government agencies,educators and the general public. We are taking serious efforts to promote our journal across the globe in various ways, we are sure that our journal will act as a scientific platform for all researchers to publish their works online.
In power engineering the power flow analysis (also known as load flow study) is an important tool involving numerical analysis applied to a powe r system. This project deals with a model of existing power system using the actual data taking care of all parameters required for the simulation and analysis. With the help of Maharasht ra State Electricity Transmission co. Ltd.,a model of 220KV lines,of Solapur District grid usin g MATLAB software will be modeled. In this project,an algorithm will be used for power f low study and data collection and coding required for modeling. Load flow studies will be ca rried out using Newton Raphson method and voltage profile of buses will be analyzed. New meth od for the improvement of voltage profile will be suggested and analyze using the developed m odel. The optimization techniques include power factor compensation,tap changing,up gradati on of substation,up gradation of line and load shifting will be analyzed. Importance of power flow or Load flow studies is in planning future expansion of power system as well as determi ning the best operation of existing systems. From results of simulation buses with low voltage p rofile will be identified and possible solutions can be suggested.
Designing Conservative Reversible N-Bit Binary Comparator for Emerging Quantu...VIT-AP University
The quantum-dot cellular automata (QCA) has more advantages than CMOS regarding area and power. This
work targets a conservative reversible comparator and its realization in QCA. In this work, we construct a
conservative reversible comparator with an optimal value of reversible metrics. In state to design, three conservative
reversible gates, namely PPC, PPNG-1 and PPNG-2 (PP = parity-preserving, C = comparator, N = new,
G = gate), are proposed. Furthermore, the quantum equivalent of 1-bit and 2-bit comparator is presented. The
proposed concept has been implemented through an algorithm for the n-bit comparator. Also, PPC workability
is tested in QCA. The PPC has been performing 1-bit comparator result with minimum area, cell complexity,
and latency, which is found to be 0.52 m2, 387 and 1 respectively. In addition, the complete energy dissipation
analysis to explore such as a thermal layout map of PPC is also presented in this paper. Further, average
energy dissipation v’s kink energy, maximum energy dissipation v’s kink energy, minimum energy dissipation
v’s kink energy and average output node polarization v’s temperature are provided in this paper. The proposed
comparator forwards an improved ratio of 33.33% in gate count and ranging from 27.27% to 29.35% in garbage
outputs than its counterparts circuits, which ensure more scalable.
Adiabatic Logic Based Low Power Carry Select Adder for future TechnologiesIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
New Approaches for Harmonic Reduction Using Cascaded H-Bridge and Level Modulesijiert bestjournal
This paper analyzes and compares two approaches for dc to ac power conversion i.e. inverter . First method uses cascaded H - Bridge Inverter and second uses new Multi - level Scheme having Level Modules and H - Bridge. The simulation is done in MATLAB Software. Also the hardware can be done by taking the AC supply from the mains and converts it into DC suppl y by using rectifier. MOSFET can be used for switching purpose. The Total Harmon ic Distortion in output load voltage,produced by both the approaches is compared. It is shown that THD produced in second scheme is better up to a certain stages of the first scheme. The Total Harmonic Distortion produced in output load voltage when casca ded H - Bridge is used is 12.64% while t he Total Harmonic Distortion produced in output load voltage when Level Modules and H - Bridge are used is 7.94%.
DESIGN & ANALYSIS OF A CHARGE RE-CYCLE BASED NOVEL LPHS ADIABATIC LOGIC CIRCU...VLSICS Design
This paper focuses on principles of adiabatic logic, its classification and comparison of various adiabatic logic designs. An attempt has been made in this paper to modify 2PASCL (Two Phase Adiabatic Static CMOS Logic) adiabatic logic circuit to minimize delay of the different 2PASCL circuit designs. This modifications in the circuits leads to improvement of Power Delay Product (PDP) which is one of the figure of merit to optimize the circuit with factors like power dissipation and delay of the circuit. This paper investigates the design approaches of low power adiabatic gates in terms of energy dissipation and uses of Simple PN diode instead of MOS diode which reduces the effect of Capacitances at high transition and power clock frequency. A computer simulation using SPECTRE from Cadence is carried out on different adiabatic circuits, such as Inverter, NAND, NOR, XOR and 2:1 MUX.
Design of a Low Power Combinational Circuit by using Adiabatic LogicIJERA Editor
A novel low power and Positive Feedback Adiabatic Logic (PFAL) combinational low power circuit is presented in this paper. The power consumption and general characteristics of the PFAL combinationallow power circuit arethen compared against two combinational low power circuit Efficient Charge Recovery Logic (ECRL), Conventional CMOS. The proposed PFAL combinational low power circuit design was proven to be superior to the other two designs in power dissipation and area. The combination of low power and low transistor count makes the new PFAL cell a viable option for low power design.
International Journal of Engineering Research and Applications (IJERA) is a team of researchers not publication services or private publications running the journals for monetary benefits, we are association of scientists and academia who focus only on supporting authors who want to publish their work. The articles published in our journal can be accessed online, all the articles will be archived for real time access.
Our journal system primarily aims to bring out the research talent and the works done by sciaentists, academia, engineers, practitioners, scholars, post graduate students of engineering and science. This journal aims to cover the scientific research in a broader sense and not publishing a niche area of research facilitating researchers from various verticals to publish their papers. It is also aimed to provide a platform for the researchers to publish in a shorter of time, enabling them to continue further All articles published are freely available to scientific researchers in the Government agencies,educators and the general public. We are taking serious efforts to promote our journal across the globe in various ways, we are sure that our journal will act as a scientific platform for all researchers to publish their works online.
In power engineering the power flow analysis (also known as load flow study) is an important tool involving numerical analysis applied to a powe r system. This project deals with a model of existing power system using the actual data taking care of all parameters required for the simulation and analysis. With the help of Maharasht ra State Electricity Transmission co. Ltd.,a model of 220KV lines,of Solapur District grid usin g MATLAB software will be modeled. In this project,an algorithm will be used for power f low study and data collection and coding required for modeling. Load flow studies will be ca rried out using Newton Raphson method and voltage profile of buses will be analyzed. New meth od for the improvement of voltage profile will be suggested and analyze using the developed m odel. The optimization techniques include power factor compensation,tap changing,up gradati on of substation,up gradation of line and load shifting will be analyzed. Importance of power flow or Load flow studies is in planning future expansion of power system as well as determi ning the best operation of existing systems. From results of simulation buses with low voltage p rofile will be identified and possible solutions can be suggested.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design of 6 bit flash analog to digital converter using variable switching vo...VLSICS Design
This paper presents the design of 6-bit flash analog to digital Converter (ADC) using the new variable
switching voltage (VSV) comparator. In general, Flash ADCs attain the highest conversion speed at the
cost of high power consumption. By using the new VSV comparator, the designed 6-bit Flash ADC exhibits
significant improvement in terms of power and speed of previously reported Flash ADCs. The simulation
result shows that the converter consumes peak power 2.1 mW from a 1.2 V supply and achieves the speed of
1 GHz in a 65nm standard CMOS process. The measurement of maximum differential and integral
nonlinearities (DNL and INL) of the Flash ADC are 0.3 LSB and 0.6 LSB respectively.
Design and Analysis of Multi Vt and Variable Vt based Pipelined Adder for Lo...VLSICS Design
Majority of Digital Signal Processing (DSP) applications require arithmetic blocks such as multipliers and adders for hardware realization of complex algorithms. Power consumption of arithmetic blocks need to be minimized by use of low power techniques. In this paper, an experimental setup is developed to identify the sources of power dissipation and remedies that can be adopted to minimize power dissipation in arithmetic blocks. Use of low power techniques such as Multi Vt, variable Vt, pipelining, geometry scaling and use of appropriate load capacitance have been used to reduce power dissipation. A 4-bit pipelined adder is designed and the power dissipation is reduced to 4.17µW from 9.6µW. The designed pipelined adder can be used for DSP applications.
.
Differential Evolution Based Optimization Approach for Power Factor CorrectionIDES Editor
In radial distribution systems, the voltages at buses
reduces when moved away from the substation, also the losses
are high. The reason for decrease in voltage and high losses is
the insufficient amount of reactive power, which can be
provided by the shunt capacitors. For this purpose, in this
paper, two stage methodologies are used. In first stage, the
load flow of pre-compensated distribution system is carried
out using ‘Dimension reducing distribution load flow
algorithm’. In the second stage, Differential Evolution (DE)
technique is used to determine the optimal location and size
of the capacitors. The above method is tested on IEEE 69 bus
system. In this paper a new method is proposed to improve the
power factor of those buses having low power factor (less than
0.8lag) to unity power factor simultaneously by placing the
capacitors.
The CMOS faces challenges related to the increment in leakage-current to power-consumption. QCA is a promising alternative to overcome these challenges successfully. On the other hand, reversible logic plays a significant role in quantum-computing. Keeping this technique in mind, a conservative-reversible flip flops and counter are explored here which will bring QCA and reversible computing together in a singleplatform. In synthesizing, a reversible-conservative-quantum-cellular-automata (R-CQCA) is proposed. The proposed D, T, JK and dual-edge master-slave flip-flops advocate an improvement of 20%, 46.6%,
50%, and 36.66% respectively than its counterpart in quantum-cost. Further, the 100% fault-coverage
by stuck-fault is framed in R-CQCA, which can be useful for a tester to maintain data-integrity. Also, the R-CQCA layout is implemented in QCA, which achieve some parameters such as cell-complexity of 177, leakage-energy-dissipation of 0.1055 eV, and size of 0.24 mm2. Moreover, R-CQCA is better than FRG, RM, PPRG and MX-cqca regarding QCA-primitives are reported here.
INTRODUCTION BASIC TECHNIQUES TYPE OF BUSES
Y BUS MATRIX POWER SYSTEM COMPONENTS BUS ADMITTANCE MATRIX
Power (Load) flow study is the analysis of a power system in normal steady-state operation
This study will determine:
Fpga implementation of race control algorithm for full bridge prcp convertereSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
COMPREHENSIVE ANALYSIS AND SIMULATION OF MULTILEVEL POWER CONVERTERS TO CURTA...ecij
Present day industrial applications require higher power apparatus for power conversion. At medium
voltage grid, to connect only one power semiconductor switch directly is a not practically successful
concept. To overcome this multilevel power converter structure has been introduced and studied as an
alternative in high power and medium voltage applications. Renewable energy sources like photovoltaic,
wind, fuel cells can be conveniently interfaced to a multilevel converter system for high power applications.
In this study it is discussed in detail for different levels of the multilevel converters using pulse width
modulation technique (PWM) the harmonics contents decreases gradually. The simulated results are
presented and compared thereafter. Total harmonic distortion decreases as the number of levels increased
are tabulated accordingly. All the simulation results are carried out under MATLAB/Simulink environment.
A Novel Control Method for Unified Power Quality Conditioner Using Nine-Switc...IJERA Editor
A nine-switch power converter having two sets of out-put terminals was recently proposed in place of the traditional back-to-back power converter that uses 12 switches in total. The nine-switch converter has already been proven to have certain advantages, in addition to its component saving topological feature. Despite these advantages, the nine-switch converter has so far found limited applications due to its many perceived performance tradeoffs like requiring an oversized dc-link capacitor, limited amplitude sharing, and constrained phase shift between its two sets of output terminals. Instead of accepting these tradeoffs as limitations, a nine-switch power conditioner is proposed here that virtually “converts” most of these topological short comings into interesting performance advantages. Aiming further to reduce its switching losses, an appropriate discontinuous modulation scheme is proposed and studied here in detail to doubly ensure that maxi-mal reduction of commutations is achieved. With an appropriately designed control scheme then incorporated, the nine-switch converter is shown to favorably raise the overall power quality in experiment, hence justifying its role as a power conditioner at a reduced semiconductor cost.
1 ijaems oct-2015-3-design and development of novel matrix converter performanceINFOGAIN PUBLICATION
Matrix converter is a direct AC-AC converter topology that directly converts energy from an AC source to an AC load without the need of a bulky and limited lifetime energy storage element. Due to the significant advantages offered by matrix converter, such as adjustable power factor, capability of regeneration and high quality sinusoidal input/output waveforms. Matrix converter has been one of the AC–AC topologies that hasreceived extensive research attention for being an alternative to replace traditional AC-DC-AC converters in the variable voltage and variable frequency AC drive applications. In the present paper an indirect space vector modulated matrix converter is proposed. The basic idea of an indirect modulation scheme is to separately apply SVM to the rectification and inversion stages, before combining their switching states to produce the final gating signals. The paper encompasses development of a laboratory prototype of 230V, 250VA three phase to three phase DSP controlled matrix converter fed induction motor drive. The observations and real time testings have been carried out to evaluate and improve the stability of system under various typical abnormal input voltage conditions
SIMULTANEOUS OPTIMIZATION OF STANDBY AND ACTIVE ENERGY FOR SUB-THRESHOLD CIRC...VLSICS Design
Increased downscaling of CMOS circuits with respect to feature size and threshold voltage has a result of
dramatically increasing in leakage current. So, leakage power reduction is an important design issue for
active and standby modes as long as the technology scaling increased. In this paper, a simultaneous active
and standby energy optimization methodology is proposed for 22 nm sub-threshold CMOS circuits. In the
first phase, we investigate the dual threshold voltage design for active energy per cycle minimization. A
slack based genetic algorithm is proposed to find the optimal reverse body bias assignment to set of noncritical paths gates to ensure low active energy per cycle with the maximum allowable frequency at the
optimal supply voltage. The second phase, determine the optimal reverse body bias that can be applied to
all gates for standby power optimization at the optimal supply voltage determined from the first phase.
Therefore, there exist two sets of gates and two reverse body bias values for each set. The reverse body bias
is switched between these two values in response to the mode of operation. Experimental results are
obtained for some ISCAS-85 benchmark circuits such as 74L85, 74283, ALU74181, and 16 bit RCA. The
optimized circuits show significant energy saving ranged (from 14.5% to 42.28%) and standby power
saving ranged (from 62.8% to 67%).
IJCER (www.ijceronline.com) International Journal of computational Engineerin...ijceronline
Call for paper 2012, hard copy of Certificate, research paper publishing, where to publish research paper,
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJCER, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, research and review articles, IJCER Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathematics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer review journal, indexed journal, research and review articles, engineering journal, www.ijceronline.com, research journals,
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journal of engineering, online Submission
Optimal Body Biasing Technique for CMOS Tapered Buffer IJEEE
This paper represents Fixed Body Biased CMOS Tapered Buffer which is designed to minimize the average power dissipation across large capacitive load. The implementation of Reverse Body Bias (RBB) in the proposed Buffer chain is to vary Vth value of NMOS in the first stage. And with the increase in Vth /sub-threshold leakage current and power has been reduced. The technology constraints on the threshold voltage does not allow designer to set high threshold voltage for MOS devices. Hence, this was found that in proposed circuit that when optimal Reverse Body Bias value is set within (0.2 VDD to 0.4 VDD) range, the average power dissipation across capacitive load reduces to 82.2 % at very less penalty in delay. Thus CMOS buffer designers can use the proposed method to vary Vth while keeping VDD constant, which could improve the performance parameters of Tapered Buffer. The proposed analysis is verified by simulating the 3-stage tapered buffer schematics using standard 180nm CMOS technology in Cadence environment.
Energy Efficient Design of Multiplexer Using Adiabatic logicIJEEE
the increasing prominence of portable systems and the need to limit the power consumption in very high density VLSI chips have led to rapid and innovative developments in low power design during the recent years. The CMOS technology provides circuits with very low static power dissipation, during the switching operation currents are generated, due to the discharge of load capacitances that cause power dissipation increasing with the clock frequency. The adiabatic technique prevents such losses, the charge does not flow from the supply voltage to the load capacitance and then to ground, but it flows back to a trapezoidal or sinusoidal supply voltage and can be reused.In this paper a low 2:1 multiplexer is designed using positive feedback adiabatic logic. The design is simulated at .12µm technology using Microwind 3.1. Simulated results shows that proposed design saves 38% energy as compare to conventional CMOS design.
A RAIL-TO-RAIL HIGH SPEED CLASS-AB CMOS BUFFER WITH LOW POWER AND ENHANCED SL...VLSICS Design
A rail-to-rail class-AB CMOS buffer is proposed in this paper to drive large capacitive loads. A new
technique is used to reduce the leakage power of class-AB CMOS buffer circuits without affecting dynamic
power dissipation .The name of applied technique is LECTOR, which gives the high speed buffer with the
reduced low power dissipation (1.05%) and reduced area (2.8%). The proposed buffer is simulated at
45nm CMOS technology and the circuit is operated at 3V supply with cadence software. This analog circuit
is performed with extremely low leakage current as well as high current driving capability for the large
input voltages. The proposed paper is achieved very high speed with very low propagation delay range
i.e.(292×10-12). So the delay of the circuit is reduced to 10%. The settling time of this circuit is reduced by
24% (in ns) at 3V square wave input. The measured quiescent current is 41μA
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design of 6 bit flash analog to digital converter using variable switching vo...VLSICS Design
This paper presents the design of 6-bit flash analog to digital Converter (ADC) using the new variable
switching voltage (VSV) comparator. In general, Flash ADCs attain the highest conversion speed at the
cost of high power consumption. By using the new VSV comparator, the designed 6-bit Flash ADC exhibits
significant improvement in terms of power and speed of previously reported Flash ADCs. The simulation
result shows that the converter consumes peak power 2.1 mW from a 1.2 V supply and achieves the speed of
1 GHz in a 65nm standard CMOS process. The measurement of maximum differential and integral
nonlinearities (DNL and INL) of the Flash ADC are 0.3 LSB and 0.6 LSB respectively.
Design and Analysis of Multi Vt and Variable Vt based Pipelined Adder for Lo...VLSICS Design
Majority of Digital Signal Processing (DSP) applications require arithmetic blocks such as multipliers and adders for hardware realization of complex algorithms. Power consumption of arithmetic blocks need to be minimized by use of low power techniques. In this paper, an experimental setup is developed to identify the sources of power dissipation and remedies that can be adopted to minimize power dissipation in arithmetic blocks. Use of low power techniques such as Multi Vt, variable Vt, pipelining, geometry scaling and use of appropriate load capacitance have been used to reduce power dissipation. A 4-bit pipelined adder is designed and the power dissipation is reduced to 4.17µW from 9.6µW. The designed pipelined adder can be used for DSP applications.
.
Differential Evolution Based Optimization Approach for Power Factor CorrectionIDES Editor
In radial distribution systems, the voltages at buses
reduces when moved away from the substation, also the losses
are high. The reason for decrease in voltage and high losses is
the insufficient amount of reactive power, which can be
provided by the shunt capacitors. For this purpose, in this
paper, two stage methodologies are used. In first stage, the
load flow of pre-compensated distribution system is carried
out using ‘Dimension reducing distribution load flow
algorithm’. In the second stage, Differential Evolution (DE)
technique is used to determine the optimal location and size
of the capacitors. The above method is tested on IEEE 69 bus
system. In this paper a new method is proposed to improve the
power factor of those buses having low power factor (less than
0.8lag) to unity power factor simultaneously by placing the
capacitors.
The CMOS faces challenges related to the increment in leakage-current to power-consumption. QCA is a promising alternative to overcome these challenges successfully. On the other hand, reversible logic plays a significant role in quantum-computing. Keeping this technique in mind, a conservative-reversible flip flops and counter are explored here which will bring QCA and reversible computing together in a singleplatform. In synthesizing, a reversible-conservative-quantum-cellular-automata (R-CQCA) is proposed. The proposed D, T, JK and dual-edge master-slave flip-flops advocate an improvement of 20%, 46.6%,
50%, and 36.66% respectively than its counterpart in quantum-cost. Further, the 100% fault-coverage
by stuck-fault is framed in R-CQCA, which can be useful for a tester to maintain data-integrity. Also, the R-CQCA layout is implemented in QCA, which achieve some parameters such as cell-complexity of 177, leakage-energy-dissipation of 0.1055 eV, and size of 0.24 mm2. Moreover, R-CQCA is better than FRG, RM, PPRG and MX-cqca regarding QCA-primitives are reported here.
INTRODUCTION BASIC TECHNIQUES TYPE OF BUSES
Y BUS MATRIX POWER SYSTEM COMPONENTS BUS ADMITTANCE MATRIX
Power (Load) flow study is the analysis of a power system in normal steady-state operation
This study will determine:
Fpga implementation of race control algorithm for full bridge prcp convertereSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
COMPREHENSIVE ANALYSIS AND SIMULATION OF MULTILEVEL POWER CONVERTERS TO CURTA...ecij
Present day industrial applications require higher power apparatus for power conversion. At medium
voltage grid, to connect only one power semiconductor switch directly is a not practically successful
concept. To overcome this multilevel power converter structure has been introduced and studied as an
alternative in high power and medium voltage applications. Renewable energy sources like photovoltaic,
wind, fuel cells can be conveniently interfaced to a multilevel converter system for high power applications.
In this study it is discussed in detail for different levels of the multilevel converters using pulse width
modulation technique (PWM) the harmonics contents decreases gradually. The simulated results are
presented and compared thereafter. Total harmonic distortion decreases as the number of levels increased
are tabulated accordingly. All the simulation results are carried out under MATLAB/Simulink environment.
A Novel Control Method for Unified Power Quality Conditioner Using Nine-Switc...IJERA Editor
A nine-switch power converter having two sets of out-put terminals was recently proposed in place of the traditional back-to-back power converter that uses 12 switches in total. The nine-switch converter has already been proven to have certain advantages, in addition to its component saving topological feature. Despite these advantages, the nine-switch converter has so far found limited applications due to its many perceived performance tradeoffs like requiring an oversized dc-link capacitor, limited amplitude sharing, and constrained phase shift between its two sets of output terminals. Instead of accepting these tradeoffs as limitations, a nine-switch power conditioner is proposed here that virtually “converts” most of these topological short comings into interesting performance advantages. Aiming further to reduce its switching losses, an appropriate discontinuous modulation scheme is proposed and studied here in detail to doubly ensure that maxi-mal reduction of commutations is achieved. With an appropriately designed control scheme then incorporated, the nine-switch converter is shown to favorably raise the overall power quality in experiment, hence justifying its role as a power conditioner at a reduced semiconductor cost.
1 ijaems oct-2015-3-design and development of novel matrix converter performanceINFOGAIN PUBLICATION
Matrix converter is a direct AC-AC converter topology that directly converts energy from an AC source to an AC load without the need of a bulky and limited lifetime energy storage element. Due to the significant advantages offered by matrix converter, such as adjustable power factor, capability of regeneration and high quality sinusoidal input/output waveforms. Matrix converter has been one of the AC–AC topologies that hasreceived extensive research attention for being an alternative to replace traditional AC-DC-AC converters in the variable voltage and variable frequency AC drive applications. In the present paper an indirect space vector modulated matrix converter is proposed. The basic idea of an indirect modulation scheme is to separately apply SVM to the rectification and inversion stages, before combining their switching states to produce the final gating signals. The paper encompasses development of a laboratory prototype of 230V, 250VA three phase to three phase DSP controlled matrix converter fed induction motor drive. The observations and real time testings have been carried out to evaluate and improve the stability of system under various typical abnormal input voltage conditions
SIMULTANEOUS OPTIMIZATION OF STANDBY AND ACTIVE ENERGY FOR SUB-THRESHOLD CIRC...VLSICS Design
Increased downscaling of CMOS circuits with respect to feature size and threshold voltage has a result of
dramatically increasing in leakage current. So, leakage power reduction is an important design issue for
active and standby modes as long as the technology scaling increased. In this paper, a simultaneous active
and standby energy optimization methodology is proposed for 22 nm sub-threshold CMOS circuits. In the
first phase, we investigate the dual threshold voltage design for active energy per cycle minimization. A
slack based genetic algorithm is proposed to find the optimal reverse body bias assignment to set of noncritical paths gates to ensure low active energy per cycle with the maximum allowable frequency at the
optimal supply voltage. The second phase, determine the optimal reverse body bias that can be applied to
all gates for standby power optimization at the optimal supply voltage determined from the first phase.
Therefore, there exist two sets of gates and two reverse body bias values for each set. The reverse body bias
is switched between these two values in response to the mode of operation. Experimental results are
obtained for some ISCAS-85 benchmark circuits such as 74L85, 74283, ALU74181, and 16 bit RCA. The
optimized circuits show significant energy saving ranged (from 14.5% to 42.28%) and standby power
saving ranged (from 62.8% to 67%).
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Call for paper 2012, hard copy of Certificate, research paper publishing, where to publish research paper,
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Optimal Body Biasing Technique for CMOS Tapered Buffer IJEEE
This paper represents Fixed Body Biased CMOS Tapered Buffer which is designed to minimize the average power dissipation across large capacitive load. The implementation of Reverse Body Bias (RBB) in the proposed Buffer chain is to vary Vth value of NMOS in the first stage. And with the increase in Vth /sub-threshold leakage current and power has been reduced. The technology constraints on the threshold voltage does not allow designer to set high threshold voltage for MOS devices. Hence, this was found that in proposed circuit that when optimal Reverse Body Bias value is set within (0.2 VDD to 0.4 VDD) range, the average power dissipation across capacitive load reduces to 82.2 % at very less penalty in delay. Thus CMOS buffer designers can use the proposed method to vary Vth while keeping VDD constant, which could improve the performance parameters of Tapered Buffer. The proposed analysis is verified by simulating the 3-stage tapered buffer schematics using standard 180nm CMOS technology in Cadence environment.
Energy Efficient Design of Multiplexer Using Adiabatic logicIJEEE
the increasing prominence of portable systems and the need to limit the power consumption in very high density VLSI chips have led to rapid and innovative developments in low power design during the recent years. The CMOS technology provides circuits with very low static power dissipation, during the switching operation currents are generated, due to the discharge of load capacitances that cause power dissipation increasing with the clock frequency. The adiabatic technique prevents such losses, the charge does not flow from the supply voltage to the load capacitance and then to ground, but it flows back to a trapezoidal or sinusoidal supply voltage and can be reused.In this paper a low 2:1 multiplexer is designed using positive feedback adiabatic logic. The design is simulated at .12µm technology using Microwind 3.1. Simulated results shows that proposed design saves 38% energy as compare to conventional CMOS design.
A RAIL-TO-RAIL HIGH SPEED CLASS-AB CMOS BUFFER WITH LOW POWER AND ENHANCED SL...VLSICS Design
A rail-to-rail class-AB CMOS buffer is proposed in this paper to drive large capacitive loads. A new
technique is used to reduce the leakage power of class-AB CMOS buffer circuits without affecting dynamic
power dissipation .The name of applied technique is LECTOR, which gives the high speed buffer with the
reduced low power dissipation (1.05%) and reduced area (2.8%). The proposed buffer is simulated at
45nm CMOS technology and the circuit is operated at 3V supply with cadence software. This analog circuit
is performed with extremely low leakage current as well as high current driving capability for the large
input voltages. The proposed paper is achieved very high speed with very low propagation delay range
i.e.(292×10-12). So the delay of the circuit is reduced to 10%. The settling time of this circuit is reduced by
24% (in ns) at 3V square wave input. The measured quiescent current is 41μA
Adiabatic describe the thermodynamic processes in which there is no energy exchange with the environment, and therefore very less dissipated energy loss. These circuits are low power circuits which use reversible logic to conserve energy. Adiabatic logic works with the concept of switching activities which reduces the power by giving stored energy back to the supply. The main design changes are focused on power clock which plays the vital role in the principle of operation. This has been used because many adiabaticcircuits use a combined power supply and clock, or a power clock (Four Phase).To achieve this, the power supply of adiabatic logic circuits have used time varying voltage charging signal, in contrast to traditional non-adiabatic systems that have generally used constant voltage charging from a fixed-voltage power supply. Thereby the circuit topology and operation of the circuit has been changed so that the source current of CMOS transistor change its direction and goes back to the supply(Recovery) when the power clock falls from VDD to zero. Power efficient blocks can be designed by using adiabatic logic which can be used in combinational and sequential circuits. The simulation of the designs is done using a backend tool called MENTOR GRAPHICS in 130nm technology
A low power cmos analog circuit design for acquiring multichannel eeg signalsVLSICS Design
EEG signals are the signatures of neural activities and are captured by multiple-electrodes and the signals are recorded from pairs of electrodes. To acquire these multichannel signals a low power CMOS circuit was designed and implemented. The design operates in weak inversion region employing sub threshold
source coupled logic. A 16 channel differential multiplexer is designed by utilizing a transmission gate with
dynamic threshold logic and a 4 to 16 decoder is used to select the individual channels. The ON and OFF
resistance of the transmission gate obtained is 27 ohms and 10 M ohms respectively. The power dissipation
achieved is around 337nW for a dynamic range of 1μV to 0.4 V.
An Ultra-Low Power Robust Koggestone Adder at Sub-Threshold Voltages for Impl...VLSICS Design
The growing demand for energy constrained applications and portable devices have created a dire need for ultra-low power circuits. Implantable biomedical devices such as pacemakers need ultra-low power circuits for a better battery life for uninterrupted biomedical data processing. Circuits operating in subthreshold region minimize the energy per operation, thus providing a better platform for energy constrained implantable biomedical devices. This paper presents 8, 16 and 32-bit ultra-low power robust Kogge-Stone adders with improved performance. These adders operate at subthreshold supply voltages which can be used for low power implantable bio-medical devices such as pacemakers. To improve the performance of these adders in sub-threshold region, forward body bias technique and multi-threshold transistors are used. The adders are designed using NCSU 45nm bulk CMOS process library and the simulations were performed using HSPICE circuit simulator. Quantitative power-performance analysis is performed at slow-slow (SS), typical-typical (TT) and fast-fast (FF) corners clocked at 50 KHz for temperature ranging from 25̊C to 120̊C. For a supply voltage 0.3V, all the adders had the least PDP. Using 0.3V as the supply voltage, multi threshold voltage and forward body biasing techniques were applied to
further improve the performance of the adders. The PDP obtained using the forward body biasing technique shows an effective improvement compared to high threshold voltage and multi threshold voltage techniques. The forward biasing technique maintains a balance between delay reduction and increase in average power, thus reducing the power delay product when compared to the other two techniques.
AN ULTRA-LOW POWER ROBUST KOGGESTONE ADDER AT SUB-THRESHOLD VOLTAGES FOR IMPL...VLSICS Design
The growing demand for energy constrained applications and portable devices have created a dire need for
ultra-low power circuits. Implantable biomedical devices such as pacemakers need ultra-low power
circuits for a better battery life for uninterrupted biomedical data processing. Circuits operating in subthreshold
region minimize the energy per operation, thus providing a better platform for energy
constrained implantable biomedical devices. This paper presents 8, 16 and 32-bit ultra-low power robust
Kogge-Stone adders with improved performance. These adders operate at subthreshold supply voltages
which can be used for low power implantable bio-medical devices such as pacemakers. To improve the
performance of these adders in sub-threshold region, forward body bias technique and multi-threshold
transistors are used. The adders are designed using NCSU 45nm bulk CMOS process library and the
simulations were performed using HSPICE circuit simulator. Quantitative power-performance analysis is
performed at slow-slow (SS), typical-typical (TT) and fast-fast (FF) corners clocked at 50 KHz for
temperature ranging from 25̊C to 120̊C. For a supply voltage 0.3V, all the adders had the least PDP. Using
0.3V as the supply voltage, multi threshold voltage and forward body biasing techniques were applied to
further improve the performance of the adders. The PDP obtained using the forward body biasing
technique shows an effective improvement compared to high threshold voltage and multi threshold voltage
techniques. The forward biasing technique maintains a balance between delay reduction and increase in
average power, thus reducing the power delay product when compared to the other two techniques.
GENERIC SYSTEM VERILOG UNIVERSAL VERIFICATION METHODOLOGY BASED REUSABLE VERI...VLSICS Design
In this paper, we present Generic System Verilog Universal Verification Methodology based Reusable Verification Environment for efficient verification of Image Signal Processing IP’s/SoC’s. With the tight schedules on all projects it is important to have a strong verification methodology which contributes to First Silicon Success. Deploy methodologies which enforce full functional coverage and verification of corner cases through pseudo random test scenarios is required. Also, standardization of verification flow is needed. Previously, inside imaging group of ST, Specman (e)/Verilog based Verification Environment for IP/Subsystem level verification and C/C++/Verilog based Directed Verification Environment for SoC Level Verification was used for Functional Verification. Different Verification Environments were used at IP
level and SoC level. Different Verification/Validation Methodologies were used for SoC Verification across multiple sites. Verification teams were also looking for the ways how to catch bugs early in the design cycle? Thus, Generic System Verilog Universal Verification Methodology (UVM) based Reusable Verification Environment is required to avoid the problem of having so many methodologies and provides a standard unified solution which compiles on all tools.
Carbon nano tube based delay model for high speed energy efficient on chip da...elelijjournal
Speed is a major concern for high density VLSI networks. In this paper the closed form delay model for current mode signalling in VLSI interconnects has been proposed with resistive load termination.RLC interconnect line is modelled using characteristic impedance of transmission line and inductive effect.The inductive effect is dominant at lower technology node is modelled into an equivalent resistance. In this model first order transfer function is designed using finite difference equation, and by applying the boundary conditions at the source and load termination. It has been observed that the dominant pole determines system response and delay in the proposed model. Using CNIA tool (carbon nanotube interconnect analyzer) the interconnect line parameters has been estimated at 45nm technology node. The novel proposed current mode model superiority has been validated for CNT type of material. It superiority factor remains to 66.66% as compared to voltage mode signalling. And current mode dissipates 0.015pJ energy where as VM consume 0.045pJ for a single bit transmission across the interconnect over CNT
material. Secondly the damping factor of a lumped RLC circuit is shown to be a useful figure of merit.
Compact low power high slew-rate cmos buffer amplifier with power gating tech...VLSICS Design
A qualitative analysis of different parameters such as Phase noise, Slew rate and tranconductance by using
power gating reduction technique is presented. The circuit achieves the large driving capability by
employing simple comparators to sense the transients of the input to turn on the output stages, which are
statically off in the stable state. The effect of the different number of transistors and their topologies on the
phase noise and Slew rate is analyzed. Good agreement between qualitative and quantitative measurements
is observed. Scope of reducing of Noise and avoidance of Leakage due to various sources is discussed.
A Sub Threshold Source Coupled Logic Based Design of Low Power CMOS Analog Mu...VLSICS Design
A novel approach for designing Ultra Low Power and wide dynamic range circuit for multiplexing analog
signals is presented. The design operates in weak inversion (Sub threshold) region and uses Source -
Coupled Logic ( SCL) circuit. The bias current of the SCL gates is varied to scale down linearly the power
consumption and the operating frequency. The multiplexer design employs CMOS transistors as
transmission gate with dynamic threshold voltage. The design exhibits low power dissipation, high
dynamic range and good linearity. The design was implemented in 180 nm technology and was operated at
a supply voltage of 400 mV with a bias current ranging in the order of few Pico-amperes. The ON and
OFF resistance of the transmission gate achieved were 27 ohms and 10 M ohms respectively. The power
dissipation achieved is around 0.79 μW for a dynamic range of 1μV to 0.4 V.
Power Comparison of CMOS and Adiabatic Full Adder Circuits VLSICS Design
Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. Apart from the basic addition adders also used in performing useful operations such as subtraction, multiplication, division, address calculation, etc. In most of these systems the adder lies in the critical path that determines the overall performance of the system. In this paper conventional complementary metal oxide semiconductor (CMOS) and adiabatic adder circuits are analyzed in terms of power and transistor count using 0.18UM technology.
Implementation of Area Effective Carry Select AddersKumar Goud
Abstract: In the design of Integrated circuit area occupancy plays a vital role because of increasing the necessity of portable systems. Carry Select Adder (CSLA) is a fast adder used in data processing processors for performing fast arithmetic functions. From the structure of the CSLA, the scope is reducing the area of CSLA based on the efficient gate-level modification. In this paper 16 bit, 32 bit, 64 bit and 128 bit Regular Linear CSLA, Modified Linear CSLA, Regular Square-root CSLA (SQRT CSLA) and Modified SQRT CSLA architectures have been developed and compared. However, the Regular CSLA is still area-consuming due to the dual Ripple-Carry Adder (RCA) structure. For reducing area, the CSLA can be implemented by using a single RCA and an add-one circuit instead of using dual RCA. Comparing the Regular Linear CSLA with Regular SQRT CSLA, the Regular SQRT CSLA has reduced area as well as comparing the Modified Linear CSLA with Modified SQRT CSLA; the Modified SQRT CSLA has reduced area. The results and analysis show that the Modified Linear CSLA and Modified SQRT CSLA provide better outcomes than the Regular Linear CSLA and Regular SQRT CSLA respectively. This project was aimed for implementing high performance optimized FPGA architecture. Modelsim 10.0c is used for simulating the CSLA and synthesized using Xilinx PlanAhead13.4. Then the implementation is done in Virtex5 FPGA Kit.
Keywords: Field Programmable Gate Array (FPGA), efficient, Carry Select Adder (CSLA), Square-root CSLA (SQRTCSLA).
Design and Analysis of Multi Vt and Variable Vt based Pipelined Adder for Low...VLSICS Design
Majority of Digital Signal Processing (DSP) applications require arithmetic blocks such as multipliers and adders for hardware realization of complex algorithms. Power consumption of arithmetic blocks need to be minimized by use of low power techniques. In this paper, an experimental setup is developed to identify the sources of power dissipation and remedies that can be adopted to minimize power dissipation in arithmetic blocks. Use of low power techniques such as Multi Vt, variable Vt, pipelining, geometry scaling and use of appropriate load capacitance have been used to reduce power dissipation. A 4-bit pipelined adder is designed and the power dissipation is reduced to 4.17µW from 9.6µW. The designed pipelined adder can be used for DSP applications.
IMPLEMENTATION OF LOW POWER ADIABATIC SRAMVLSICS Design
In the featuring VLSI era, compact electronic devices are popular. The reliability and durability of such compact devices relies on low power utilization. The purpose of this project was to implement a low power adiabatic Static Random Access Memory (SRAM), with the following objectives - To reduce the power waste by means of stepwise charging using tank capacitors which is an adiabatic way of generating power
clock. This method is capable of recuperating the electrical energy back to the source. Further to examine the Static Noise Margin (SNM) – a parameter which gives detailed information about the cell stability – in
contrast with conventional 6T, 7T and 8T topologies of SRAM under 180 nm technology. Finally, SNM variations with respect to process parameters are also discussed. All the implementations and analysis were made using CADENCE tool and MATLAB tool.
IMPLEMENTATION OF LOW POWER ADIABATIC SRAMVLSICS Design
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variations with respect to process parameters are also discussed. All the implementations and analysis were made using CADENCE tool and MATLAB tool.
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SIMULTANEOUS OPTIMIZATION OF STANDBY AND ACTIVE ENERGY FOR SUB-THRESHOLD CIRCUITS
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.7, No.5/6, December 2016
DOI : 10.5121/vlsic.2016.7601 1
SIMULTANEOUS OPTIMIZATION OF STANDBY
AND ACTIVE ENERGY FOR SUB-THRESHOLD
CIRCUITS
Ali T. Shaheen and Saleem M. R. Taha
Department of Electrical Engineering, University of Baghdad, Iraq
ABSTRACT
Increased downscaling of CMOS circuits with respect to feature size and threshold voltage has a result of
dramatically increasing in leakage current. So, leakage power reduction is an important design issue for
active and standby modes as long as the technology scaling increased. In this paper, a simultaneous active
and standby energy optimization methodology is proposed for 22 nm sub-threshold CMOS circuits. In the
first phase, we investigate the dual threshold voltage design for active energy per cycle minimization. A
slack based genetic algorithm is proposed to find the optimal reverse body bias assignment to set of non-
critical paths gates to ensure low active energy per cycle with the maximum allowable frequency at the
optimal supply voltage. The second phase, determine the optimal reverse body bias that can be applied to
all gates for standby power optimization at the optimal supply voltage determined from the first phase.
Therefore, there exist two sets of gates and two reverse body bias values for each set. The reverse body bias
is switched between these two values in response to the mode of operation. Experimental results are
obtained for some ISCAS-85 benchmark circuits such as 74L85, 74283, ALU74181, and 16 bit RCA. The
optimized circuits show significant energy saving ranged (from 14.5% to 42.28%) and standby power
saving ranged (from 62.8% to 67%).
KEYWORDS
Dual Threshold Design, Slack Based Genetic Algorithm, Sub-threshold Circuits, Reverse Body Bias,
Standby Power
1. INTRODUCTION
Modern digital CMOS circuits explore dramatically leakage power increasing with each
generation. These technology scaling problems have recently made power reduction an important
design aspect. The well-known CMOS sub-threshold circuits are considered candidate solution
for energy constrained-low speed applications since it can significantly reduce energy per cycle
(EPC) due to its very low supply voltage. However, these circuits suffer from the large delay
which increases exponentially due to the exponential relation between the sub-threshold current
and the supply voltage whereas the delay in above threshold operation increases according to α-
power law [1].
The sub-threshold operation is a weak inversion mode depends on the sub-threshold current as the
main source of current. This current is summarized in Equation (1)
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.7, No.5/6, December 2016
2
I୪ୣୟ୩ୟୣ = ܫ exp ൬
ܸ௦ − ܸ௧
்ܸ݊
൰ 1 − exp ൬−
ܸௗௌ
்ܸ
൰൨ (1)
where
ܫ = ߤܥ௫
ܹ
ܮ
(݊ − 1)்ܸ
ଶ (2)
µ is effective mobility, Cox is oxide capacitance, W is transistor width, L is transistor length, Vds
is drain-source voltage, Vgs is gate-source voltage, VT is the thermal voltage, Vth is threshold
voltage and n is the sub-threshold slope, which is a technology determined parameter [2, 3].
According to this weak inversion operation, the power reduction techniques should be used with
special constraints for sub-threshold circuits due to its effects on the delay.
Unlike above threshold circuits, the EPC (power-delay product) in sub-threshold circuits may be
very high even when power consumption is small because of the large delay of such circuits.
Therefore the EPC is the key parameter that will determine whether this design is good or not [4].
This is demonstrated in Equation (3) which gives the approximate EPC for N-gates circuit. The 1st
term of Equation (3) represents the dynamic energy whereas the 2nd
term represents the static or
leakage energy.
ܧ = 0.5 ∝ (݅). .)݅(ܥ ܸ݀݀ଶ
+ ܲ (݅) . ܶ
ே
ୀଵ
(3)
where α(i) is the switching activity of the ith
node , C(i) is the capacitance of the ith
gate, Pleak(i) is
the leakage power of the ith
gate and T is the critical path delay.
Many researches were proposed for power optimization in sub-threshold circuits. Dual supply
sub-threshold circuit design work was presented by a research group at Auburn University [5-9].
In [6], the authors developed a slack based algorithm to achieve maximum energy per cycle
saving. Mixed integer linear programs (MILP) were developed in [8] to optimally assign dual
supply voltages to sub-threshold circuits in such a way to eliminate the required level converters.
Ultra-Dynamic Voltage Scaling (UDVS) was proposed for sub-threshold operation in [10]; the
power saving was achieved through the combination of dithering at high performance and
minimum energy operation for low performance scenarios.
On the other hand, dual-Vth design can be considered as a common method for reducing leakage
power consumption in above-threshold and sub-threshold operations [4]. The relevance of dual
threshold design for sub-threshold circuits stems from the use of high threshold voltage for some
gates on the off critical paths to reduce power consumption without affecting the critical path
delay.
In above threshold circuits, the dual threshold approach was proposed for power optimization
with various assignment algorithms under some constraint formulas [11-14]. For example in [12]
the researchers attempted to use linear programming (LP) to minimize the power under some
constraints on circuit speed, gate slack, delay and cell size. In [4] the dual threshold approach was
proposed for 32nm sub-threshold circuits using slack based heuristic algorithm. The author
showed the effectiveness of dual threshold voltage design for 32 nm sub-threshold circuits where
significant energy saving has been shown. However, these researches ignore the leakage power in
the standby mode of operation. The power optimization in this mode may be effective in some
applications when the device spends long periods idle. In [15], a standby energy analysis and
optimization technique were proposed for low supply applications. The interaction of the optimal
energy, cut-off structures, and supply voltage were investigated.
3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.7, No.5/6, December 2016
3
In this paper, we propose a simultaneous active and standby modes energy optimization technique
for 22nm sub-threshold circuits with non-zero standby applications. Firstly, the dual threshold
voltage design is investigated for active mode optimization. An optimal reverse body bias (RBB)
assignment is achieved using the proposed slack based genetic algorithm (SBGA) to ensure
maximum EPC saving with maximum allowable operation frequency at the optimal supply
voltage (Vddopt). Secondly, the optimal RBB for standby mode operation is evaluated to obtain
minimum standby power at the previously determined (Vddopt) for the active mode optimization.
A Variable threshold technique is used to simultaneously combine the two optimization phases
2. REVERSE BODY BIAS EFFECT
In CMOS circuits it is common to adjust the threshold voltage of MOSFET transistors by
applying a source-bulk bias voltage as given in Equation (4)
ܸ௧ = ܸ௧ + ߛ(ඥ⃓ − 2߶ி + ܸௌ⃓ − ඥ2߶ி) (4)
where Vtho is the zero body bias threshold voltage, VSB is the source-bulk bias voltage, 2ϕF is the
surface potential parameter, and γ is the body effect parameter. The RBB technique increases the
threshold voltage of a MOSFET by applying a negative voltage across the source-to-substrate p–n
junction whereas zero RBB is used in the structure of low Vth logic gates as demonstrated in
Figure 1. In Figure 1.a, a low Vth two input NAND gate is constructed with zero RBB by
grounding the fourth terminal of NMOS transistor and connecting the fourth terminal of PMOS
transistors to Vdd. The same gate is constructed in Figure1.b with non-zero RBB to increase the
threshold voltage [4, 16].
Although increasing the RBB voltage across the source-to-substrate p–n junction of a MOSFET
increases the threshold voltage, and consequently reducing the sub-threshold leakage current; the
RBB also increases the tunnelling leakage current at the reverse biased source-to-body and drain-
to-body p–n junctions.
When the RBB voltage is increased, both the bulk and surface band-to-band tunnelling current
components increase but the sub-threshold leakage current decreases. Therefore, there exist an
optimum RBB voltage (specific to a process technology) that minimizes the overall leakage
power consumption [17].
Figure 1. Two input NAND gate: (a) Low Vth (RBB=0); (b) High Vth (RBB= Vx)
4. International Journal of VLSI design & Communication Systems (VLSICS) Vol.7, No.5/6, December 2016
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3. CIRCUIT MODEL AND STATIC TIMING ANALYSIS
The first step in our design methodology is to classify the logic gates of the circuit according to
gate type and no. of inputs such as (AND2, AND3, AND4, OR2, etc.) all these gates are
considered with different fan-outs to cover all cases in the circuit. HSPICE is used to perform an
accurate simulation for each gate type in order to obtain a power-delay-capacitance library (PDC)
for all gates as shown in Figure 2. The library contains leakage power as a function of (Vdd and
RBB), gate delay as a function of (Vdd, RBB and fan-out or node capacitance) and node
capacitance as a function of (Vdd and Fan-out). The assignment algorithm depends on the library
content at each (Vdd and RBB values) to calculate and compare the overall power and delay.
The simulations must be performed under different values of the supply voltage (Vdd). For each
gate, the lower delay (DL) value is obtained with (RBB=0) design, whereas the higher delay
value (DH) occurs with specific RBB for a given Vdd and fan-out values. Depending on these
values our algorithm will optimally select some gates of the non-critical paths to be switched
from low threshold voltage design (RBB=0) to high threshold voltage design (RBB≠0) without
increasing the critical path delay of the circuit at the specific supply voltage.
Secondly, the combinational gate-level circuit is modeled as Directed Acyclic Graph (DAG), G=
(V, E) as shown in Figure 3. The logic gates represented as nodes or vertices within a set (V) and
the connections between nodes are represented as directed edges within edges set (E) from the
inputs to the outputs. Assign the first node to the Primary Inputs (PI) and the last node to the
Primary Outputs (PO).
Usually, static timing analysis is used to provide timing information and to calculate the actual
arrival time (AAT) and required arrival time (RAT) at the output of the gates. Also, STA is used
to find the critical path delay (T) and the slack of each gate (slk). The gate slack is defined as the
difference between the critical path delay and the maximum path delay through this gate; so it
represents the delay margin for each gate. For correct operation of the chip with respect to setup
(maximum path delay) constraints, it is required that AAT (v) ≤ RAT (v) [4, 18].
In this paper, we use the APAC (All paths and cycle) Algorithm proposed in [19] to get all paths
between any two nodes in a given DAG. Then by using the delay contents of the PDC library and
the APAC results we can find the arrival time of each node, critical path delay and the slack of
each node, as in the STA algorithm given in Table 1.
All paths from node (1) (primary inputs node) to any node (v) (primary outputs node) are given in
Step 4 of Table 1. These paths are represented by the indices of nodes along each path.
Consequently, after substituting the delay of each node from PDC library which may be DL or
DH according to the algorithm assignment, the maximum delay from node (1) to node (v) is
obtained. Similarly, the maximum delay from node (v) to node (N) (which is the primary output
node) is determined in step 9. In step 10 the longest path through each gate is calculated
depending on the previous results. The critical path delay of the overall circuit and the slack of
each gate are calculated in steps 11 and 12 respectively.
Finally, it is required to estimate the switching activity at each node to complete the circuit model
in order to evaluate and compare the EPC according to Equation (3). Probabilistic estimation is
used with the help of DAG analysis to evaluate the switching activity at each node, where the
roots of the inputs for each gate can be determined.
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Figure 2. Flow chart of PDC library simulation for each gate
Loop on Fan-out
End
Measure & save average static
power, delay& node cap. for all
possible input vectors
Gate Hspice Netlist
Param (Vdd, RBB, Fan-out)
Loop on RBB
End
Loop on Vdd
End
Store the Gate Library Result
Stp., Delay, and Cap.
function of (vdd, RBB,fan-out)
Increase
Fan-out
Increase RBB
Fan-out=1
Start with Vdd=Vdd1,
RBB=0, Fan-out=1
Increase Vdd
RBB=0
Fan-out=1
No
Yes
No
Yes
Yes
No
6. International Journal of VLSI design & Communication Systems (VLSICS) Vol.7, No.5/6, December 2016
6
(a) (b)
Figure 3. DAG of simple circuit: (a) Gate level representation; (b) DAG
Table 1. STA algorithm
1. Input: directed graph G =(V, E) and PDC library: where V is
set of circuit nodes V={v1 ,v2, . . . . vN}
2. Output: T: Critical Path delay and slk: slack of each gate
3. ∀ node v ∈ V find:
4. gpi{v}= APAC( G,1,v); all paths from node 1 to node v
5. gpo{v} = APAC( G,v,N); all paths from node v to node N
6. use gpi{v},gpo{v} and PDC Library to find:
7. D (v); delay of node v
8. TPI (v) ;the longest time from node 1 to node v,
9. TPO (v) ; the longest time from node v to node N
10. DP(v)=DPI(v)+TPO(v)+D(v) ;the longest path through node
v
11. T= max{ DP(v) } where v = 1 ∼ N ;critical path delay
12. slk (v)=T- DP(v) ;slack of each gate
4. PROPOSED METHODOLOGY
4.1. Phase 1- Active Mode Energy Optimization
In this phase, a dual threshold voltage design is applied to reduce the active mode EPC of sub-
threshold circuits in the 22nm scale. A framework is presented to find the optimal supply voltage
and the optimal dual threshold voltages using the proposed SBGA given in Table 2. This energy
minimization methodology depends on the optimal assignment of high threshold voltage (RBB
≠0) for some gates on the off-critical paths. The genetic algorithm is modified through the use of
STA given in Table 1 in such a way to assign dual threshold voltages to gates in sub-threshold
circuits without increasing the critical path delay at Vddopt. As seen from Table2, this algorithm
combines the original structure of the genetic algorithm with the STA algorithm given in
Table 1.
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As given in the previous section, each gate is designed with low threshold voltage transistors
(with RBB=0) and with high threshold voltage transistors (with RBB≠0) (as given in Figure 1 for
NAND2). The PDC library is evaluated for all gates under different values of fan-out, RBB and
supply voltage as given in Figure 2. Then the SBGA is automatically assign Vth-low design to
critical paths gates to maintain the performance. Consequently, SBGA also finds an optimal set of
gates on the off-critical paths that can be assigned to Vth-high design without any performance
degradation.
The first step in the proposed assignment algorithm (shown in Table 2) is to assign Vth-low
design for all gates so that the delay of any node D (v) will be DL (v). Through step 4 of Table2,
STA algorithm (given in Table 1) is applied to find the critical path delay (T) and the slack of
each gate slk (v). The critical path delay of this design at the specified Vdd is used as the timing
requirement for the dual threshold voltage design. In step 5, the Vth-high design is assigned for
all gates so that the delay of any node D (v) will be DH (v). STA algorithm is applied again to
find the new critical path delay (Thigh) and delta value for each gate ∆ (v) which equal to DH (v)-
DL (v). The upper and lower slack bounds used in the optimization are calculated in step 7. A set
of nodes that must be kept at Vth-low design is determined in step 8. The characteristic of these
nodes is to have small slack time less than the slack lower bound (SL). When any gate contained
in {Low_Set} is switched from Vth-low to Vth-high design, the delay of the gate is converted
from DL to DH and therefore gate slack will become negative as illustrated below in Equation
(4). However, our algorithm does not allow negative slack because negative gate slack means a
performance degradation occurred, where longest path delay exceeds the original circuit delay T.
Table 2. Slack Based Genetic Algorithm (SBGA)
1. ∀ ܸ݀݀ ∈ ൛ܸ݀݀ _ݐ݁ݏൟ do
2. ∀ ܴ݆ܤܤ ∈ ൛ܴܤܤ _ݐ݁ݏൟ do
3. Assign RBB=0 design for all gates
4. Apply STA algorithm and find: T, delay and slack of each gate DL(v) and slk(v) :
5. Assign RBB=RBBj for all gates
6. Apply STA algorithm an find: Thigh , and delay of each gate DH(v)
7. Calculate: k= Thigh/T ; ∆(v)=DH(v)-DL(v);
slack upper bound SU= (k-1).T/k and slack lower bound SL=min {∆(v)}
8. If slk (v) ≤ SL then v → {Low_Set} the indices set is {idx1} =0’s
and no. of nodes in the set =N1
9. If slk (v) ≥SU then v → {High_Set} the indices set is {idx2} =1’s
and no. of nodes in the set =N2
10. The remaining nodes grouped in a set { Rem_set} with indices set is {idx3}
and no. of nodes in the set=N3=N-N1-N2
11. Apply GA to { Rem_set}: to select which nodes assigned to RBBj (Vth-H)
12. Initialization: Select iterations no. , cross over prob., mutation prob. and population size
13. Pop: Initial population with random zeros and ones (M,N3) ; M: no. of chromosomes
14. ∀ chromosome Mx ∈ pop
15. Mix the three sets : {Low_Set} , {High_Set} and { Rem_set}
16. Apply STA algorithm: find inst. critical path delay Tx ,and energy Ex
17. Calculate fitness: Ex. Tx= ൫∑ 0.5 . α(i). C(i). Vddଶ
+ P୪ୣୟ୩ୟୣ(݅). Tx
୧ୀଵ ൯. ܶݔ
18. Apply selection: select the chromosomes of minimum fitness
19. New generation pop_new: Apply cross-over and mutation
20. ∀ Mx ∈ pop_new: repeat steps (14-18) until stop
21. End RBB loop
22. End -Vdd loop
Another set {High_Set} is determined in step 9 to contain all nodes that can be switched directly
to (Vth-high) design without affecting the critical path delay. The characteristic of these nodes is
to have large slack time greater than the slack upper bound (SU) which determined in step 7. So,
8. International Journal of VLSI design & Communication Systems (VLSICS) Vol.7, No.5/6, December 2016
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this assignment will still keep its slack non-negative, as illustrated below in Equations (5) and (6).
This step will reduce the complexity of the genetic algorithm where the unique solution (i.e. same
critical path delay of the original circuit) can be easily obtained.
Let us consider, slk* (v) is the updated gate slack and DP*(v) is the updated longest path delay of
gate v after it is switched from Vth-low design to Vth-high design. For the gates with gate slack
slk (v) < SL,
݈݇ݏ∗
()ݒ = ܶ − ܲܦ∗
()ݒ = ܶ − ሾ)ݒ(ܲܦ + ∆()ݒሿ = )ݒ(݈݇ݏ − ∆()ݒ (4)
Equation (4) will be negative since we define SL to be slk (v) < SL ≤ ∆ (v).
As for the gates whose gate slack slk (v) ≥ SU,
݈݇ݏ∗()ݒ = ܶ − ܲܦ∗()ݒ = ܶ − ݇. )ݒ(ܲܦ = ܶ − ݇. ሾܶ − )ݒ(݈݇ݏሿ (5)
From the definition of SU, we know that slk (v) ≥ SU = (k-1).T/k,
ܶ − ݇. ሾܶ − )ݒ(݈݇ݏሿ ≥ ܶ − ݇. ܶ + ݇. ܷܵ = 0 (6)
Therefore, Equation (5) remains non-negative after Vth-high assignment. Here an approximation
is used that k = Thigh/T≃ DP*(v)/DP (v).
The remaining nodes are grouped in a new set {Rem_set}, with nodes indices {idx3}. Some of
the nodes contained in this set are optimally assigned to Vth-high design through the application
of the modified genetic algorithm. The chromosome length should be the same as the number of
nodes contained in {Rem_set}. Binary encoding is used to represent the nodes in each individual.
(0) is used for Vth-low design assignment and (1) is used for Vth-high design assignment.
For each individual which represents the nodes of {Rem_set}, all above three sets are mixed
according to their node indices in order to generate a full vector that represents nodes indices of
the overall circuit. Depending on this vector and through the use of PDC library the instantaneous
EPC (Ex) is calculated. Also, the instantaneous critical path delay (Tx) is evaluated in step 16,
where STA algorithm is applied again and the delay of each node is D (v) which may be DL (v)
or DH (v) according to the gate index (v) in the final vector. These two objectives (Ex and Tx) are
multiplied to generate the fitness value as in step 17. A new generation is obtained after the
selection, cross-over and mutation steps. The genetic algorithm steps are repeated until the
minimum fitness value is obtained. As a result, the maximum delay after the dual threshold
voltage assignment does not exceed T (the critical path delay of the original circuit at the specific
supply voltage) and the optimized EPC is determined. This process repeated for all RBB values
and the presented framework find the optimal RBB value and optimal supply voltage operation.
4.2. Phase 2- Standby Leakage Power Minimization
As reported in the literature, the leakage power can be significantly reduced with the application
of reverse body bias voltage. Hence, a high reverse body bias can be applied to all gates when a
standby signal is detected. As a result, the threshold voltages of all gates are increased, and
therefore a significant leakage power reduction can be obtained. However, as given in section 2,
not all RBB values are allowed. The RBB voltage increasing results in sub-threshold leakage
current decreasing but both the bulk and surface band-to-band tunneling current components
increase. So, there exist an optimal RBB voltage for maximum standby leakage power saving.
The PDC library contains the static power for each gate type at different RBB and Vdd values.
9. International Journal of VLSI design & Communication Systems (VLSICS) Vol.7, No.5/6, December 2016
9
Hence, the static power of the overall circuit is evaluated at the optimal supply voltage
determined from phase1 as given in Equation (7). The calculations are performed for all RBB
values and the optimal RBB value for standby mode is the one corresponding to the minimum
standby power. This RBB should be applied for all gates during the standby interval.
ܲ_ݕܾ݀݊ܽݐݏ = ܲ(݅)
ே
ୀଵ
(7)
where Pleak(i) is the leakage power of the ith
gate.
From the active mode optimization phase, three design parameters are determined; the optimal set
of gates are to be modified (set A), the RBB bias value for these gates (Vx) and Vddopt. The
other gates (set B) should be assigned to RBB=0. On the other hand, the optimal RBB voltage for
minimum standby power consumption (Vy) is found through phase 2 at the previously
determined Vddopt. This RBB value (Vy) is assigned for all gates when a standby signal is
detected. Therefore, there are two sets of gates and two RBB values are determined for each set of
gates one for active mode and the other for standby mode of operation as shown in Figure 4
which demonstrate the variable threshold voltage design of an inverter CMOS gate.
Figure 4. Variable threshold CMOS inverter: (a) From set A of gates; (b) From set B of gates
5. EXPERIMENTAL RESULTS AND DISCUSSIONS
In this section, a simulation details and experimental results are given. The transistor model used
is PTM 22nm bulk CMOS technology with W=5L for NMOS transistors and W=12L for PMOS
transistors. HSPICE simulator is used to simulate all gates with and without RBB under different
values of Vdd and fan-outs. Hence, the gate data library for each gate in the simulated circuits is
obtained. The framework finds the optimal supply voltage and optimal reverse body bias (RBB)
for minimum EPC. Optimal dual threshold assignment is achieved through the use of the
proposed SBGA to ensure operation at the maximum allowable frequency at (Vddopt). The
supply voltage used in our simulations is ranged from 0.25 V to 0.4 V in step of 0.01 V (i.e. 16
values of supply voltage are used), and RBB voltage is ranged from 0.1 V to 1 V.
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Experimental results of dual Vth design and single Vth-low design are obtained and compared for
some benchmark circuits (16bit RCA, 74L85, 74283 andALU7418) where the amount of energy
saving that achieved by dual threshold assignment is influenced by the circuit topology. The EPC
simulations of these circuits are shown in Figure 5, Figure 7, Figure 9, and Figure 10 respectively.
Table 3 gives more detailed analysis, where (optimal EPC, Vddopt, RBB, operation frequency,
and percentage of Vth-high gates) are given for all circuits. For each (Vdd and RBB combination)
the algorithm is applied to select some gates of the non-critical paths to be switched from Vth-low
to Vth-high through the application of RBB to these gates. EPC is calculated for the new design
at the specific RBB for all Vdd values. Each RBB results in one curve as shown in EPC Figures
and there exist a minimum EPC at an optimal Vdd. The lowest energy occurs at Vddopt of the
lowest energy curve, i.e. the optimal Vdd-optimal RBB.
Maximum active mode energy saving (42.28%) is achieved for the 16 bit RCA at optimal RBB
(0.7 V) and Vddopt (0.3 V) which corresponds to (10.91 MHz) clock frequency. The 16 bit RCA
circuit explores a large number of short off-critical paths and the path length difference between
the critical path and off-critical paths is sufficiently large. Therefore, it allows more gates (60.2%
of total gates) to be assigned to 0.7V RBB. Gate slack distribution of 16 bit RCA circuit with and
without optimization is shown in Figure 6. The non-optimized 16 bit RCA circuit has an optimal
EPC (4.29 fJ) occurs at Vddopt (0.32V) which corresponds to clock frequency (12.041 MHz).
From Figure 5 we can find that EPC of the optimal dual threshold design is (2.515 fJ) at Vdd
(0.32V), so there exist a significant EPC saving (41.37%) even for the same operation frequency
of the non-optimized circuit (12.041 MHz). Similar aspect can be noted for all simulated circuits.
Alternatively, we can design the circuits to operate with lower energy saving at Vdd greater than
Vddopt and improve the performance where this aspect is required for some applications
especially for large circuits or circuits that have long critical paths. So, the critical path delay is
large and resulting in low operation frequency.
Figure 5. EPC of 16 bit RCA circuit for single and dual Vth design
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Figure 6. Gate slack distribution of 16 bit RCA: (a) Single Vth-Low (RBB=0) at Vdd= 0.3V; (b) Dual- Vth
at Vdd= 0.3V and RBB=0.7V
The lower bound of active energy saving (14.58%) is achieved for the 74L85 circuit at Vddopt
(0.31V) since its balanced structure result in a large number of candidate gates with small slack
time and few gates with relatively large slack time as shown in Figure 8. So, the algorithm
selected the RBB (0.2V) as an optimum case which considered suitable for all candidate gates.
This is due to the proportional relation between the gate delay and the applied RBB value.
However, RBB of 0.2V result will optimally exploit the available slack time but the energy
saving will be small as compared with other circuits.
The other two circuits show EPC saving of (21% and 15.27%) for 74283 and ALU74181,
respectively, as given in Table 3 where more details can be found.
Figure 7. EPC of 74L85 circuit for single and dual Vth design
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Figure 8. Gate slack distribution of 74L85: (a) Single Vth-low (RBB=0) at Vdd= 0.31V; (b) Dual Vth at
Vdd= 0.31V and RBB=0.2V
Figure 9. EPC of 74283 circuit for single and dual Vth design
Figure 10. EPC of ALU74181 circuit for single and dual Vth design
13. International Journal of VLSI design & Communication Systems (VLSICS) Vol.7, No.5/6, December 2016
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Table 3. Experimental results of simulated circuits.
Circuit Design EPC
(f J)
Freq.
(MHz)
Vddopt RBB EPC
Saving
Vth-H
gates%
16 bit
RCA
Single-Vth 4.290 12.041 0.32V 0 - -
Dual_Vth 2.476 10.91 0.3V 0.7V 42.28% 60.2 %
74283 Single-Vth 0.403 17.685 0.32 V 0 - -
Dual_Vth 0.318 17.01 0.3 V 0.3V 21 % 61.5%
ALU
74181
Single-Vth 0.694 17.216 0.32V 0 - -
Dual_Vth 0.588 17.216 0.32V 0.3V 15.27% 57.6%
74L85 Single-Vth 0.459 17.142 0.31V 0 - -
Dual_Vth 0.392 17.142 0.31V 0.2V 14.58% 54.3%
The other part of the results is the standby mode simulation results. Figure 11 shows the standby
leakage power of the 16 bit RCA for different values of RBB and Vdd. As seen from this figure,
the leakage power is reduced with the increasing of the RBB but and the maximum power saving
(67%) is occur at (RBB= 0.8V). For more RBB increasing, the case is reversed. The circuit
supply voltage should be equal (Vddopt) obtained from active mode optimization (0.3V). Similar
simulations are performed for the other circuits as given in Table 4.
Figure 11. Standby leakage power for 16 bit RCA
Table 4. Experimental results of simulated circuits in standby mode.
Circuit non_optm
Pstby
Optm.
Pstby
Vddopt Optimal
RBB
Saving
16 bit-RCA 1.035 ߤw 0.341ߤw 0.3V 0.8V 67%
74L85 0.456ߤw 0.165ߤw 0.31V 0.8V 63.8%
ALU74181 0.706ߤw 0.262ߤw 0.32V 0.8V 62.88%
74283 0.358ߤw 0.12ߤw 0.3V 0.8V 66.48%
14. International Journal of VLSI design & Communication Systems (VLSICS) Vol.7, No.5/6, December 2016
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6. CONCLUSIONS
Some applications in the market may require minimum energy consumption in deep submicron
technologies for both active and standby modes. Ignoring standby leakage current in sub-
threshold can significantly impact the energy efficiency of the design. In this paper, a combined
standby and active modes energy optimization methodology is proposed for non-zero standby
22nm sub-threshold circuits. In the first part of the paper, the validation of dual threshold voltage
design for runtime energy minimization was investigated. A slack based genetic algorithm is used
to find the optimal RBB or (optimal Vth) and the optimal supply voltage to ensure low EPC
operation with the maximum allowable frequency at (Vddopt). According to the obtained results,
it is clear that the dual threshold voltage design still has an important role in energy optimization
for 22nm sub-threshold circuits. The 16 bit RCA shows a maximum slack time utilization, where
(42.28%) EPC reduction is obtained as compared with the non-optimized circuit. Whereas the
minimum EPC reduction (14.58%) is obtained for the 74L85 circuit. The other two benchmark
circuits; 74283 and ALU74181 result in (21%) and (15.27%) EPC reduction, respectively. This
variation in EPC reduction is due to the topology of the circuit, and the available slack time from
the off-critical paths to be utilized.
In the second part of the paper, a variable threshold standby power minimization approach is
integrated with the active mode energy optimization given in part1. A significant standby leakage
power saving on average of (65%) is obtained. This shows the impact of leakage reduction in
standby mode and how can this affect the energy efficiency of the design, especially for non-zero
standby circuits.
As future works, other techniques can be integrated with this approach such as sizing technique
transistor stacking, gate replacement techniques, and Multi-Vth technique. For efficient slack
time exploiting and greater energy reduction, different gate designs can be used. Moreover,
aggressive downscaling may display higher leakage current in the sub-threshold region, so it is
worth to explore the validation of dual threshold design in the future CMOS technologies.
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AUTHORS
Ali T. Shaheen received his B.S. degree in electrical engineering from University of Baghdad in July 2000,
and his M.S. degree in electronic and communication from University of Baghdad, Iraq in 2007. He is
working as a lecturer in the Electrical Engineering Department, University of Baghdad and currently he is a
Ph.D. research student in the same university. His research interests include the fields of digital signal
processing, communication and currently he is working on the field of low power electronic circuits.
Saleem M. R. Taha received the B.S. degree in electrical engineering with elective courses in computer
science, the Higher Diploma degree in electronics and communications, the M.S. degree in digital systems
design, and the Ph.D. degree in reversible and quantum computations from the University of Baghdad,
Baghdad, Iraq, in 1978, 1980, 1982 and 2011, respectively. In May 1983 he joined the Department of
Electrical Engineering, College of Engineering, University of Baghdad, and since July 1998 he has been a
Professor at that university. He has supervised more than fifty M.S. and Ph.D. research students. In
16. International Journal of VLSI design & Communication Systems (VLSICS) Vol.7, No.5/6, December 2016
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addition, he has contributed to and authored more than sixty five papers in the areas of hybrid circuit
design, digital signal processing, digital instrumentation and measurements, microcomputer applications,
biomedical engineering, computer-aided design, reversible and quantum computations.