The document discusses the design of an energy-efficient 2:1 multiplexer using adiabatic logic, focusing on power consumption reduction in high-density VLSI chips. The proposed design shows a 38% energy saving compared to conventional CMOS designs, leveraging the ability to recycle energy through adiabatic switching principles. Various logic styles are compared, with results indicating that the adiabatic multiplexer outperforms traditional counterparts in terms of energy efficiency and drain current.

1. Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426
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Energy Efficient Design of Multiplexer Using
Adiabatic logic
1
Richa Singh, 2
Prateek Raj Gautam, 3
Anjali Sharma
1,2
Dept.of Electronics& Communication, Allen House Institute of Technology, Rooma, Kanpur,India
Dept.of Electronics & Communication, AP Goyal University, Shimla, India
1
singhricha51@gmail.com, 2
prateekrajgautam@gmail.com, 3
Anjali.iitt@gmail.com
Abstract—the increasing prominence of portable systems and
the need to limit the power consumption in very high density
VLSI chips have led to rapid and innovative developments in
low power design during the recent years. The CMOS
technology provides circuits with very low static power
dissipation, during the switching operation currents are
generated, due to the discharge of load capacitances that
cause power dissipation increasing with the clock frequency.
The adiabatic technique prevents such losses, the charge does
not flow from the supply voltage to the load capacitance and
then to ground, but it flows back to a trapezoidal or
sinusoidal supply voltage and can be reused.In this paper a
low 2:1 multiplexer is designed using positive feedback
adiabatic logic. The design is simulated at .12µm technology
using Microwind 3.1. Simulated results shows that proposed
design saves 38% energy as compare to conventional CMOS
design.
Keywords- VLSI, PFAL, Adiabatic, BSIM, Multiplexer.
INTRODUCTION
The need for low power design is becoming a major issue
in high performance digital systems, such as
microprocessors, digital signal processors, and other
application. The common traits of high performance chips
are the high integration density and high clock frequency.
The power dissipation of the chip, and thus, the
temperature, increases with the increasing clock frequency.
Since the dissipated heat must be removed effectively to
keep the chip temperature at an acceptable level. There are
many ways t achieve low power in digital circuits, it
involves reduction of the switching events, decrease the
node capacitance, reduce the voltage swing or apply a
combination of these methods. Yet in all these methods
energy drawn from the power supply is used only once
before being dissipated[1].
.
In CMOS logic design half of the power is dissipation in
PMOS network and stored energy is dissipated during
discharging process of output load capacitor during the
switching events. Most of the power consumption
reduction techniques are based upon scaling of the supply
voltage, reducing capacitance and switching activity. Yet
in all these cases, energy drawn from the power supply is
used only once before being dissipated. Thus to increase
the energy efficiency of logic circuits, a technique is
required that can reuse the energy stored on load capacitor.
It has been found that there is a fundamental relation
between computation and power dissipation. That is if
somehow computation could be implemented without any
loss of information, then the energy required by it could be
potentially reduced to zero. This can be done by
performing all computation in reversible manner. Also
energy dissipation depends upon average voltage drop
traversed by charge that flows on to the load capacitance
[2-3]. By using smaller voltage steps or increments
dissipation can be reduced [3]. The minimum power
consumption during the charge transfer phase is termed as
adiabatic switching.
Fig.1 Conventional CMOS logic circuit with pull-up (F) and pull-down
(/F) networks
ADIABATIC PRINCIPLE
Most of the power saving techniques involved scaling of
the power supply, which results, substantial increase in
subthreshold leakage current also it causes uncertainty in
the process variation. Therefore some other technique is
required which is independent of voltage scaling. It has
been found that there is fundamental connection between
computation and power dissipation. That is if somehow
computation could be implemented without any loss of
information, then energy required by it could be potentially
reduced to zero. This can be achieved by performing all the
computation in a reversible manner. Thus minimum power
consumption during charge transfer phase is known as
adiabatic switching [4].
In Fig. 2output load capacitance is charged by a constant
current source instead of a constant voltage source used in
conventional CMOS structures. This circuit is same as the
equivalent model used in charging process in conventional
CMOS. On resistance of pull up PMOS network is
represented by R and C0 is the output capacitance. It is
noted that constant charging current corresponds to a linear
voltage ramp. Energy dissipated through adiabatic logic is
given as [5-6]

2. Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426
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 TVC
T
RC
E Cd
2
.. (1)
Fig.2 Equivalent model during charging phase in adiabatic circuits [4]
It can be seen from equation from equation 1 that If
charging period T is larger than 2RC then dissipated
energy can be made smaller than Conventional CMOS
circuit. Thus dissipated energy can be made arbitrarily
small by increasing the charging period. Hence by using
constant current source energy can be transferred from
supply to load capacitor with any dissipation and the
energy stored on the load capacitance after charging
process send back to the supply voltage by simply
reversing the direction of current source. Thus recycling is
very attractive feature in adiabatic logic. The constant
current supply must be capable of retrieving the charge
back to the power supply as shown in fig. 2. Adiabatic
circuits does not use standard power supply instead of this
it uses pulsating power supply which is also called as
pulsed power supply[7-8].
PREVIOUS WORK
A logic style is the way how a logic function is derived
from a set of transistors. It affects the speed, size, and
power consumption and wiring complexity of a circuit. All
these characteristics may vary considerably from one logic
style to another and thus make the proper choice of logic
style crucial for circuit performance. Cascade voltage logic
switch (CVSL) is developed by IBM. Later it is known as
differential cascade switch logic (DCVSL) shown in fig. 3.
The designing of DCVSL logic style requires both its true
andcomplementary signal to be routed. It is made of two n-
type switching networks and two p-type switching networks
connected in a cross coupled manner to VDD. The
MDCVSL stands for modified differential cascade voltage
switch logic. Delay has been improved by adding two
NMOS in the previous design. It is shown in fig. 4 this
circuit also provides self checking feature that is if circuit is
operating correctly, the values at the output may assume 0-1
or 1-0 means the combination such as 0-0 or 1-1 will never
occur[9].
Complementary pass transistor logic (CPL) is based upon
pass transistors networks. The CPL circuit requires
complementary inputs and generates complementary
outputs to pass on the next CPL that is in this logic for
every signal its complement is generated. Elimination of
PMOS transistors reduces the parasitic capacitances
associated with each node in the circuit Gates are static,
because the output is connected to either VDD or GND.
Design is modular; same cell can produce various gates by
simply permuting the input signals. CPL requires fewer
transistors[10-11]. The threshold voltages of NMOS must
be reduced to zero through threshold adjustment implants.
It performs very fast operation as compare to CMOS. The
advantages of CPL logic are good output driving capability
due to outputinverters, fast differential stage due to cross
coupled PMOS structure and small input loads. The main
disadvantage of CPL logic is largenumber ofnodes and
high overhead due to dual rail signal. Schematic design of
CPL MUX is shown in fig. 5 In the energy economized
pass-transistor logic (EEPL), the sources of the PMOS
pull-up transistors of a CPL gate are connected to the
complementary output signal instead of Fig. 5 The main
advantage is smaller delay and smaller power dissipation
as compare to CPL. Becauseof regenerative positive
feedback which provides shorter delay than CPL logic. It
has same structure as CPL MUX employing two PMOS
and four NMOS instead of a positive feedback [12-13]. It
is shown in Fig. 6.
Fig.3 Schematic design of DCVSL 2:1 Multiplexer [31].
Fig. 4 Schematic design of MDCVSL 2:1 Multiplexer [31].
Fig. 5 Schematic design of CPL 2:1 Multiplexer [20].
Fig.6 Schematic design of EEPL 2:1 Multiplexer [20]
PROPOSED WORK
This design 2:1 MUX is based upon a pair of cross coupled
inverters. In this latch is made from two PMOS and two
NMOS that avoids the degradation of the logic level at the
output node. These NMOS devices areconnected between
output and ground. A sinusoidal supply is applied. This
logic familyalso generates both positive and negative
outputs. The functional blocks are in parallel with the
PMOSFETs of the adiabatic amplifier and form a
transmission gate. The two n-trees realize the logic
functions. This logic family also generates both positive

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and negative outputs. It is known as positive feedback
adiabatic logic [14-15]. An adiabatic 2:1 multiplexer based
on PFAL is designed on DSCH 3.1. This circuit implements
the function BSSAF  shown in fig. When the select
(S) line is low, the output node follows thesignal A and
when the select (S) line is high, theoutput nodefollows the
signal B, respectively. Schematic is shown in fig. 7
Fig. 7 Adiabatic design of 2:1 multiplexer.
An adiabatic XOR gate based on positive feedback logic is
designed and simulated. Timing waveforms and its
schematic is shown in fig. 8. The minimum sized XORgate
is implemented at 0.12µm technology. In the given circuit
complementary output is obtained.
Fig 8 Design of a XOR gate using positive feedback adiabatic logic.
LAYOUT & SIMULATION
Physical layout of a positive feedback adiabatic
multiplexer is designed using Microwind 3.1 and
simulation is performed using BSIM4 model. Schematic of
an inverter is designed using DSCH 3.1 tool. Layout of the
circuit is achieved after compiling the verilog file, in the
Microwind. A verilog file is a kind of netlist consisting all
thecomponents and connections used in designing of a
circuit [16-17]. Layout of inverter is shown in fig. 9
Fig.10 Layout simulation of 2:1 adiabatic multiplexer
Layout simulation of X-OR/X-NOR circuit is shown in fig.
11The waveforms verify the correct logic of the circuit.
Range of the voltage used for analog signal is 0-1.2V.
Fig. 11 Layout simulation of 2 input X-OR/X-NOR gate.
RESULT & COMPARISON
In this paper circuits based on various logic styles are
compared with the adiabatic circuits. These logic styles
include CMOS & complementary CMOS family that is
DCVSL, MDCVSL, CPL, EEPL. Adiabatic circuits are
designed using DSCH and simulation is performed on
Microwind 3.1 tool with 120nm technology.Table 1 shows
maximum darin current and energy for different logic style
multiplexers. It has been observed from the table that
proposed multiplexer is very energy efficient as compare to
other multiplexers. Also darin current is minimum for
proposed multiplexer which indicates low power
consumption.
Table.1Comparison table of drain current & energy for different
muliplexer,
Different Logic
Multiplexers
Max Drain
Current (mA)
Energy (fJ)
MDCVSL 0.672 179.3
DCVSL 0.604 98.2
CPL 0.511 11.74
EEPL 0.489 9.4
CMOS 0.462 5.9
PROPOSED 0.161 3.6
Analog simulation is performed on the layout of
multiplexer design. Fig. 10 shows time domain simulation
of Multiplexer. Logic ‘0’ corresponds to a zero voltage and
logic ‘1’ corresponds to 1.2V. A sinusoidal signal is
applied as power clock supply with amplitude 0.8V.
Simple clocks are applied as inputs and select lines
Fig. 9 Layout Representation of 2:1 adiabatic multiplexer.
Drain current is a stong function of power consumption,
means power dissipation largely depends upon darin
current. Fig. 12 shows variation of drain current with
supply volage at 270
C temperature. PFAL is more power
efficient than DCVSL multiplexer.

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107 NITTTR, Chandigarh EDIT-2015
CONLUSION
Multiplexer through various logic style has been designed
and simulated using DSCH & Microwind 3.1. These logic
styles includes DVCSL, MDCVSL, CPL and EEPL
multiplexer design. It is observed that proposed
Multiplexer shows better performance in terms of power
consumption. It is recorded that 49.56% and 68.32%
improvement is obtained in terms power consumption as
compare toCMOS It has been observed that proposed
multiplexer saves 38.9% energy as compare to CMOS
multiplexer. All results are verified at different supply
voltage and temperature. Proposed Multiplexer shows
good performance with supply voltage vs temperature &
supply voltage vs drain current variations as compare to
EEPL, CPL, DCVSL, MDCVSL multiplexer.energy as
compare to CMOS multiplexer. All results are verified at
different supply voltage and temperature. Proposed
Multiplexer shows good performance with supply voltage
vs temperature &supply voltage vs drain current variations
as compare to EEPL, CPL, DCVSL, MDCVSL
multiplexer
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