At very high frequencies, every trace and pin is an RF emitter and receiver. If careful design practices are not followed, the unwanted signals can easily mask those a designer is trying to handle. The design choices begin at the architecture level and extend down to submillimeter placement of traces. There are tried and proven techniques for managing this process. The practical issues of real system design are covered in this session, along with ways to minimize signal degradation in the RF environment.
High Speed & RF Design and Layout: RFI/EMI Considerations (Design Conference ...Analog Devices, Inc.
At very high frequencies, every trace and pin is an RF emitter and receiver. If careful design practices are not followed, the unwanted signals can easily mask those a designer is trying to handle. The design choices begin at the architecture level and extend down to submillimeter placement of traces. There are tried and proven techniques for managing this process. The practical issues of real system design is covered in this session, along with ways to minimize signal degradation in the RF environment.
High Speed & RF Design and Layout: RFI/EMI Considerations (Design Conference ...Analog Devices, Inc.
At very high frequencies, every trace and pin is an RF emitter and receiver. If careful design practices are not followed, the unwanted signals can easily mask those a designer is trying to handle. The design choices begin at the architecture level and extend down to submillimeter placement of traces. There are tried and proven techniques for managing this process. The practical issues of real system design is covered in this session, along with ways to minimize signal degradation in the RF environment.
Focusing on the physical layer of the 5G network, new methodologies, new problems facing the network and solutions for each problem.
topics are:-
Channel Models, Channel Coding, Multiple Access, Smart Antenna, Massive MIMO & Beamforming, Network Architecture, Frame structure & Numerology
addition: exploring the new trends that might be done in the future
Orthogonal Frequency Division Multiplexing, OFDM uses a large number of narrow sub-carriers for multi-carrier transmission to overcome the effect of multi path fading problem. LTE uses OFDM for the downlink, from base station to terminal to transmit the data over many narrow band careers of 180 KHz each instead of spreading one signal over the complete 5MHz career bandwidth. OFDM meets the LTE requirement for spectrum flexibility and enables cost-efficient solutions for very wide carriers with high peak rates.
The primary advantage of OFDM over single-carrier schemes is its ability to cope with severe channel conditions. Channel equalization is simplified. The low symbol rate makes the use of a guard interval between symbols affordable, making it possible to eliminate inter symbol interference (ISI).
Hello everyone. This is a short presentation on path loss and shadowing. I have not covered all the topics but a brief idea is given on path loss and wireless channel propagation models.
Hope you find it useful.
Thanks
The attached narrated power point presentation attempts to explain the methods of computation of total power loss and system rise time in a fiber optic link. The material will be useful for KTU final year B Tech students who prepare for the subject EC 405, Optical Communications.
SiC & GaN - Technology & market knowledge updatePntPower.com
Wide Band Gap semiconductor are more and more used in power electronics. Silicon Carbide and Gallium Nitride are now involved in the race to replace silicon. With huge R&D investments and start-ups facing historical players, market and technology knowledge becomes key. Point The Gap presented a SiC & GaN market knowledge update. All the information needed to understand this market, gathered in a few slides by a power electronics market intelligence specialist. Also available on www.PointThePower.com.
Including company names like Transphorm, Infineon, EPC corp., Cambridge electronics, Rohm, Cree, Toyota, Finsix, Zolt, Avogy, etc...
This session combines the high speed analog signal chain from RF to baseband with FPGA-based digital signal processing for wireless communications. Topics include the high speed analog signal chain, direct conversion radio architecture, the high speed data converter interface, and FPGA-based digital signal processing for software-defined radio. The demo board uses the latest generation of Analog Devices’ high speed data converters, RF, and clocking devices, along with the Xilinx Zynq-7000 SoC. Other topics of discussion include the imperfections introduced by the modulator/demodulator with particular focus on the effect of temperature and frequency changes. In-factory and in-field algorithms that reduce the effect of these imperfections, with particular emphasis on the efficacy of in-factory set-and-forget algorithms, are examined.
Focusing on the physical layer of the 5G network, new methodologies, new problems facing the network and solutions for each problem.
topics are:-
Channel Models, Channel Coding, Multiple Access, Smart Antenna, Massive MIMO & Beamforming, Network Architecture, Frame structure & Numerology
addition: exploring the new trends that might be done in the future
Orthogonal Frequency Division Multiplexing, OFDM uses a large number of narrow sub-carriers for multi-carrier transmission to overcome the effect of multi path fading problem. LTE uses OFDM for the downlink, from base station to terminal to transmit the data over many narrow band careers of 180 KHz each instead of spreading one signal over the complete 5MHz career bandwidth. OFDM meets the LTE requirement for spectrum flexibility and enables cost-efficient solutions for very wide carriers with high peak rates.
The primary advantage of OFDM over single-carrier schemes is its ability to cope with severe channel conditions. Channel equalization is simplified. The low symbol rate makes the use of a guard interval between symbols affordable, making it possible to eliminate inter symbol interference (ISI).
Hello everyone. This is a short presentation on path loss and shadowing. I have not covered all the topics but a brief idea is given on path loss and wireless channel propagation models.
Hope you find it useful.
Thanks
The attached narrated power point presentation attempts to explain the methods of computation of total power loss and system rise time in a fiber optic link. The material will be useful for KTU final year B Tech students who prepare for the subject EC 405, Optical Communications.
SiC & GaN - Technology & market knowledge updatePntPower.com
Wide Band Gap semiconductor are more and more used in power electronics. Silicon Carbide and Gallium Nitride are now involved in the race to replace silicon. With huge R&D investments and start-ups facing historical players, market and technology knowledge becomes key. Point The Gap presented a SiC & GaN market knowledge update. All the information needed to understand this market, gathered in a few slides by a power electronics market intelligence specialist. Also available on www.PointThePower.com.
Including company names like Transphorm, Infineon, EPC corp., Cambridge electronics, Rohm, Cree, Toyota, Finsix, Zolt, Avogy, etc...
This session combines the high speed analog signal chain from RF to baseband with FPGA-based digital signal processing for wireless communications. Topics include the high speed analog signal chain, direct conversion radio architecture, the high speed data converter interface, and FPGA-based digital signal processing for software-defined radio. The demo board uses the latest generation of Analog Devices’ high speed data converters, RF, and clocking devices, along with the Xilinx Zynq-7000 SoC. Other topics of discussion include the imperfections introduced by the modulator/demodulator with particular focus on the effect of temperature and frequency changes. In-factory and in-field algorithms that reduce the effect of these imperfections, with particular emphasis on the efficacy of in-factory set-and-forget algorithms, are examined.
This session combines the high speed analog signal chain from RF to baseband with FPGA-based digital signal processing for wireless communications. Topics include the high speed analog signal chain, direct conversion radio architecture, the high speed data converter interface, and FPGA-based digital signal processing for software-defined radio. Demonstrations use the latest generation Analog Devices’ high speed data converters, RF, and clocking devices, along with the Xilinx Zynq-7000 SoC. Other topics of discussion include the imperfections introduced by the modulator/ demodulator with particular focus on the effect of temperature and frequency changes. In-factory and in-field algorithms that reduce the effect of these imperfections, with particular emphasis on the efficacy of in-factory set-and-forget algorithms, are examined.
This article talks about the available IoT embedded antenna options and influencing factors analysis. How to choose an embedded antenna for IoT applications?
IoT projects rely on wireless connectivity, and the signal of the wireless connection depends on the chip itself as well as the antenna.
Wi-Fi is the preferred choice for portable devices or IP cameras, while industrial applications (such as remote monitoring, smart meters, smart buildings, smart cities, manufacturing automation, smart agriculture, and tracking) are more likely to use LPWAN networks such as NB-IoT, LoRa, SigFox, ISM or cellular networks. Each of these types of networks has a wide variety of embedded antennas.
This article will discuss the embedded antenna options available and some of the factors that influence selection.
Six Hidden Costs in a 99 Cent Wireless SoC Considerations when choosing betwe...Pallavi Das
Silicon Labs is the vendor of choice for OEMs developing ZigBee® networking into their products. The Silicon Labs ZigBee platform is the most integrated, complete and feature rich ZigBee solution available — a family of Wireless SoCs, based on ARM® Cortex® processor and 2.4 GHz transceiver, together the most reliable, scalable and advanced ZigBee software and supported by best-in-class development tools.
This training module introduces the packing improvement for high speed amplifiers and summary the performance & design considerations of high speed amplifiers
PCB Fabrication, China PCB Circuit Board Manufacturing from ChinaLeah-Hitech PCB
As a leading China PCB manufacturer, Hitech Circuits has rich experience and extensive expertise.from PCB layout & design, and PCB manufacturing to PCB testing and after-sales, all processesare finished in our ISO-certified factory. We put quality as the first priority, each circuit board goesthrough a strict quality control process before delivery, We specialize in producing all kinds ofprinted circuit boards, including PCB prototypes, FR4 PCB, Double-sided PCB, Aluminum PCB,RF PCB, Ceramic PCB, High-Frequency PCB, HDI PCB, etc. If you are looking for a reliablePCB board manufacturer in China, please don't hesitate to contact us.
As a leading one-stop electronics manufacturing services provider in China, Hitech Circuits Co., Limited (sales12@hitechpcb.com)offers high quality, cost effective and quick turn PCB board products, Printed Circuit board, PCB assembly, electronics assembly manufacturing, Electronic parts components sourcing services for your new products development.
With mature supply chain, talented design team, advanced manufacturing techniques and quality control systems, Hitech Circuits Co., Limited is able to provide one-stop electronics manufacturing services and solution for our customers to help them stand out in the marketplace.
This is an overview of the Analog Devices’ JESD204 Interface Framework, a system-level software package targeted at simplifying development by providing a performance optimized IP framework.
An Introduction to ADI’s Power components used in RF signal chains, with special treatment of high performance data converters, transceivers and PLL/VCOs.
An Introduction to ADI’s RF Switches and RF Attenuators including their key characteristics and how and where they should be used in the RF signal chain.
Digital isolation plays a key role in designing industrial motor control systems. This presentation takes you through why, where and how for isolation designs that optimize system performance while meeting the ever stringent safety and efficient standards. Analog Devices, Nicola O'Byrne at PCIM 2015
Isolation in gate drive is one critical area for designing efficient, safe and highly productive motor control systems. Learn how the latest ADI isolated gate drives can help you solve the design challenges. Analog Devices, Dara O'Sullivan PCIM 2015
When it comes to high performance signal chains, you need high performance power solutions. Noise sensitive
circuits such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), amplifiers, and phase
lock loops (PLLs)—as well as FPGAs—demand low noise power supplies that require specialized design
techniques. Engineers spend hours trying to figure out how to power these circuits without adding noise.
This presentation will focus on understanding various methods for not only approaching but meeting system
requirements. The session will introduce tested solutions and layout considerations that must be taken into
account when designing with switching regulators and low drop out (LDO) regulators.
This session provides insight into the operation of electric motor drive systems. Topics include electric motor operation and construction, motor control strategies, feedback sensors and circuits, power and isolation, and challenges of designing highly efficient motor control systems. A new high performance servo control FMC board will be introduced in the presentation, which provides an efficient motor control solution for different types of electric motors, addresses power and isolation challenges, and provides accurate measurement of motor feedback signals and increased control flexibility due to FPGA interfacing capabilities. The motor control hardware platform will be used to demonstrate rapid prototyping of motor control algorithms using Xilinx base platforms and the MathWorks development and simulation tools.
Finding the right combination of parts to create a signal chain can be a complex and daunting task, due to time demands, unfamiliarity with various technology areas, and the enormous amount of unproven solutions scattered across the Web. Signal Chain Designer is an intelligent selection and design tool that accesses verified product combinations and applications circuits, which can be customized or newly created according to user specifications. The Signal Chain Designer experience is supported by direct access to online EE design tools, evaluation hardware, software, documentation, and ADI Circuits from the Lab® reference circuits.
Sensors are the eyes, ears, and hands of electronic systems and allow them to capture the state of the environment. The capture and processing of sensor inputs is a delicate process that requires understanding of the signal details. Integration of sensor functions onto silicon has brought about improved performance, better signal handling, and lower total system cost. MEMS (microelectromechanical systems) sensors have opened up entire new areas and applications. In this session, the fundamental MEMS sensor concept of moving fingers that form a variable capacitor is covered, along with how it is turned into a usable motion signal. Adaptations for multiaccess sensing, rotational sensing, and even sound sensing, along with concepts of how these devices are tested and calibrated, are covered.
The industrial control market involves the monitoring and control aspects of both complex and simple processes. Common trends within the industry, notably the drive for increased efficiencies, better robustness, higher channel densities, and faster monitoring and control speeds, subsequently drive new technology advancements for semiconductor manufacturers. This session aims to give a broad overview of the system requirements for both field instruments (sensors/actuators) and control room (analog input/output) modules, and demonstrates a typical I/O module configuration with HART® (highway addressable remote transducer) connectivity.
Instrumentation: Test and Measurement Methods and Solutions - VE2013Analog Devices, Inc.
Tilt Measurement: Tilt measurement is fast becoming a fundamental analysis tool in many fields including automotive, industrial, and healthcare. Navigation, vehicle dynamic control, building sway indication, and motion detection systems all rely on this simple, cheap, and precise way of angle monitoring. MEMS accelerometers are better suited to inclination measurement than other methodologies. This session will address the challenges encountered when designing a dual-axis tilt sensor using a MEMS accelerometer including measurement resolution, signal conditioning, single- vs. dual-axis, angle computation, and calibration.
Impedance Measurement: The measurement of complex impedance is widely used across industrial, commercial, automotive, healthcare, and consumer markets, and can include applications such as proximity sensing, inductive transducers, metallurgy and corrosion detection, loudspeaker impedance, biomedical, virus detection, blood coagulation factor, and network impedance analysis. This session will cover the concepts, approaches, and challenges of performing complex impedance measurements and will present a system-level solution for impedance conversion.
Weigh Scale Measurement: Most common industrial weigh scale applications use a bridge-type load-cell sensor, with a voltage output that is directly proportional to the load weight placed on it. This session examines the basic parameters of a bridge-type load-cell sensor, such as the number of varying elements, impedance, excitation, sensitivity (mV/V), errors, and drift. It will also discuss the various components of the signal conditioning chain and present solutions with high dynamic range.
Liquid Sensing: Visible light absorption spectroscopy and colorimetry are two fundamental tools used in chemical analysis. Most of these light-based systems use photodiodes as the light sensor, and require similar high input impedance signal chains. This session examines the different components of a photodiode amplifier signal chain, including a programmable gain transimpedance amplifier, a hardware lock-in amplifier, and a Σ-Δ ADC that can measure a sample and reference channel to greatly reduce any measurement error due to variations in intensity of the light source.
Gas Sensing: Many industrial processes involve toxic compounds, and it is important to know when dangerous concentrations exist. Electrochemical sensors offer several advantages for instruments that detect or measure the concentration of toxic gases. This session will describe a portable toxic gas detector using an electrochemical sensor. The system presented here includes a potentiostat circuit to drive the sensor, as well as a transimpedance amplifier to take the very small output current from the sensor and translate it to a voltage that can take advantage of the full-scale input of an ADC.
In wireless communications and data acquisition systems, there is more to consider when designing and implementing a complete solution beyond simply physically connecting a high speed analog module to an FPGA platform. Available hardware description language (HDL) components and software are critical to establishing an interface, which is necessary for practical system integration. This session starts with a top-level overview of various physical interfaces that are typically used and provides an in-depth focus on high speed serial JESD204B. Prototype HDL used for these types of boards is covered, along with the specific board components and how they are used to interface to high speed ADCs and DACs. Linux device drivers for the HDL components, as well as for the ADI components, are presented. This includes a short introduction into the Industrial I/O (IIO) framework, the benefits it offers, and how it can be used in end designs.
DevOps and Testing slides at DASA ConnectKari Kakkonen
My and Rik Marselis slides at 30.5.2024 DASA Connect conference. We discuss about what is testing, then what is agile testing and finally what is Testing in DevOps. Finally we had lovely workshop with the participants trying to find out different ways to think about quality and testing in different parts of the DevOps infinity loop.
Let's dive deeper into the world of ODC! Ricardo Alves (OutSystems) will join us to tell all about the new Data Fabric. After that, Sezen de Bruijn (OutSystems) will get into the details on how to best design a sturdy architecture within ODC.
JMeter webinar - integration with InfluxDB and GrafanaRTTS
Watch this recorded webinar about real-time monitoring of application performance. See how to integrate Apache JMeter, the open-source leader in performance testing, with InfluxDB, the open-source time-series database, and Grafana, the open-source analytics and visualization application.
In this webinar, we will review the benefits of leveraging InfluxDB and Grafana when executing load tests and demonstrate how these tools are used to visualize performance metrics.
Length: 30 minutes
Session Overview
-------------------------------------------
During this webinar, we will cover the following topics while demonstrating the integrations of JMeter, InfluxDB and Grafana:
- What out-of-the-box solutions are available for real-time monitoring JMeter tests?
- What are the benefits of integrating InfluxDB and Grafana into the load testing stack?
- Which features are provided by Grafana?
- Demonstration of InfluxDB and Grafana using a practice web application
To view the webinar recording, go to:
https://www.rttsweb.com/jmeter-integration-webinar
Essentials of Automations: Optimizing FME Workflows with ParametersSafe Software
Are you looking to streamline your workflows and boost your projects’ efficiency? Do you find yourself searching for ways to add flexibility and control over your FME workflows? If so, you’re in the right place.
Join us for an insightful dive into the world of FME parameters, a critical element in optimizing workflow efficiency. This webinar marks the beginning of our three-part “Essentials of Automation” series. This first webinar is designed to equip you with the knowledge and skills to utilize parameters effectively: enhancing the flexibility, maintainability, and user control of your FME projects.
Here’s what you’ll gain:
- Essentials of FME Parameters: Understand the pivotal role of parameters, including Reader/Writer, Transformer, User, and FME Flow categories. Discover how they are the key to unlocking automation and optimization within your workflows.
- Practical Applications in FME Form: Delve into key user parameter types including choice, connections, and file URLs. Allow users to control how a workflow runs, making your workflows more reusable. Learn to import values and deliver the best user experience for your workflows while enhancing accuracy.
- Optimization Strategies in FME Flow: Explore the creation and strategic deployment of parameters in FME Flow, including the use of deployment and geometry parameters, to maximize workflow efficiency.
- Pro Tips for Success: Gain insights on parameterizing connections and leveraging new features like Conditional Visibility for clarity and simplicity.
We’ll wrap up with a glimpse into future webinars, followed by a Q&A session to address your specific questions surrounding this topic.
Don’t miss this opportunity to elevate your FME expertise and drive your projects to new heights of efficiency.
Epistemic Interaction - tuning interfaces to provide information for AI supportAlan Dix
Paper presented at SYNERGY workshop at AVI 2024, Genoa, Italy. 3rd June 2024
https://alandix.com/academic/papers/synergy2024-epistemic/
As machine learning integrates deeper into human-computer interactions, the concept of epistemic interaction emerges, aiming to refine these interactions to enhance system adaptability. This approach encourages minor, intentional adjustments in user behaviour to enrich the data available for system learning. This paper introduces epistemic interaction within the context of human-system communication, illustrating how deliberate interaction design can improve system understanding and adaptation. Through concrete examples, we demonstrate the potential of epistemic interaction to significantly advance human-computer interaction by leveraging intuitive human communication strategies to inform system design and functionality, offering a novel pathway for enriching user-system engagements.
"Impact of front-end architecture on development cost", Viktor TurskyiFwdays
I have heard many times that architecture is not important for the front-end. Also, many times I have seen how developers implement features on the front-end just following the standard rules for a framework and think that this is enough to successfully launch the project, and then the project fails. How to prevent this and what approach to choose? I have launched dozens of complex projects and during the talk we will analyze which approaches have worked for me and which have not.
The Art of the Pitch: WordPress Relationships and SalesLaura Byrne
Clients don’t know what they don’t know. What web solutions are right for them? How does WordPress come into the picture? How do you make sure you understand scope and timeline? What do you do if sometime changes?
All these questions and more will be explored as we talk about matching clients’ needs with what your agency offers without pulling teeth or pulling your hair out. Practical tips, and strategies for successful relationship building that leads to closing the deal.
The Art of the Pitch: WordPress Relationships and Sales
High Speed and RF Design Considerations - VE2013
1. Analog Design Conference 2013
High Speed/RF Design and Layout
RFI/EMI Considerations
Zoltan Frasch
2. Legal Disclaimer
Notice of proprietary information, Disclaimers and Exclusions Of Warranties
The ADI Presentation is the property of ADI. All copyright, trademark, and other intellectual property and
proprietary rights in the ADI Presentation and in the software, text, graphics, design elements, audio and all other
materials originated or used by ADI herein (the "ADI Information") are reserved to ADI and its licensors. The ADI
Information may not be reproduced, published, adapted, modified, displayed, distributed or sold in any manner, in
any form or media, without the prior written permission of ADI.
THE ADI INFORMATION AND THE ADI PRESENTATION ARE PROVIDED "AS IS". WHILE ADI INTENDS THE ADI
INFORMATION AND THE ADI PRESENTATION TO BE ACCURATE, NO WARRANTIES OF ANY KIND ARE MADE
WITH RESPECT TO THE ADI PRESENTATION AND THE ADI INFORMATION, INCLUDING WITHOUT LIMITATION
ANY WARRANTIES OF ACCURACY OR COMPLETENESS. TYPOGRAPHICAL ERRORS AND OTHER
INACCURACIES OR MISTAKES ARE POSSIBLE. ADI DOES NOT WARRANT THAT THE ADI INFORMATION AND
THE ADI PRESENTATION WILL MEET YOUR REQUIREMENTS, WILL BE ACCURATE, OR WILL BE
UNINTERRUPTED OR ERROR FREE. ADI EXPRESSLY EXCLUDES AND DISCLAIMS ALL EXPRESS AND IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT OF
ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. ADI SHALL NOT BE RESPONSIBLE FOR ANY DAMAGE
OR LOSS OF ANY KIND ARISING OUT OF OR RELATED TO YOUR USE OF THE ADI INFORMATION AND THE ADI
PRESENTATION, INCLUDING WITHOUT LIMITATION DATA LOSS OR CORRUPTION, COMPUTER VIRUSES,
ERRORS, OMISSIONS, INTERRUPTIONS, DEFECTS OR OTHER FAILURES, REGARDLESS OF WHETHER SUCH
LIABILITY IS BASED IN TORT, CONTRACT OR OTHERWISE. USE OF ANY THIRD-PARTY SOFTWARE
REFERENCED WILL BE GOVERNED BY THE APPLICABLE LICENSE AGREEMENT, IF ANY, WITH SUCH THIRD
PARTY.
2
4. 4
Overview
What is high speed?
The frequency above which a PCB can significantly degrade circuit
performance. 50MHz and above can be considered high speed.
Why High Speed PCB?
1 f 10 f 100 f1 f
?To get this waveform Need this bandwidth
5. 5
Overview
PCB layout is one of the final steps in the design process and often
not given the attention it deserves. High Speed circuit performance
is heavily dependent on board layout.
Today we will address
Practical layout guidelines to:
Improve the layout process
Help ensure expected circuit performance
Reduce design time
Lower design cost
7. 7
Schematics
A good layout starts with good Schematics!
Two Basic Functions of Schematic
Represent actual circuit connections
Generate NetList for layout.
Can it be made more effective?
Can it represent functionality more clearly?
Others can understand circuit
Can it show signal path?
Aid layout
Aid troubleshooting, debug
Represent functionality
Can it be made more attractive?
Can increase perceived value
More effective schematics decrease time to market
10. PCB Fundamentals
Top Copper
Usually a signal layer.
Normally a 1.4 mils (0.04 mm) thick (1 oz) copper
plate. Can be thicker.
Laminate
Woven glass epoxy.
Thickness adjustable from 0.05 mm (1.9 mils) to
suit requirements.
Relative permittivity (dielectric constant) between
2.2 and 4.7. Value depends on material and
construction.
Plane copper
Contiguous copper sheet .
Normally 0.7 mils (0.02 mm) thick (1/2 oz). Can
be thicker.
Etched to form signal traces, landing pads, vias.
Minimum trace width is 4 mils (0.1 mm).
Minimum space requirement between two objects
is 4 mils (0.1 mm).
Each trace, pad, via forms a transmission line
with a characteristic impedance Zo.
Zo depends on construction, width, height,
distance from plane copper.
A copper shape (trace, pad, via)
terminated with its characteristic
impedance:
Forms a terminated transmission line.
Signal integrity is not degraded.
Unterminated copper shapes:
Form unterminated transmission lines
Have capacitance and/or inductance
Degrade signal integrity
Controlled impedance PCB:
Manufactured to a specified Zo, applicable to one
specific trace width only.
To optimize PCB signal integrity:
Keep all long traces the same width.
Terminate all long traces at the load end with a
resistor R=Zo.
Can double terminate with additional series
resistor at the source end but not necessary.
Double termination reduces drive current requirement
from source at the expense of increased output source
voltage requirement.
Keep all unterminated traces as short as possible.
Design pads as small as possible.
The basic high speed PCB consists of 3 layers:
11. PCB Fundamentals - PCB Material selection examples
15
Isola – FR4 types
Common general purpose material.
High temperature versions for leadfree solder exist
Higher permittivity 4.7-4.2. Generates manageable parasitic capacitances
Low Cost
Reasonable controlled impedance trace consistency.
Specified to 1 GHz
Rogers – PTFE types
High frequency, high temperature material
Low permittivity. 2.2 and up. Can reduce parasitic capacitances
Expensive
Good impedance consistency.
Specified to 10 GHz
Numerous other manufacturers. Some with performance
specifications similar to above.
12. PCB Fundamentals - Component Landing pad design
16
Landing pad size
Traditionally oversized by ≈ 30% from
component pad.
Can fit soldering iron on it
Can allow visual inspection of solder joint
Can accommodate component with larger
placement errors.
Increases parasitic capacitance – lowers
effective useful frequency
Increases chances for solder bridging
Requires more board space
Minimum oversizing: 0-5% from
component pad.
Retains mechanical strength
Contact area between component and PCB
remains the same
Reduces parasitic capacitance – retains
higher useful frequency
Reduces required board space
Pad shape
Traditionally rectangular with sharp corners
Rounded corners allow tighter pad-to-trace
spacing. Reduces board size.
This or This
ThisOr This
13. PCB Fundamentals - Via Placement
17
*Courtesy of Lee Ritchey
Conventional
Connecting
trace
minimized
Via just inside
pad
Via Centered
in pad
Less Inductance
Less capacitance
Smaller board space
Increased probability of solder wicking
Fix wicking with tented vias
15. 19
Component Placement and Signal Routing
Just as in real estate location is everything!
Input/output and power connections on a board
are typically defined
Component placement and Signal routing
require deliberate thought and planning
16. Component Placement and Signal Routing
Use of Plane Layers
Plane LayerPrepregCopper Signal TraceSolder MaskSignal Current
Return Current
follows the path of
least inductance
17. Component Placement and Signal Routing
Plane layer cutouts
Plane LayerPrepregCopper Signal TraceSolder MaskSignal Current
Return Current
Not so good.
Minimize Voids in
plane layers
18. Component Placement and Signal Routing
Signal Routing
Placement not optimized – Minimize crossings
Connector
Digital ADC
RF
Power
Conditioning
Analog
Temp
Sensor
Connector
ADC
Driver
Placement optimized – Idealized
19. Component Placement and Signal Routing
Return Path Routing
Clock
Circuitry
Analog
Circuitry
Resistor
Digital
Circuitry
Sensitive Analog
Circuitry Disrupted by
Digital Supply Noise
Not so good
ID
Voltage Drop
A better way
Sensitive Analog
Circuitry Safe from
Digital Supply Noise
Use GND and PWR planes to
reduce return path R and L.
Use separate AGND and DGND
planes to minimize digital
coupling into AGND plane.
Compartmentalize functions
Group components associated
with functions.
Place functions to coincide with
signal path.
Route functions first with input
and output along signal path.
Route connections between
functions next.
Voltage Drop
More Voltage
Drop
ANALOG
CIRCUITS
DIGITAL
CIRCUITSVD VA
+ +
ID
IA
IA + ID
VIN
GND
REF
20. Component Placement and Signal Routing
Packaging and Pinout choices
Packaging plays a large role in high-speed applications
Smaller packages
Improved high frequency response
Compact layout
Lower package parasitics
Low Distortion Pinout (dedicated feedback)
Compact layout
Streamline signal flow
Lower distortion
1
2
3
4
8
7
6
5
FB
INP
INN
VOUT
+
-
Low Distortion
1
2
3
4
8
7
6
5
VOUT
+
-
Standard
INP
INN
21. 25
Component Placement and Signal Routing
CSP and SOIC Package Distortion
HARMONICDISTORTION(dBc)
0.1
–120
–100
–110
–80
–90
–60
–70
–50
1 10 50
04511-0-085
SOLID LINES – SECOND HARMONICS
DOTTED LINES – THIRD HARMONICS
G = +5
VOUT = 2V p-p
VS = ±5V
RL = 100Ω
FREQUENCY (MHz)
SOIC
CSP
Improvement
10dB at 1MHz 14dB
at 10MHz
22. Example - Component Placement and Signal Routing
Two Inputs. Carbon copies to
ensure balance.
Gain and feedback. Carbon
copies to ensure symmetry.
Outputs. Carbon copies to
ensure symmetry.
Level shifting tapped into signal
path. Carbon copies to ensure
symmetry.
Auxiliary function.
Critical Signal path as short as
possible.
Critical signal paths are carbon
copies to maintain balance.
23. Example – PCB and component Placement
A perfectly good high frequency board
BUT:
Excessive number of unnecessary vias
Plane layer compromised with a large
cutout
Unnecessarily long signal traces
Landing pads are too large
No internal plane layers
Same circuit with added provisions for
an auxiliary function
A better alternative?
More components yet smaller board size
Vias are minimized
Several internal plane layers
“Properly” sized Landing pads
24. Example - Component Placement and Performance
RoHS Tg 170 6 layers
HR370 6 layers
RoHS Tg 170 6 layers
HR370 6 layers
Two resistors located as shownMove resistors closer to input pins
25. Example – PCB and Performance
• 6 layer PCB
• RoHS Tg 170 & HR370
• No bypass caps
• No GND plane on top
• No plane cut outs
• No “stitching” vias
• Smaller size
RoHS Tg 170 6 layers
HR370 6 layers
FR4 2 layers
RoHS Tg 170 6 layers
HR370 6 layers
FR4 2 layers
• 2 layer FR4 PCB
• 4 bypass caps
• Top GND plane segmented
• Plane cut outs
• “Stitching” vias
27. 31
Power Supply Bypassing
Bypassing is essential to high
speed circuit performance.
It provides low impedance
source and return paths to high
frequency changes in load
current.
Capacitors as close as possible
to the supply pins of each IC
provide localized bypassing.
Capacitors self-resonate.
Not all capacitors are equal.
28. 32
Power Supply Bypassing - Capacitor Model
ESR (Equivalent Series
Resistance)
Rs
Capacitance
XC = 1/2πfC
ESL (Equivalent Series
Inductance)
XL=2πfL
Effective Impedance
At Series resonance
XL=XC
Z = R
30. Multiple Parallel Capacitors
1 x 330µF T520, 1 x 1.0µF 0603, 2 x 0.1µF 0603, and 6 x 0.01µF 0603
*Courtesy of Lee Ritchey
*
2 x (1 x 330µF T520, 1 x 1.0µF 0603, 2 x 0.1µF 0603, and 6 x 0.01µF 0603)
1µF
330µF
0.1µF
0.01µF
31. Example - Bypass Capacitor Placement
C
C
Tantalum
Tantalum
C
C
Tantalum capacitors provide
low frequency bypassing for
the area
Chip capacitors provide
bypassing for higher
frequencies for the area.
Chip capacitors on the
supply pins provide
additional high frequency
bypassing for the IC.
32. Power Supply Bypassing Interplanar Capacitance
36
TOP SILK
TOP MASK
TOP COPPER
2 X 106 0.009”
50Ω with 16 mils TRACE WIDTH
INNER COPPER GND
0.37” SPACER
INNER COPPER VCC
1 X 1080 0.0032”
INNER COPPER GND
1 X 1080 0.0032”
INNER COPPER VEE
1 X 1080 0.0032”
BOTTOM COPPER GND
BOTTOM MASK
BOTTOM SILK
kA
11.3d
C=
0.062”
6 LAYER STACKUP
Can replace most or all
discrete bypass capacitors.
Uniformly distributed.
-160
-140
-120
-100
-80
-60
-40
-20
0
0.01 1 100 10000
BareBoardGain
f (MHz)
AD4896-2 bare board Input-to-Output gain
6-layers
2-layers
36. 40
Parasitics
PCB parasitcs take the
form of hidden
capacitors, inductors
and resistors in the PCB
Parasitics degrade and
distort performance
37. 41
113
kXY
C pF
Z
=
K = relative dielectric constant
X = Copper Length (mm)
Y = Copper Width (mm)
Z = Distance to nearest Plane (mm)
2
0 2 0 5 2235
X Y Z
L X nH
Y Z X
. . ln .
+
= + + +
Trace/Pad Parasitics
X Y
Z
Top Solder mask
Has effect on characteristic impedance
Top (Signal) layer
Has signal traces and component landing
pads.
Traces are transmission lines with
characteristic impedance
Controlled Impedance Plane Layer
Traces on the top signal layer, the spacer
between and this plane forms transmission
lines with a characteristic impedance.
Spacer
Large distance to eliminate interaction with
Controlled Impedance Layer above it.
PWR-GND combination
Two layers closely spaced layers form an
Interplanar capacitance.
Spacer eliminates interaction
between the signal layer with its
associated controlled impedance
layer and all other layers below the
controlled impedance layer.
Every unterminated trace and pad
has capacitance and inductance.
EXAMPLES
Choose FR4 PCB with 1 oz Cu on top
Need 50Ω controlled impedance for 10
mils and 0.2mm wide traces
K= 4.7, Z=0.16mm and 0.13mm
Example1: SOIC landing pad
X = 0.51 mm Y = 1.27mm
Z = 0.16mm: C = 0.17 pF; L=0.08 nH
Z = 0.13mm: C = 0.21 pF; L=0.08 nH
Example2: 3x3 mm CSP landing
pad
X = 0.6 mm Y = 0.3mm
Z = 0.16mm: C = 0.05 pF; L=0.05 nH
Z = 0.13mm: C = 0.05 pF; L=0.05 nH
Minimize capacitance
Reduce trace/pad area
Increase spacing to plane layer
Void plane under trace/pad
Minimize Inductance
Reduce trace/pad length
Increase trace/pad width
Remove Voids in plane layer under
trace/pad
Decrease spacing to plane layer
38. 42
Via Parasitics
𝐿 = 0.2𝐻 𝑙𝑙
4𝐻
𝑑
+ 1 𝑛𝑛
𝐶 =
0.055𝑘𝑘𝑑1
𝑑2 − 𝑑1
𝑝𝑝
𝑤𝑤𝑤𝑤𝑤 𝑘 = 𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑 𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐.
𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 𝑎𝑎𝑎 𝑖𝑖 𝑚𝑚.
Example: A “10 mil via” on FR4 PCB
d=0.254 mm, d1=0.55 mm, d2=1.1mm
K=4.7, H=1.62 mm
L=0.93 nH, C=0.48 pF
Vias are capacitive in signal traces,
inductive when connecting to planes.
Vias are usually invisible to signals
below 1 GHz.
Compare to a 10mm long 10 mils wide
trace: L=8.8 nH, C=0.66 pF
39. 43
Simplified Component Parasitic Models
C = Capacitance
RP = insulation resistance
RS = equivalent series resistance (ESR)
L = leads and plates series inductance
RDA = dielectric absorption
CDA = dielectric absorption
L
r
RP
C
RDA CDA
RS CP
R
L
R = Resistance
CP = Parallel capacitance
L= equivalent series inductance (ESL)
Chip Resistors:
Cp range from 0.25 – 1pF
45. Vias in signal path
No hard evidence to their measurable degrading effect (up to ≈ 2GHz).
Vias increase PCB real estate requirements.
Sharp corners, 90° bends in signal traces
No hard evidence to their measurable degrading effect (up to ≈ 2GHz).
Sharp corners and 90° turns can increase PCB real estate requirements.
50
Signal Routing
46. 51
Signal Routing
Use GND and PWR Planes
Connect pads to planes using “Via-in-pad” method to minimize parasitics
Use controlled impedance plane layer directly under or over a signal layer.
Place components of a functional block as close as possible
0.5 mm component-to-component spacing is sufficient for manual placement
Minimize vias in signal traces. The less the better.
Keep traces within a functional block on the same layer.
Use interplanar capacitance for bypassing
Keep plane layers as contiguous as possible
Avoid unnecessary vias perforating plane layers.
Avoid cutouts in plane layers
Keep traces as straight as possible
Minimize bends and turns
47. PCB Termination resistors
• Termination resistors as close to first
component in signal path as
possible.
• Long transmission line, minimized
unterminated trace length.
• Optimized.
• Termination resistors as close to
input connector as possible
• Short transmission line, long
unterminated trace length.
• Not optimized.
48. PCB Don’t-s
• Too many vias. Internal plane layer perforated. Looks
more of a mesh than a plane. Plane layer effectiveness is
diminished.
• Copper plating is cheap. No resistance to corrosion.
Landing pads are blemished after two months. PCB
longevity is compromised.
• IC landing pads are too long. Increased parasitic
capacitance.
• Silk screen text is not readable. Unnecessary expense in
its current form.
• Component orientation appears ad hoc. Difficult to follow
signal path during debug.
• Component designator placement not optimized. Difficult
to locate components during debug.
52. Examples – Bare board response
-160
-140
-120
-100
-80
-60
-40
-20
0
0.01 0.1 1 10 100 1000 10000
BareBoardGain
f (MHz)
AD4896-2 bare board Input-to-Output gain
6-layers
2-layers
53. 59
Summary
Begin by selecting a strategy and putting a plan in place
Have a power supply bypass strategy in place.
Decide how to manage parasitics before you begin
A good layout starts with a good schematic
High speed PCB design requires deliberate thought and attention to detail!
Use multiple Ground, Power and controlled impedance planes
Component location on the board is just as important as to where you put
entire circuits
Take the lead when laying out your board, don’t leave anything to chance
New packaging and pinouts allow for improved performance and more
compact layouts
There are many options for signal distribution. Choose the right one for the
application
55. Design Resources Covered in this Session
Design Tools & Resources:
Ask technical questions and exchange ideas online in our
EngineerZone™ Support Community
Choose a technology area from the homepage:
ez.analog.com
Access the Design Conference community here:
www.analog.com/DC13community
[Other resources if available]
61
Name Description URL
[Relevant tool]
[wiki site] Contains reference design materials, etc.
[other]
57. Visit the [name of demo] in the exhibition room
[Brief explanation of demo they
will find in the exhibit hall]
Image of demo/board
63
This demo board is available for purchase:
www.analog.com/DC13hardware
59. Crosstalk and Coupling
65
Capacitive Crosstalk or Coupling
This results from traces running on top of each other, which forms a
parasitic capacitor
Solutions run traces orthogonal, to minimize trace coupling and lower area
profile
Inductive Crosstalk
Inductive crosstalk exists due to the magnetic field interaction between long
traces parallel traces
There are two types of inductive crosstalk; forward and backward
Backward is the noise observed nearest the driver on the victim trace
Forward is the noise observed farthest from the driver on the driven line
Minimize crosstalk by
Increasing trace separation (improving isolation)
Using guard traces
Using differential signals
60. 66
Electromagnetic compatibility (EMC)
There are two aspects of EMC:
It describes the ability of electronic systems to operate without interfering with
other systems
It also describes the ability of such systems to operate as intended within a
specified electromagnetic environment
Primary specifications are IEC-60050 and IEC1000
Extensive reviews in tutorial MT-095 and Analog Dialog 30-4 on
Analog Devices website (www.analog.com)
Inability to meet these requirements will compromise your
equipment
Inability to meet these requirements will severely limit the ability to
sell the equipment to customers
61. 67
Blank form
With the short signal transition times
and high clock rates of modern digital
circuitry, PCB traces need to be
considered not as simple connections
but as transmission lines.
The receiving aerial possesses a natural, or characteristic,
impedance and electrical theory shows that for the aerial to
transfer maximum power to the set (and to ensure the integrity of
the electrical signal) the impedance both of the feeder and the
receiver should match that of the aerial. In other words the signal
should ideally be presented with a constant impedance as it
travels from its source to its destination. Where a mismatch
occurs only part of the signal will be transmitted; the rest will be
reflected toward the source (this degrades the signal). Cable
designers therefore take great care to ensure the accuracy and
consistency of the cable dimensions and material
characteristics. At high signal switching speeds, the electrical
properties of the cable, such as the capacitance and inductance,
must be taken into account, and cables can no longer be
considered as simple wires. Cables designed for high signal
speeds where these factors are taken into consideration are
referred to as transmission lines.
Similarly, as the speed of signal switching on a PCB increases,
the electrical properties of the traces carrying signals between
devices become increasingly more important. The impedance
of a PCB trace is controlled by
its configuration
dimensions (trace width and thickness and height of the board
material)
dielectric constant of the board material
As with a cable, when the signal encounters a change of
impedance arising from a change in material or geometry, part
of the signal will be reflected and part transmitted. These
reflections are likely to cause aberrations on the signal which
may degrade circuit performance (e.g. low gain, noise and
random errors). In practice board designers will specify
impedance values and tolerances for board traces and rely on
the PCB manufacturer to conform to the specification.