The document discusses DDR noise interference issues in cellular devices. It notes that DDR noise can desense channels near half the DDR clock frequency and that this noise can couple from the DDR chip to the baseband chip and then to RF components. It recommends using an LC filter near the baseband chip to mitigate this issue but notes the capacitor cannot be too large or it may degrade the sensitivity of wide bandwidth LTE signals by attenuating the I/Q signals.

1. 1

2. Issue
 As shown below, for DDR, the CLK frequency is half of
data frequency. So, desense is seen on channels
surrounding (533/ 2 * 7 = DCS 1800 ; 533/2 *8 =W/L-B1)
when DDR is running at 533 MHz[1-3].
 And channels surrounding (400/2 * 9, = DCS 1800 ;
400/2 * 10 = 2000 MHz, right above the high band of PCS
1900 and W/L-B2) when DDR is running at 400 MHz[1-2].
(533/2)*N (533/2)*(N+1)
(400/2)*N (400/2)*(N+1)
Channel
Level
2

3. Issue
 In some design, DDR chip is on baseband chip(POP-
Package on Package), DDR noise is coupled to
baseband chip, noise then transfers to baseband chip
RX I/Q pins and is carried to RF chip[1-2].
Transceiver
BaseBand
Chip
RX IQ
DDR Noise
3

4. Mitigation
 Locate a LC filter near baseband chip on RX I/Q
signal[1,2].
Transceiver
BaseBand
Chip
RX IQ
DDR Noise
 Nevertheless, the shunt capacitor should NOT be too
large.
4

5. Mitigation
 As show below, the wider the LTE signal bandwidth is,
the wider the baseband I/Q signal bandwidth will be.
 Take 150 pF shunt capacitor for example, chances are
that the sensitivity of 15/20 MHz bandwidth LTE signal
may degrade because I/Q signal is attenuated.
5

6. Reference
[1] MSM8x26/MSM8x28 + WTR2605 DDR Desense Issue, Qualcomm
[2] MSM8926/MSM8928 Chipset DDR Desense Issue, Qualcomm
[3] Analysis of GSM ORFS Issue, slideshare
6