AD-IP-JESD204 JESD204B Interface Framework

ROBIN GETZ
DEL JONES
ANALOG DEVICES
AD-IP-JESD204
JESD204B Interface Framework

AD-IP-JESD204
Agenda
► The agenda has the following points:
 Review of JESD204 concepts, high level
requirements
 Going through each of the JESD204 layer and
matching it with the JESD204 IPs
 Going through software drivers for the framework
► Physical layer description
► Data link layer description
► Transport layer description
► Example Design
 Hardware design issues taken into consideration
 Pinout issues
 HDL parameters selection
 Sharing of transceiver
► Software
 Linux drivers
 Linux device-tree
 Linux kernel
 No-Os
► License
► Summary

4
Why the Need for a High Speed
Converter-to-FPGA Serial Interface?
► Today’s solution ► Solution with JESD204A/JESD204B serial
interface
FPGA
34 WIRES
18 WIRES
Tight timing
requirements
Large number of I/Os
TO
ANTENNA 1
34 WIRES
18 WIRES
TO
ANTENNA 2
FPGA
TO
ANTENNA 1
TO
ANTENNA 2
Relaxed
timing requirements
with sync control
Minimum number of I/Os
8
SERIAL PAIRS
1 to 2
SERIAL PAIRS
1 to 2
SERIAL PAIRS
14B ADC
250 MSPS
DUAL 16B DACDUAL
16B DAC
1.2 GSPS
14B ADC
250 MSPS
DUAL 16B DACDUAL
16B DAC
1.2 GSPS
14B ADC
250 MSPS
14B ADC
250 MSPS
QUAD
16B DAC
2 GSPS
Simplification of overall system design
Smaller/lower number of trace routes, easier to
route board designs
Easier synchronization
Reduction in pin count – both the Tx and Rx side
Move from high pin count low speed parallel
interfaces
to low pin count high speed serial interfaces
Embedded clock incorporated to even further
reduce pin count
Reduction in system costs
Smaller IC packages and board designs lead to
lower cost
Easily scalable to meet future bandwidth requirements
As geometries shrink and speed increases, the
standard adapts

Key Aspects of JESD204x Standards
► 8b/10b Embedded Clock
 DC balanced encoding which guarantees significant
transition frequency for use with clock and data recovery
(CDR) designs
 Encoding allows both data and control characters –
control characters can be used to specify link alignment,
maintenance, monitoring, etc.
 Detection of single bit error events on the link
► Serial Lane Alignment
 Using special training patterns with control characters,
lanes can be aligned across a “link”
 Trace-to-trace tolerance may be relaxed, relative to
synchronous sampling parallel LVDS designs
► Serial Lane Maintenance/Monitoring
 Alignment maintained through super-frame structure and
use of specific “characters” to guarantee alignment
 Link quality monitored at receiver on lane by lane basis
 Link established and dropped by receiver based on error
thresholds
5

Key Signals in JESD204B Systems
► Device Clock
 A clock signal in the system which is a harmonic of the frame
rate of the data on the link. In JESD204B systems, the
frame clock is no longer the master system reference.
► SYNC~
 Same as JESD204A except synchronous to local multiframe
clocks (LMFC) instead of the frame clock.
► Lane 0, … , L-1
 Differential lanes on the link
 Typically high speed current mode logic (CML)
 8B/10B code groups are transmitted MSB first/LSB last.
► SYSREF (Optional)
 An optional source-synchronous, high slew rate timing resolution
signal responsible for resetting device clock dividers (including
LMFC) to ensure deterministic latency.
 One shot, “gapped periodic” or periodic.
 Distributed to both ADCs/DACs and ASIC/FPGA logic devices
in the system.
 When available, SYSREF is the master timing reference in
JESD204B systems since it is responsible for resetting the
LMFC references.
6

Deterministic Latency in JESD204x
► Latency can be defined as deterministic when the time from the input of the JESD204x transmitter
to the output of the JESD204x receiver is consistently the same number of clock cycles
► In parallel implementations, deterministic latency is rather simple – clocks are carried with the data
► In serial implementations, multiple clock domains exist, clock domain crossing require FIFOs, which
can cause nondeterminism
► JESD204 and JESD204A do not contain provisions for guaranteeing deterministic latency
► JESD204B looks to address this issue by specifying three device subclasses:
 Device Subclass 0 – no support for deterministic latency
 Device Subclass 1 – deterministic latency using SYSREF (above 500 MSPS)
 Device Subclass 2 – deterministic latency using SYNC~ (up to 500 MSPS)
7

JESD204 – Introduction
► High-speed serial link for data converters
between conveter and logic device (FPGA/ASIC)
 Up to 12.5* Gbps (raw data)
 Up to 32 lanes per link
► Handles data mapping and framing
► Multi-chip synchronization
► Deterministic latency
► Applications
 Communications
 Cellular Towers
 Software Defined Radio (SDR)
 Medical Imaging
 Radar
 Instrumentation
* Up to 16 Gbps or more out-of-spec

JESD204 – Challenges of High-Speed Links
► High-speed serial links are complex
 Lots of interconnected components
 Clockchip, Converter, FPGA
 Many PLLs and clock dividers
 With different constraints on the operating range
 Hundreds of registers to program
 Transceivers in FPGAs differ between vendors
and generations
 If any component along the link fails the whole link
fails
 Difficult to find initial working configuration set
 Difficult to debug
► Challenge: Alleviate complexity allowing end
users to manage the system from an
application perspective

Why do end users care?
► Application configuration
 Number of converters
 Converter sample rate
 Signal processing settings (like DDC)
► Interface configuration
 PLL settings, clock dividers
 JESD204B link configuration
 Lane rate
 Number of lanes
 Octets-per-frame, frames-per-multiframe, …
► Configuration settings are performance orientated and
different applications require different settings.
► Applications will want to change configuration settings
at runtime depending on operating conditions.
 low sample-rate in idle monitor-mode
 high-sample rate in active communication mode.
► Software-defined platforms are applications that require
ultimate re-configuration capabilities.
 software-defined measurement,
 software-defined radio
► Interface configuration settings are effectively baggage!
 They are necessary, but most application developers do not
care about the detailed interface settings are
 Would rather talk about application configuration settings
► JESD204B Interface Framework Solves this problem

Players in the subsystem
► Converter and Clockchip Vendor
 Provides hardware and datasheets with
configuration settings
► FPGA/ASIC Vendor
 Provides hardware, FPGA IP and datasheets with
► System Integrator
 Chooses components and designs PCB
 Implements interface components (HDL)
 Selects configuration settings
► Application Developer
 Implements signal processing application (both
software + FPGA HDL)
► Roles can overlap:
 When ADI builds a reference design/rapid prototyping platform it is both converter
vendor and system integrator
 Companies building specialized systems are both system integrator and
application developer
► Necessary communication between roles introduces friction,
misunderstandings and overhead.
► Sometimes converter/clockchip and FPGA vendors provide code
snippets for configuration. But no integration between the different
components and no system integration. The System Integrator is still on
their own to make things work, and the Application developer has no
hope.
► The system integrator has to carefully choose configuration settings that
allow interoperability between all components in the system. Needs to
become a expert for each component. This can be difficult, even more
so if the documentation is incomplete.
 Due to this complexity the system integrator might choose to only provide one or a
few operating profiles.
► The application developer is usually a domain expert for their specific
signal processing application. Very rarely a domain expert for
converters, on-PCB signaling standards or JESD204B specifically.
 This means they have to work with the setting profiles provided by the system
integrator. This is often a small subset of what the platform is actually capable off.
► Application developer looking for ease-of-use for component
configuration to be able to focus on their application.
► JESD204B Interface Framework allows ADI to become the System
Integrator as well.

What is the JESD204 Interface Framework?
► System-level integrated HDL and software
framework
► Framework handles system-level as well as
component-level constraints and dependencies
 Valid operating values of a configuration settings
 Relationship between different configuration
settings
 Constraints are propagated between connected
components
 PLL out frequency constraints will affect converter
sample rate constraints and vice versa.
► Framework provides diagnostics to detect
failure source

JESD204 Interface Framework Technical overview
► Operating Mode:
 Basic Mode: Developer provides application
 Framework uses heuristics to compute valid interface
configuration settings based on application
 Advanced Mode: Developer provides application
and interface configuration settings
 Framework validates interface configuration settings
 Reports settings that violate constraints
► Heuristics are based on best practices and have
to make trade-offs
► Might not always choose the perfect configuration
(e.g. due to hidden external constraints).
► Advanced mode allows users that are domain
experts for the JESD204B standard to choose
interface settings by hand.
► It is easy to make mistakes though when working
with a complex system, a single setting wrong
and the whole system fails. Configuration
validation allows finding the needle in the
haystack when things not working.

JESD204 Interface Framework – Introduction
► Integrated Framework covering the whole stack
 Hardware: Reference and rapid prototyping systems
 HDL: Components for JESD204 protocol handling
 Software: Drivers to manage clock-chips, converters and HDL
► Components have been co-designed for improved interoperability
► Key features
 Automatic interface configuration based on application settings
 High-level API
 Dynamic re-configuration
 Improved diagnostics
► ADI provides full stack reference designs
 Works out of the box
 Starting point for development of custom designs

JESD204 Interface Framework – Configuration Management
Application Configuration
► Performance oriented
 Different applications require different settings
 E.g.
 Number of converters
 Converter sample rate
 Signal processing (DDC/DUC)
► Change at runtime based on operating conditions
► Framework hides the details of interface
configuration
 Automatically derived from application configuration
► Considers component and board constraints
 E.g.
 PLL VCO ranges
 Minimum and maximum lane rate
 Number of connected lanes
Interface Configuration
► Required to get data from converter to
application
 Change based on application settings
 E.g.
 PLL configuration, clock dividers
 Lane rate, number of lanes
 Octets-per-frame, frames-per-multiframe, ...

JESD204 Interface Framework – Benefits
► Automatic interface configuration based on
application settings
 High level API
 Focus on developing application
 No need to work with raw register values
► Manages system complexity
 Less domain specific knowledge required
 Simplified system bring-up
 Reduced development time
 Faster time to market
► Improved diagnostics
 Introspection points throughout the whole
interface chain
 Find out what is wrong when something is wrong
 Notifications about runtime errors
 Automatic link recovery
► Dynamic re-configuration
 Switch between different application profiles at
runtime
 Allows software defined applications
 Software defined radio
 Software defined instrumentation

ADI JESD204 Interface Framework
Architecture

JESD204 Hardware Considerations
► Clocking
 Single clock source for the system
 Reference clock
 Device clock
► SYSREF for deterministic latency (Subclass 1
operation)
 Source synchronous with the device clock
 Usually generated by the same clock generator IC
► FPGA selection
 Transceivers support the desired lane rate
► Pin Selection
 Use MGTREFCLK pin for transceiver reference
 Use global clock for device clock
 SYSREF, usually connected to a HP pin

JESD204 Layers
► Layers communicate via well defined interfaces
► PHY layer
 FPGA vendor and family specific high-speed
transceiver
► Link layer
 Generic JESD204 link layer processing core
► Transport layer
 Converter specific
► Application layer
 Reference design by ADI
 Replaceable with customer custom logic
► Software Drivers
 Control various layers and devices
 Heuristics to ensure proper operation

JESD204 ADI HDL IPs
► JESD204B Physical Layer
 Xilinx
 UTIL_ADXCVR
 AXI_ADXCVR
 Altera / Intel
 JESD204_PHY
 AVL_ADXCFG
 AXI_ADXCVR
► JESD204B Data Link Layer
 ADI JESD204 IP
 JESD204 RX
 JESD204 TX
► JESD204B Transport Layer
 AXI_AD9680
 AXI_AD9144
 AXI_AD9250
 AXI_AD9625
 AXI_AD9371
 AXI_AD6676
 AD-IP-JESD204-ADC (under development, replace above)
 AD-IP-JESD204-DAC (under development, replace above)

JESD204 HDL Physical Layer
Xilinx
► JESD204B Physical Layer
 Responsible for instantiating and configuring the high-speed serial transceivers
 UTIL_ADXCVR instantiates transceivers available in the FPGA (GTX, GTH3, GTH4)
 AXI_ADXCVR provides an AXI interface for performing DRP reads and writes to the transceivers, allowing for
dynamic reconfiguration
 Supports transceiver sharing between TX and RX IPs
► Xilinx JESD204-PHY IP can be used as an alternative to implement the physical layer, as it’s part of
Vivado without additional licensing
► We are currently evaluating the pro’s and con’s of integrating Xilinx JESD204-PHY as part of our
framework

UTIL_ADXCVR
Xilinx
► Supports GTX2,GTX3 and GTX4
► Exposes all the necessary attributes for
QPLL/CPLL configuration
► Supports shared transceiver mode
► Supports dynamic reconfiguration
► RX Eye Scan
► Clocking:
 DRP Clock
 Reference Clock
 AXI Clock, microprocessor clock

GTX2 Quad
Xilinx
► QPLL
► CPLL
Source : Xilinx datasheets

GTXE2 QPLL and CPLL Configuration
Xilinx
► QPLL ► CPLL
► VCO operating range: GTX: 1.6GHz to 3.3GHz

GTXE2 Clocking
Xilinx
► The reference clock must be fed through the
MGTREFCLK pins, either corresponding to the
current QUAD or adjacent QUAD
► The reference clock can be used also as
device clock to drive the Data Link Layer, as
long as certain conditions are met
► RX/TXSYSCLKSEL and RX/TXOUTCLKSEL
configure the output of the TXOUTCLK port,
which can be used to drive the Data Link Layer
► Data Link Layer clock always has a frequency
equal with lane rate / 40

UTIL_ADXCVR Customization
Xilinx
► Number of lanes mandatory
► XCVR Type
 0 = GTX (7 Series)
 1 = GTH3 (Ultrascale)
 2 = GTH4 (Ultrascale+)
► Parameters correctly defined for default
operation, software just brings core out of reset
► Parameters left as default, software must
configure the transceiver through DRP before
bringing out of reset
► Specific values can be found in the Transceiver
User Guide for the specific Transceiver type

AXI_ADXCVR
Xilinx
► Simple software interface, if HDL correctly
configured. The transceiver initialization
sequence walk through is fully handled by the
HDL
► Reconfiguration access allows broadcast,
software may choose to see the link as a single
primitive
► Statistical eye scan fully implemented in HDL
► No JESD204 specific functionality
► Supports up to 16 transceiver lanes per link

The Statistical Eye (2D Post Equalization)
Xilinx
► The Rx Eye Scan in Xilinx GTH, GTX, and GTP
transceivers of Xilinx FPGAs provides a mechanism to
measure and visualize the receiver eye margin after the
equalizer.
► Statistical eye scan functionality on per-lane basis is based
on comparison between the data sample in the nominal
center of the eye and the offset sample captured by an
independent and identical circuitry at a programmable
horizontal and vertical offset.
► Bit error (BER) is defined as a mismatch between these
two samples.
► Taking BER measurements at all horizontal and vertical
offsets allows drawing a 2D eye diagram while enabling
BER to be measured with high confidence down to
10
-15
.
30
Nominal Sample
Offset Sample

JESD204B High Speed ADC Demo
31
AD9250 JESD204B SerDes outputs measured
at the Tx pins at 5 Gbps using $250k scope
AD9250-FMC-250EBZ
• 2× AD9250 14-bit/250 MSPS ADC with JESD204B
• AD9517-1 clock generator
• 3× ADP151 LDO
• 4× ADP1753 LDO
• 2× ADP2301 switcher
Xilinx Zynq FPGA ZC706 Evaluation Kit
Recovered eye (after EQ)
Analog inputs
Verification of signal performance
using VisualAnalog™
The Rx Eye Scan in
transceivers of Xilinx 7 series
FPGAs provides a mechanism
to measure and visualize
receiver eye margin, based on
comparison between the data
sample in the nominal
center of the eye and an offset
sample.

Arria 10 JESD204 Diagram
► Physical layer implemented partially in
fabric
 No need for additional license
► Data Link Layer implemented fully in
fabric
► Physical Media Attachment (PMA)
► Physical Coding Sublayer (PCS)
Source : Intel datasheets

Arria 10 Transceiver
► 6 Channels per bank
► 2 fPLLs
► 2 ATX PLLs
► 2 CMU PLLs
► 6 Local CGB (clock generator)
► Dynamically reconfiguration for fPLL,
ATX PLL, CDR PLL

Arria 10 Transceiver Channel

JESD204B_PHY Standard PCS
Intel
► Arria 10 Native PHY Standard
PCS
 Depends on the speedgrade of
transceivers
 Max lane rate 12 Gbps
 Configured for 4 octets per beat
 8B/10B encoder/decoder included in
Hard PCS
 Character Alignment (Word Aligner)
included in Hard PCS

JESD204B_PHY Enhanced PCS
Intel
► Arria 10 Native PHY Enhanced
PCS
 Part of the PCS implemented in
fabric
 Configured for 4 octets per beat
 Lane rates over 12 Gbps
 8B/10B encoder/decoder included in
Soft PCS
 Character Alignment (Word Aligner)
included in Soft PCS

Arria 10 Transceiver PLL Description
► Advanced Transmit (ATX) PLL
 Best jitter performance
 LC tank based voltage controlled oscillator
 Support fractional synthesis mode
 Used for both bonded and non-bonded channel
configurations
► Fractional (fPLL) PLL
 Ring oscillator based VCO
 Supports fractional synthesis mode
 Used for both bonded and non-bonded channel
configurations
► Clock Multiplier Unit (CMU) PLL
 Ring oscillator based VCO
 Used as an additional clock source for non-
bonded applications

AD-IP-JESD204
► Subclass 0 and Subclass 1 support
► Deterministic Latency (for Subclass 1
operation)
► Runtime re-configurability through memory-
mapped register interface (AXI4)
► Interrupts for event notification
► Diagnostics
► Max Lanerate: 16 Gbps
► Low Latency
► Independent per lane enable/disable
► Common output interface Xilinx and Intel
(Altera)

AD-IP-JESD204 TX
► Clock domains:
 the AXI clock domain for control path
 the device clock, as described in the JESD204B
specification. Must be line clock / 40 for correct
operation.
► This IP is the equivalent of the Xilinx licensed
JESD204
► We provide Linux and baremetal software
drivers for setting up parameters

AD-IP-JESD204 RX
► Clock domains:
 the AXI clock domain for control path
 the device clock, as described in the JESD204B
specification. Must be line clock / 40 for correct
operation.
► This IP is the equivalent of the Xilinx licensed
JESD204
► We provide Linux and baremetal software
drivers for setting up parameters

JESD204 Transport Layer
► Transport layer peripherals are responsible for
converter specific data framing and de-framing.
► We currently have support for selected lane
configurations for the following ICs:
► ADCs
 AD6676
 AD9250
 AD9625
 AD9671
 AD9680
► DACs
 AD9144
 AD9152
 AD9162
► Transceivers
 AD9371
► AXI-Stream
► FIFO
► Clock
► Valid
► Data
► Enable
32-bits per lane
32-bits per lane

Supported Software Environments
Linux
► Fully integrated operating system
► Out-of-the-box support for many external
components
 Networking: Ethernet, wireless, Bluetooth
 Storage: SD card, hard drive
 Audio, Video
 Human Input Devices: Keyboard, mouse,
touchscreen
► ADI converter drivers use the IIO framework
 Easy integration into external tools: Visual Analog,
Matlab/Simulink, GNU Radio, IIO-Scope
 Programming interfaces for C, C++, C#, Python
NoOS
► Bare-metal / Low-overhead
► Allows more bespoke applications
► Easier to setup for very simple tasks
 More effort required for complex tasks

Linux
Physical Layer Devicetree
zynq-zc706-adv7511-fmcdaq2.dts
axi_ad9680_adxcvr: axi-ad9680-adxcvr@44a50000 {
compatible = "adi,axi-adxcvr-1.0";
reg = <0x44a50000 0x1000>;
clocks = <&clk0_ad9523 4>;
clock-names = "conv";
#clock-cells = <1>;
clock-output-names = "adc_gt_clk", "rx_out_clk";
adi,sys-clk-select = <0>;
adi,out-clk-select = <4>;
adi,use-lpm-enable;
adi,use-cpll-enable;
};
axi_ad9144_adxcvr: axi-ad9144-adxcvr@44a60000 {
compatible = "adi,axi-adxcvr-1.0";
reg = <0x44a60000 0x1000>;
clocks = <&clk0_ad9523 9>;
clock-names = "conv";
#clock-cells = <1>;
clock-output-names = "dac_gt_clk", "tx_out_clk";
adi,sys-clk-select = <3>;
adi,out-clk-select = <4>;
adi,use-lpm-enable;
};

Linux
Data Link Layer Transmit Devicetree
► Required properties:
 compatible: Must always be “adi,axi-jesd204b-tx-
1.00.a”
 reg: Base address and register area size. This
parameter expects a register range.
 interrupts: Property with a value describing the
interrupt number.
 clock-names: List of input clock names -
“s_axi_aclk”, “device_clk”
 clocks: Clock phandles and specifiers (See clock
bindings for details on clock-names and clocks).
 adi,frames-per-multiframe: Number of frames per
multi-frame (K)
 adi,octets-per-frame: Number of octets per frame
(N)
► Optional property:
 adi,high-density: If specified the JESD204B link is
configured for high density (HD) operation.
► zynq-zc706-adv7511-fmcdaq2.dts
axi_ad9144_jesd: axi-jesd204-tx@44a90000 {
compatible = "adi,axi-jesd204-tx-1.0";
reg = <0x44a90000 0x1000>;
interrupts = <0 54 0>;
clocks = <&clkc 16>, <&axi_ad9144_adxcvr 1>, <&axi_ad9144_adxcvr 0>;
clock-names = "s_axi_aclk", "device_clk", "lane_clk";
adi,octets-per-frame = <1>;
adi,frames-per-multiframe = <32>;
adi,converter-resolution = <16>;
adi,bits-per-sample = <16>;
adi,converters-per-device = <2>;
#clock-cells = <0>;
clock-output-names = "jesd_dac_lane_clk";
};

Linux
Data Link Layer Receive Devicetree
► Required properties:
 compatible: Must always be “adi,axi-jesd204b-rx-
1.00.a”
 reg: Base address and register area size. This
parameter expects a register range.
 interrupts: Property with a value describing the
interrupt number.
 clock-names: List of input clock names -
“s_axi_aclk”, “device_clk”
 clocks: Clock phandles and specifiers (See clock
bindings for details on clock-names and clocks).
 adi,frames-per-multiframe: Number of frames per
multi-frame (K)
 adi,octets-per-frame: Number of octets per frame
(N)
► Optional properties:
 adi,high-density: If specified the JESD204B link is
configured for high density (HD) operation.
axi_ad9680_jesd: axi-jesd204-rx@00040000 {
compatible = "adi,axi-jesd204-rx-1.0";
reg = <0x00040000 0x4000>;
interrupt-parent = <&intc>;
clocks = <&sys_clk>, <&rx_device_clk_pll>, <&axi_ad9680_xcvr>;
clock-names = "s_axi_aclk", "device_clk", "lane_clk";
adi,octets-per-frame = <1>;
adi,frames-per-multiframe = <32>;
clock-output-names = "jesd_adc_lane_clk";
};

Linux
Transport Layer Devicetree
rx_dma: rx-dmac@7c400000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x7c400000 0x10000>;
#dma-cells = <1>;
clocks = <&clkc 16>;
dma-channel {
adi,source-bus-width = <64>;
adi,destination-bus-width = <64>;
adi,type = <0>; }; };
axi_ad9680_core: axi-ad9680-hpc@44a10000 {
compatible = "adi,axi-ad9680-1.0";
reg = <0x44a10000 0x10000>;
dmas = <&rx_dma 0>;
dma-names = "rx";
spibus-connected = <&adc0_ad9680>; };
tx_dma: tx-dmac@7c420000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x7c420000 0x10000>;
#dma-cells = <1>;
clocks = <&clkc 16>;
dma-channel {
adi,source-bus-width = <128>;
adi,destination-bus-width = <128>;
adi,type = <1>;
adi,cyclic; };};
axi_ad9144_core: axi-ad9144-hpc@44a04000 {
compatible = "adi,axi-ad9144-1.0";
reg = <0x44a04000 0x4000>;
dmas = <&tx_dma 0>;
dma-names = "tx";
spibus-connected = <&dac0_ad9144>;
adi,axi-pl-fifo-enable;};

No-OS
Structures for Physical Layer
typedef struct {
uint8_t gt_type;
uint8_t qpll_enable;
uint8_t lpm_enable;
uint32_t sys_clk_sel;
uint32_t out_clk_sel;
uint32_t out_div;
} fpga_dev;
typedef enum {
PM_200,
PM_700,
PM_1250,
} clk_ppm;
typedef struct {
uint32_t base_address;
uint8_t initial_recalc;
uint8_t reconfig_bypass;
uint32_t ref_clock_khz;
uint32_t link_clk_khz;
uint32_t lane_rate_kbps;
uint32_t lanes_per_link;
uint16_t encoding;
uint8_t rx_tx_n;
clk_ppm refclk_ppm;
fpga_dev dev;
} xcvr_core;

No-OS
Structures for JESD204 Data Link Layer
typedef struct {
uint32_t base_address;
uint8_t rx_tx_n;
uint8_t scramble_enable;
uint8_t lanes_per_device;
uint8_t octets_per_frame;
uint8_t frames_per_multiframe;
uint8_t converters_per_device;
uint8_t resolution;
uint8_t bits_per_sample;
uint8_t high_density;
uint8_t subclass_mode;
sys_ref_type sysref_type;
uint32_t sysref_gpio_pin;
} jesd_core;
typedef enum {
EXTERN,
INTERN
} sys_ref_type;

AD-IP-JESD204
Diagnostics
► Clock rate monitoring for all system clocks
 Detect bad clock wiring
 Detect clock failures
► Initial lane sequence monitoring and
verification
 Detect lane swaps
► Lane arrival monitoring (relative to SYSREF)
 Detect potential sources of non-deterministic
latency
► Continuous monitoring
 Application is notified as soon as failure occurs

AD-IP-JESD204
Diagnostics - Example
Link Status
Link is enabled
Measured Link Clock: 250.012 MHz
Reported Link Clock: 250.000 MHz
Lane rate: 10000.000 MHz
Lane rate / 40: 250.000 MHz
Link status: DATA
SYSREF captured: Yes
SYSREF alignment error: No
Lane Status
CGS state: DATA
Initial Frame Synchronization: Yes
Lane Latency: 3 Multi-frames and 28
Octets
Initial Lane Alignment Sequence: Yes
DID: 0, BID: 1, LID: 0, L: 3, SCR: 1, F:
0 ...
Test pattern monitoring
CH0 : PN9 : In Sync : OK
CH1 : PN9 : In Sync : OK
CH0 : PN23A : In Sync : OK
CH1 : PN23A : In Sync : OK

What ADI products are supported?
► HDL
 ADCs
 AD6676, AD9234, AD9250, AD9625, AD9680, AD9683,
AD9250
 DACs
 AD9144, AD9152, AD9162
 Transceivers
 AD9371/AD9375, AD9379
► Software
 ADCs
 AD6676, AD9234, AD9250, AD9625, AD9680, AD9683,
AD9250
 DACs
 AD9144, AD9152, AD9162
 Transceivers
 AD9371/AD9375
 Clocking
 AD9523-1, AD9528, AD9517, AD9508, AD9548
► Working on supporting all JESD supported
devices

What FPGA vendors/families does it support?
Now
► Xilinx
 7 Series (Kintex, Virtex, Zynq)
 Ultrascale (Kintex)
 Ultrascale+ (ZynqMP)
► Altera
 Arria10 SoC
 Arria10 GX
Future
► Based on customer feedback/demand
 Xilinx Artix
► No plan to support older FPGAs that are being
phased out by the Vendors themselves
 Xilinx: Virtex6
 Altera: Arria V, Cyclon V

Rapid Prototype Platforms Example using AD-IP-JESD204
► Collection of ADI components to form full signal
chain on a single PCB
 Power, clocking, converters, diagnostic
► No external components required
 Optional external clock
► FPGA Mezzanine Card (FMC) connector
 ANSI/VITA standard
 Compatible with many FPGA development boards
► Full HDL FPGA and software reference design
available
 Works out of the box
 Customer can use them as a development
starting point

Rapid Prototype Platforms - Examples
► Available now
 AD-FMCDAQ2-EBZ (AD9144, AD9680, AD9523-1)
 ADRV9371 (AD9371, AD9528)
 AD-FMCADC2-EBZ/AD-FMCADC3-EBZ (AD9625)
 AD-FMCADC4-EBZ (2xAD9680, AD9528)
 AD-FMCADC5-EBZ (2xAD9625, interleaved)
 AD-FMCJESDADC1-EBZ (AD9250, AD9517)
 AD6676EVB
► Shipping soon
 AD-FMCDAQ3-EBZ (AD9152, AD9680, AD9528)
 AD-FMCOMMS11-EBZ (AD9162, ADF4355, AD9508)

Example design DAQ2
► DAQ2 is an FMC board for the high speed
AD9144 DAC and AD9680 ADC. In this design,
we’ll use the AD9680 ADC at 1GSPS and two
out of the 4 AD9144 DAC at 1GSPS. The
clocking is provided by AD9523-1.
► For this design, we provide schematic, HDL
project, linux and baremetal software drivers.
► https://wiki.analog.com/resources/eval/user-
guides/ad-fmcdaq2-ebz

Hardware: Documentation
► All design files including schematics, layout, and board files are freely available for reuse and
customization
 https://wiki.analog.com/resources/eval/user-guides/ad-fmcdaq2-ebz/hardware

Generic ADI Base Design
► Every HDL design of a reference project can
be divided into two subsystems:
► The base design, which contains an
embedded processor - soft or hard - and all the
peripheral IPs that the carrier board supports
and are necessary to run a Linux distribution
on the system. These designs are carrier
dependent, each prototyping board having its
own base design.
► The board design, which is a direct integration
of all the necessary IP's into a specific base
design in order to support an FMC I/O board.
These designs are carrier independent and
common to all carrier boards.

FMC Board Diagram
► The JESD clocking system is provided by the
AD9523-1, Jitter Cleaner and Clock generator
with 14 differential Outputs. Part of the outputs
are also used for generating the SYSREF
signal.
► As requested by the JESD standard, a single
source provides clocking for all the
components of the system:
 ADC,
 receiver logic device in the FPGA,
 DAC
 transmitter logic device in the FPGA.
 Along with the clock, the SYSREF signal is
generated by AD9523 in order to control the
setup/hold relationship between the device clock
and SYSREF. This relationship allows for the
system to work in Subclass 1 and have a
deterministic latency.

DAQ2 Clocking
► AD9523 provide clocking to all system
components, as required by the JESD204B
specifications
► Separate reference clocks for QPLL and
CPLLs
► SYSREF is generated by AD9523 for all
components in the system
► JESD data clock is taken from the
RX/TXOUTCLK pins of the transceiver. This
limits the application to Subclass 0, when used
at maximum sampling rate
► If separate clock would be generated and
connected to a global clock pin, Subclass 1
could be supported

HDL Customization
► ADI recommends using TCL flow
► Revision control (all text files)
► Easy portability and re-use
 Automated IP version control
 Automated CPU addressing
 Automated CPU interrupt
 Automated memory map addressing
► Partitioned to support Plug-n-Play
 projects/common/zc706/zc706_system_bd.tcl
 projects/daq2/common/daq2_bd.tcl
 projects/daq2/zc706
► Your customized IP may be added in the ADI TCL
framework itself or kept and maintained
separately
► Project files in project/daq2/zc706
► system_project.tcl - This script is creating the actual
Vivado project and runs the synthesis/implementation
of the design
► system_bd.tcl - In this file is sourced the base
design's Tcl script and the board design's Tcl script
► system_constr.xdc - Constraint files of the board
design. Here is defined the FMC IO's and board
specific clock signals.
► system_top.v - Top wrapper file, in which the
system_wrapper.v module is instantiated, and a few I/O
macros are defined. The IO port of this verilog module
will be connected to actual IO pads of the FPGA.
► Makefile - This is an auto-generated file, but after
updating the carrier name, should work with the new
project without an issue.

HDL Physical layer
► projects/daq2/common/daq2_bd.tcl
ad_ip_instance axi_adxcvr axi_ad9144_xcvr
ad_ip_parameter axi_ad9144_xcvr CONFIG.NUM_OF_LANES 4
ad_ip_parameter axi_ad9144_xcvr CONFIG.QPLL_ENABLE 1
ad_ip_parameter axi_ad9144_xcvr CONFIG.TX_OR_RX_N 1
ad_ip_instance axi_adxcvr axi_ad9680_xcvr
ad_ip_parameter axi_ad9680_xcvr CONFIG.NUM_OF_LANES 4
ad_ip_parameter axi_ad9680_xcvr CONFIG.QPLL_ENABLE 0
ad_ip_parameter axi_ad9680_xcvr CONFIG.TX_OR_RX_N 0
ad_ip_instance util_adxcvr util_daq2_xcvr
ad_ip_parameter util_daq2_xcvr CONFIG.RX_NUM_OF_LANES 4
ad_ip_parameter util_daq2_xcvr CONFIG.TX_NUM_OF_LANES 4

HDL Data Link Layer
► projects/daq2/common/daq2_bd.tcl
adi_axi_jesd204_tx_create axi_ad9144_jesd 4
adi_axi_jesd204_rx_create axi_ad9680_jesd 4

HDL Design Transport Layer
projects/daq2/common/daq2_bd.tcl
ad_ip_instance axi_ad9144 axi_ad9144_core
ad_ip_parameter axi_ad9144_core CONFIG.QUAD_OR_DUAL_N 0
ad_ip_instance axi_ad9680 axi_ad9680_core

HDL Design Transceiver Sharing
projects/daq2/common/daq2_bd.tcl
ad_xcvrcon util_daq2_xcvr
axi_ad9680_xcvr
axi_ad9680_jesd
ad_xcvrcon util_daq2_xcvr
axi_ad9144_xcvr
axi_ad9144_jesd {0 2 3 1}
RX_DATA_1
CH0
TX_DATA_3
CH1
RX_DATA_3 TX_DATA_2
CH2
RX_DATA_2 TX_DATA_1
CH3
RX_DATA_0 TX_DATA_0
RX_DATA_1
CH0
TX_DATA_3
CH1
RX_DATA_3 TX_DATA_2
CH2
RX_DATA_2 TX_DATA_1
CH3
RX_DATA_0 TX_DATA_0
UTIL_DAQ2_XCVRGTXE2 QUAD

QSYS JESD204 RX
► Single IP for Physical and Data
Link layers
► Covers all clock generation
► Resets for transceivers and PLLs
embedded in the IP
► Clock domains
 System clock
 Used for configuration and status
 Reference clock
 Used as reference for PLLs
 Link Clock
 Used for transferring data to the
transport layer
► Lane swapping
► Soft PCS

QSYS JESD204 TX
► Single IP for Physical and Data
Link layers
► Covers all clock generation
► Resets for transceivers and PLLs
embedded in the IP
► Clock domains
 System clock
 Used for configuration and status
 Reference clock
 Used as reference for PLLs
 Link Clock
 Used for transferring data to the
transport layer
► Lane swapping
► Soft PCS

Linux
► Embedded Linux
► Maintained and released with HDL
 https://github.com/analogdevicesinc/linux
► Kernel drivers
 Specified, initialized via device tree
► IIO framework
 Registered as an IIO device
 root/drivers/staging/iio/Documentation/device.txt
► Accessible as
 /sys/bus/iio/devices/iio:deviceN
root:/> cd /sys/bus/iio/devices/iio:device0/
root:/> cat name
ad9523-lpc

Linux IIO
► Lots of information online
 https://wiki.analog.com/resources/tools-
software/linux-software/libiio
► Application is independent of back end
 Ethernet, USB, Serial etc.
 iio_channel_read(,, &received_samples[0], );
 iio_channel_write(,, &transmit_samples[0],);
 Figurative only, actual function call and parameters
may vary
► The IIOScope application in the demo is running
FFTW on the received samples using the IIO
framework

IIOScope Application
► Application to visualize/analyze received
samples
► Also provides control functions (Debug window)
► IIO frame work and FFTW (http://www.fftw.org)
► Time, frequency and constellation plots
► Remote and local hosts
► Open source
 https://github.com/analogdevicesinc/iio-
oscilloscope

No-OS (Bare Metal)
► Simple generic ‘C’
► Mostly duplicated Kernel Drivers
► Proof of concept/Sanity checking
► Maintained and released with HDL & Linux
 https://github.com/analogdevicesinc/no-OS
► Capture is possible but usually requires the tool
to off load samples
► Linux is recommended for its shear capability
and ease of use
// adc device-clk-sysref, fpga-clk-sysref
ad9523_channels[ADC_DEVICE_CLK].channel_num = 13;
ad9523_channels[ADC_DEVICE_CLK].channel_divider = 1;
ad9523_channels[ADC_DEVICE_SYSREF].channel_num = 6;
ad9523_channels[ADC_DEVICE_SYSREF].channel_divider = 128;
ad9144_channels[0].dds_frequency_0 = 11*1000*1000;
ad9144_channels[0].sel = DAC_SRC_DDS;
ad9680_setup(&ad9680_spi_device, ad9680_param);
jesd_setup(ad9680_jesd);
xcvr_setup(ad9680_xcvr);
jesd_status(ad9680_jesd);
adc_setup(ad9680_core);

Linux: All together, how simple is it?
► Get Development Kit with High Speed Analog & JESD204B
► Clone the HDL repository and build the FPGA files
 git clone https://github.com/analogdevicesinc/hdl.git
 make –C hdl/projects/daq2/zc706
► Clone the Linux repository and build the image files
 git clone https://github.com/analogdevicesinc/linux.git
 export ARCH=arm
 export CROSS_COMPILE=arm-xilinx-linux-gnueabi-
 make –C linux zynq_xcomm_adv7511_defconfig
 make -C linux -j5 UIMAGE_LOADADDR=0x8000 uImage

No-OS: All together, how simple is it?
► Get the Development Kit with High Speed Analog & JESD204B
► Clone the HDL repository and build the FPGA files
 git clone https://github.com/analogdevicesinc/hdl.git
 make –C hdl/projects/daq2/zc706
► Clone the no-OS repository and build the image files
 git clone https://github.com/analogdevicesinc/no-OS.git
 make -C no-OS/fmcdaq2/zc706
► Connect the board to your host machine
 make -C no-OS/fmcdaq2/zc706 run

Not a Lawyer
► Notice of proprietary information, Disclaimers and Exclusions Of Warranties
The ADI Presentation is the property of ADI. All copyright, trademark, and other intellectual property and proprietary rights in the ADI
Presentation and in the software, text, graphics, design elements, audio and all other materials originated or used by ADI herein (the "ADI
Information") are reserved to ADI and its licensors. The ADI Information may not be reproduced, published, adapted, modified, displayed,
distributed or sold in any manner, in any form or media, without the prior written permission of ADI.
► THE ADI INFORMATION AND THE ADI PRESENTATION ARE PROVIDED "AS IS". WHILE ADI INTENDS THE ADI INFORMATION AND
THE ADI PRESENTATION TO BE ACCURATE, NO WARRANTIES OF ANY KIND ARE MADE WITH RESPECT TO THE ADI
PRESENTATION AND THE ADI INFORMATION, INCLUDING WITHOUT LIMITATION ANY WARRANTIES OF ACCURACY OR
COMPLETENESS. TYPOGRAPHICAL ERRORS AND OTHER INACCURACIES OR MISTAKES ARE POSSIBLE. ADI DOES NOT
WARRANT THAT THE ADI INFORMATION AND THE ADI PRESENTATION WILL MEET YOUR REQUIREMENTS, WILL BE ACCURATE, OR
WILL BE UNINTERRUPTED OR ERROR FREE. ADI EXPRESSLY EXCLUDES AND DISCLAIMS ALL EXPRESS AND IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT OF ANY THIRD PARTY
INTELLECTUAL PROPERTY RIGHTS. ADI SHALL NOT BE RESPONSIBLE FOR ANY DAMAGE OR LOSS OF ANY KIND ARISING OUT OF
OR RELATED TO YOUR USE OF THE ADI INFORMATION AND THE ADI PRESENTATION, INCLUDING WITHOUT LIMITATION DATA
LOSS OR CORRUPTION, COMPUTER VIRUSES, ERRORS, OMISSIONS, INTERRUPTIONS, DEFECTS OR OTHER FAILURES,
REGARDLESS OF WHETHER SUCH LIABILITY IS BASED IN TORT, CONTRACT OR OTHERWISE. USE OF ANY THIRD-PARTY
SOFTWARE REFERENCED WILL BE GOVERNED BY THE APPLICABLE LICENSE AGREEMENT, IF ANY, WITH SUCH THIRD PARTY.

AD-IP-JESD204
HDL License
► GPL-2
 Zero cost, but not Public domain
 Unlimited right to run program
 Unlimited access to source code
 Unlimited right to distribute verbatim copies of
source
 May create derivatives IF you agree to make
the derivatives free and open (distribute your
source)
 License is “viral”
 No warranties; disclaimer of consequential
damages
 Free EngineerZone support on ADI parts only
► Commercial License
 $5000 cost
 unlimited use, modification, and distribution
 Can distribute binaries without releasing source code
 Perpetual, Multi-project, Multi-site
 Must use with ADI devices
 Can sub-license to end users of customer’s product
for use on that product only
 No warranties; disclaimer of consequential damages
 Commercial Support
 one-on-one phone/email support for 10 hours
 After that, EngineerZone
►Dual-licensing distributes software under two or more different sets of terms, conditions,
and obligations
►Customers can choose the terms under which they want to use or distribute the software
►Source is the same for both licenses

AD-IP-JESD204
Software License
► Linux kernel drivers
 GPL-2 (License of the Linux kernel)
► libiio
 LGPL-2 (non-viral)
► No-OS drivers
 Permissive ADI BSD
 Allows modification without having to share changes
 Only restriction is has to be used with ADI
components
Only ADI Devices

Obtaining the core
► Analog Devices Web Site
► Arrow

More Information
► https://wiki.analog.com/jesd204
► HDL: https://github.com/analogdevicesinc/hdl/tree/dev/library/jesd204
► Linux drivers: https://github.com/analogdevicesinc/linux/tree/jesd204/drivers/iio/jesd204
► Support: https://ez.analog.com/community/fpga
► Email address for licensing: jesd204-licensing@analog.com
► Wiki pages:
 https://wiki.analog.com/resources/fpga/docs/hdl
 https://wiki.analog.com/resources/fpga/docs/util_xcvr
 https://wiki.analog.com/resources/fpga/docs/axi_adxcvr
 https://wiki.analog.com/resources/fpga/docs/axi_ad9144
 https://wiki.analog.com/resources/tools-software/linux-drivers-all
► https://www.xilinx.com/products/technology/high-speed-serial.html
► https://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf
► https://www.xilinx.com/support/documentation/user_guides/ug576-ultrascale-gth-transceivers.pdf
► https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/arria-10/ug_arria10_xcvr_phy.pdf
► https://www.altera.com/en_US/pdfs/literature/ug/ug_jesd204b.pdf

Call to Action
► Talk to your local contacts
► Go through reference design
 AD-FMCDAQ2-EBZ
► Ask questions on Engineerzone
 https://ez.analog.com/community/fpga

AD-IP-JESD204 JESD204B Interface Framework

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