Security is primary concern in our day-to-day life. Everyone wants to be as much as secure as possible. The UART (universal asynchronous receiver and transmitter) module provides asynchronous serial communication with external devices such as modems and other computers. The UART can be used to control the process of breaking parallel data from the PC down into serial data that can be transmitted and vice versa for receiving data. The UART allows the devices to communicate without the need to be synchronized. UART is a popular method of serial asynchronous communication. Typically, the UART is connected between a processor and a peripheral. To the processor, the UART appears as an 8-bit read-write parallel port that performs serial-to-parallel conversions for the processor, and vice versa for the peripheral. With the implementation of UART the serial communication is done in high data rate and no interrupts. Baud rate generator provides high data rate and interrupt controller handles all the interrupts. The UART serial communication interface device receives data and converts data from serial to parallel, where as the transmitter performs parallel to serial conversion.
This presentation discusses the details of the I2C protocol and interfacing of EEPROM with 8051 based on I2C protocol. It also discusses the other applications of I2C protocol
This presentation discusses the details of the I2C protocol and interfacing of EEPROM with 8051 based on I2C protocol. It also discusses the other applications of I2C protocol
UART – Stands for Universal Asynchronous Receiver Transmitter It is a piece of hardware that acts as a bridge between the processor and the serial communication protocol or port (RS-232). It performs parallel – to – serial data conversion at the transmitter side and serial – to – parallel data conversion at the receiver side.Asynchronous serial communication.
A serial communication can be done using fewer wires as compared to its parallel counterpart. It is a cheapest communication device with a single wire for transmitting the data and another wire for receiving. When the high-speed data transfer is not required UART is used. In a simple serial communication, 3 pins are used: TxD, RxD and GND.
At Transmission side (i.e. From Microcontoller), one can write data into UART Data Register (e.g. UART0_DR) by using software code.
These 8 bits of data from Data Register is passed to Tx FIFO Buffer. After that, the data is sent out(one at a time) from Tx Shift Register.
TxFIFO flag = 1 (Buffer full) TxFIFO flag = 0 (not full - Software can write to Data Register)
At Receiver end, there is Rx FIFO Buffer.
RxFIFO Empty flag = 1 (Buffer is empty) RxFIFO Empty flag = 0 (Buffer has data to be read)
A frame is the unit of transmission in serial communications
Start bit: To declare the start of transmission.
Data bits: 4,5,6,7, or 8 bits of useful data bits.
Parity bit : To check for transmission errors.
Stop bit: To declare end of frame
Parity bit is used to check the integrity of a frame and signal if an error occurred during transmission.
It is an extra bit added to the end of a frame.
Even parity :The number of ‘1’ symbols inside a frame must always be even.
Odd parity : The number of ‘1’ symbols inside a frame must always be odd
The configuration settings at both ends of Txd and Rxd:
Full or half-duplex operation
Data length
Start/Stop bits
Transmission speed.
EX:-198 = 11000110
Transmission speed
Common speed = 9600 bits/sec
1/9600 = 104 us.
After detecting start it will count 104us and complets start bit.
Then begins sampling the input bits after 52us with equal count of 104us between each bit untill the next stop bit with high pulse.
Advantages
Requires minimum wires
No need for clock or any other timing signal.
Parity bit ensures basic error checking.
Disadvantages
Size of the data in the frame is limited.
Can connect only two devices at a time
Speed for data transfer is less compared to parallel.
Transmitter and receiver must agree to the rules of transmission and appropriate baud rate must be selected.
if we are looking for a device to device serial communication then UART proves itself the best as it is easy to deal with and also widely used in many peripheral devices.
Serial Peripheral Interface (SPI) is an interface bus commonly used to send data between microcontrollers and small peripherals such as shift registers, sensors, and SD cards.
Direct Memory Access (DMA)-Working and ImplementationShubham Kumar
DMA is an important functionality of any computing system involving transfer of data from/to an I/O device. In this presentation, a brief description has been provided regarding how the DMA functionality is implemented on a normal PC as well as on an Intel Quark SoC based small Embedded System.Different implementations of the DMA functionality depend on the Controller Hub present on the SouthBridge of the MotherBoard of the respective platform.For example->DMA implementation in Intel ICH7 is different from those in Intel ICH to Intel ICH6. In the slides, "Galileo" refers to the Intel Galileo Board containing Intel Quark SoC. Intel Galileo Board contains Designware DMA controllers." dmatest.c " is a memory-to-memory data transfer test driver implementing DMA. This module is loaded and then memcpy is checked using dmesg. Do take a look at the "External Links and References" given at the end of the PPT.
This Presentation describes the ARM CORTEX M3 core processor with the details of the core peripherals. Soon a CORTEX base controller(STM32F100RBT6) ppt will be uploaded. For more information mail me at:gaurav.iitkg@gmail.com.
Implementation of Universal Asynchronous Receiver and TransmitterIJERA Editor
Universal Asynchronous Receiver Transmitter (UART) is the serial communication protocol that is used for data exchange between computer & peripherals. UART is a low velocity, short-distance, low-cost protocol. UART includes three modules which are received, the baud rate generator and transmitter. The UART design with Very High Description Language can be integrated into the Field Programmable Gate Array to achieve stable data transmission and to make system reliable and compact. In the result and simulation part, this project will focus on check the receive data with error free & baud rate generation at different frequencies. Before synthesizing of UART a baud rate generator is incorporated into the system. We use the frequency divider which sets itself to required frequency for the functionality at lower frequency. All modules are designed using VERILOG and implemented on Xilinx Suite development board.
UART – Stands for Universal Asynchronous Receiver Transmitter It is a piece of hardware that acts as a bridge between the processor and the serial communication protocol or port (RS-232). It performs parallel – to – serial data conversion at the transmitter side and serial – to – parallel data conversion at the receiver side.Asynchronous serial communication.
A serial communication can be done using fewer wires as compared to its parallel counterpart. It is a cheapest communication device with a single wire for transmitting the data and another wire for receiving. When the high-speed data transfer is not required UART is used. In a simple serial communication, 3 pins are used: TxD, RxD and GND.
At Transmission side (i.e. From Microcontoller), one can write data into UART Data Register (e.g. UART0_DR) by using software code.
These 8 bits of data from Data Register is passed to Tx FIFO Buffer. After that, the data is sent out(one at a time) from Tx Shift Register.
TxFIFO flag = 1 (Buffer full) TxFIFO flag = 0 (not full - Software can write to Data Register)
At Receiver end, there is Rx FIFO Buffer.
RxFIFO Empty flag = 1 (Buffer is empty) RxFIFO Empty flag = 0 (Buffer has data to be read)
A frame is the unit of transmission in serial communications
Start bit: To declare the start of transmission.
Data bits: 4,5,6,7, or 8 bits of useful data bits.
Parity bit : To check for transmission errors.
Stop bit: To declare end of frame
Parity bit is used to check the integrity of a frame and signal if an error occurred during transmission.
It is an extra bit added to the end of a frame.
Even parity :The number of ‘1’ symbols inside a frame must always be even.
Odd parity : The number of ‘1’ symbols inside a frame must always be odd
The configuration settings at both ends of Txd and Rxd:
Full or half-duplex operation
Data length
Start/Stop bits
Transmission speed.
EX:-198 = 11000110
Transmission speed
Common speed = 9600 bits/sec
1/9600 = 104 us.
After detecting start it will count 104us and complets start bit.
Then begins sampling the input bits after 52us with equal count of 104us between each bit untill the next stop bit with high pulse.
Advantages
Requires minimum wires
No need for clock or any other timing signal.
Parity bit ensures basic error checking.
Disadvantages
Size of the data in the frame is limited.
Can connect only two devices at a time
Speed for data transfer is less compared to parallel.
Transmitter and receiver must agree to the rules of transmission and appropriate baud rate must be selected.
if we are looking for a device to device serial communication then UART proves itself the best as it is easy to deal with and also widely used in many peripheral devices.
Serial Peripheral Interface (SPI) is an interface bus commonly used to send data between microcontrollers and small peripherals such as shift registers, sensors, and SD cards.
Direct Memory Access (DMA)-Working and ImplementationShubham Kumar
DMA is an important functionality of any computing system involving transfer of data from/to an I/O device. In this presentation, a brief description has been provided regarding how the DMA functionality is implemented on a normal PC as well as on an Intel Quark SoC based small Embedded System.Different implementations of the DMA functionality depend on the Controller Hub present on the SouthBridge of the MotherBoard of the respective platform.For example->DMA implementation in Intel ICH7 is different from those in Intel ICH to Intel ICH6. In the slides, "Galileo" refers to the Intel Galileo Board containing Intel Quark SoC. Intel Galileo Board contains Designware DMA controllers." dmatest.c " is a memory-to-memory data transfer test driver implementing DMA. This module is loaded and then memcpy is checked using dmesg. Do take a look at the "External Links and References" given at the end of the PPT.
This Presentation describes the ARM CORTEX M3 core processor with the details of the core peripherals. Soon a CORTEX base controller(STM32F100RBT6) ppt will be uploaded. For more information mail me at:gaurav.iitkg@gmail.com.
Implementation of Universal Asynchronous Receiver and TransmitterIJERA Editor
Universal Asynchronous Receiver Transmitter (UART) is the serial communication protocol that is used for data exchange between computer & peripherals. UART is a low velocity, short-distance, low-cost protocol. UART includes three modules which are received, the baud rate generator and transmitter. The UART design with Very High Description Language can be integrated into the Field Programmable Gate Array to achieve stable data transmission and to make system reliable and compact. In the result and simulation part, this project will focus on check the receive data with error free & baud rate generation at different frequencies. Before synthesizing of UART a baud rate generator is incorporated into the system. We use the frequency divider which sets itself to required frequency for the functionality at lower frequency. All modules are designed using VERILOG and implemented on Xilinx Suite development board.
Serial Communication Interface with Error Detectioniosrjce
UART is used for serial data communication. UART is a piece of computer hardware that translates
between parallel bits of data and serial bits. UART is usually an integrated circuit used for serial
communications over a computer or peripheral device serial port. Bits have to be moved from one place to
another using wires or some other medium. Over many miles, the expense of the wires becomes large. To reduce
the expense of long communication links carrying several bits in parallel, data bits are sent sequentially. Errors
may occur either internally or externally while we transmit information from source to destination. The errors
generated during the transmission would affect the performance of the overall system. In order to reduce the
errors we should incorporate any error detecting schemes like hamming decoder, check parity systems etc.
Different serial communication devices are available.
UART Serial Communication Module Design and Simulation Based on VHDLIJERA Editor
UART (Universal Asynchronous Receiver Transmitter) is a kind of serial communication protocol; mostly used for short-distance, low speed, low-cost data exchange between computer and peripherals. During the actual industrial production, sometimes we do not need the full functionality of UART, but simply integrate its core part. UART includes three kernel modules which are the baud rate generator, receiver and transmitter. The UART implemented with VHDL language and simulated using XILINX ISE12.1 to achieve compact, stable and reliable data transmission. It’s significant for the design of SOC. The simulation results are completely consistent.
this presentation contains all sort of information regarding USCI(Universal Serial Communication Interface)
UART, SPI, I2C etc.
this will be very helpful to the people those who are planning or starting projects or want to get idea how devices interfaced.
Synthesis & FPGA Implementation of UART IP Soft Coreijsrd.com
this paper presents synthesis and hardware implementation of fully functional Universal Asynchronous Receiver Transmitter Intellectual Property core using XILINX SPARTAN-3 XC3S400 series FPGA. The UART soft core module consists of a transmitter along with baud rate generator and a receiver module with false start bit detection features. This has been implemented using VERILOG hardware description language and synthesized using XILINX ISE development tools. All behavioral simulation of UART module performed using MODELSIM simulator. After successful FPGA implementation transmitter and receiver module was tested by connecting FPGA board with Hyper Terminal software via RS232 interface at a data speed of 9.6 kbps.
Embedded Communications Protocols UNIT 3PDF.pdfkanyaakiran
1
INDIAN KARTING RACE
2
Imperial Society
of Innovative
Engineers
Presents
INDIAN KARTING RACE (IKR 2018)
3
INDEX
Topic Page Number
Part I – ADMINISTRATIVE RULES
1. Introduction 4-6
2. Registration Requirement 7-9
3. Driver’s Requirement 8
4. Kart Eligibility 9
5. Registration Process and Deadlines 10-12
Part II – JUDGING CRITERIA
1. Pre Virtual Round 13
2. Virtual Round 13-16
3. College level Technical Inspection 16
4. Deadline and Penalties 16
5. Web based Submission 16
6. Event Points 17
7. Award List 18
PART III – TECHNICAL RULES
Vehicle Categories 20
1. Chassis Design Restriction 21-25
2. Wheels and Tyres 25-26
3. Driver’s Compartment 26
4. Steering 28
5. Braking 28-30
6. Power Unit and Transmission 30-32
7. Safety Measurements 33-36
8. Bodyworks 36-37
9. Compulsory Advertisement 37
PART IV – DYNAMIC ROUND
1. Dynamic Round Registration 38
2. Briefings 38
3. Photo Session/ Media 38-39
4. Static Event 39-40
5. Dynamic Event 41-43
6. Flags 43-44
PART V – DRIVER’S HANDBOOKS
1. Driver’s Requirement 45
2. Driver’s Equipment 45-46
3. Code of Conduct during event 46-47
4
ADMINISTRATIVE RULEBOOK
1. Introduction:
1.1. About ISIE:
Imperial Society of Innovative Engineers are well known Society of India for organizing
Motorsports events, live projects based Industrial Training and Research and publication.
ISIE – India provides a platform to the students and professionals for development and
enhancement of their technical as well as managerial skills. We are developing platform
especially for engineering students where they can easily face real-time engineering
problems and find the best solution, especially in the sector of Electric and Hybrid Vehicles.
ISIE - India is the India’s best platform for the engineering students to develop practical
skills. We believe in “Learning, Implementation, and Sharing”. The Society has a very strong
placement and consultancy wing that has an excellent network of the top companies.
Our core competencies include effective personalized industry based training and excellent
placements. ISIE is committed to the development in the field of renewable source of
energy; these are the best solution to save our environment and development of our
country. We are organizing Hybrid and Go Kart National and International event.
Our Accreditations:
Federation of Motor Sports Club of India (FMSCI) –
The FMSCI is recognized by the Government of India, Ministry of Youth Affairs and Sports as
the only National Sports Federation (NSF) for the promotion and governance of motorsports
in India. The FMSCI is also a long-standing member of the International Federations for
motorsports viz. Federation International de l' Automobile (FIA), Paris (four wheelers and
above) and Federation International de Motocyclisme (FIM), Geneva (2 and 3 wheeler
motorsports).
The FMSCI is also a member of the Indian Olympic Association. The FMSCI has a wide base
of affiliated member clubs spread across India.
ISO 9001:2008:
ISIE Awarded ISO 9001:2008 certifica
"Emblogic.com" is the best education center in India to assist you about serial port device driver and their development as well. To know more about these kind of training program, visit our professional website.
International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research (IJCER) is dedicated to protecting personal information and will make every reasonable effort to handle collected information appropriately. All information collected, as well as related requests, will be handled as carefully and efficiently as possible in accordance with IJCER standards for integrity and objectivity.
• UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
• UART is a device that has the capability to both receive and transmit serial data.
• A universal asynchronous receiver-transmitter is a computer hardware device for asynchronous serial communication in which the data format and transmission speeds are configurable.
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Achieving Reduced Area and Power with Multi Bit Flip-Flop When Implemented In...IJERA Editor
A UART (Universal Asynchronous Receiver and Transmitter) is a device allowing the reception and transmission of information, in a serial and asynchronous way. This project focuses on the implementation of UART with status register using multi bit flip-flop and comparing it with UART with status register using single bit flip-flops. During the reception of data, status register indicates parity error, framing error, overrun error and break error. The multi bit flip-flop is indicated in this status register. In modern very large scale integrated circuits, Power reduction and area reduction has become a vital design goal for sophisticated design applications. So in this project the power consumed and area occupied by both multi-bit flip-flop and single bit flip is compared. The underlying idea behind multi-bit flip-flop method is to eliminate total inverter number by sharing the inverters in the flip-flops. Based on the elimination feature of redundant inverters in merging single bit flip-flops into multi bit flip-flops, gives reduction of wired length and this result in reduction of power consumption and area.
SEASONAL VARIATION IN PHYSICO-CHEMICAL PARAMETERS OF SURFACE WATER AND GROUND...Ijrdt Journal
The present study is carried out to assess the water quality parameters of both surface water and ground water of Singanallur lake region a rivulet from river Noyyal. Parameters like pH, FC, DO, BOD, Turbidity, Total phosphates, Nitrates and Total dissolved solids are measured and compared for both summer and rainy season. Results revealed parameters varied to greater extent for surface water compared to ground water. So the surface water of Singanallur region is highly polluted due to runoff from industries, domestic waste and agricultural
Numerical modeling and analysis of slabsIjrdt Journal
This paper presents numerical modelling of slabs, linear modelling and analyzing of two way slab in a finite element based programming software ATENA and comparing with SAP for accuracy, The difference in result came to 14.3% hence, tolerable. Considering this, further nonlinear modelling and analysis is done in ATENA for one way and two way rectangular slabs, which includes both material and geometric modelling.Flexural load is applied for analysis of one way and two way slab. The displacement contour and crack pattern of slabs is presented which shows the appropriate behavior of slabs.
Literature review on need of composite additives for s.i engineIjrdt Journal
One of the major drawbacks of IC engines is low efficiency and pollution resulting from incomplete combustion. In order to improve the emission properties and performance an additive is blended with gasoline. The main objective of this paper was preparation of premium gasoline. The paper do literature study on effect of different additive on engine performance and emission. Through the study of literature survey, effect of different additives has been studied, it is found that different additive had some negative effect when used individually which conclude that there is need for new composite additives having better performance in respect of engine performance and emission control.
A mobile agent based approach for data management to support 3 d emergency pr...Ijrdt Journal
In present-day, technology is moving towards Mobile Ad-hoc Networks (MANET), which creates temporary network in environments that have no previous network infrastructure. 3D Mobile Collaborative Virtual Environments (3D MCVEs) to support emergency preparedness scenario such as security sensitive operations (firefighter, biological attacks ) and military training, have made a considerable impact on both commercial and academic fields over the last few years. In such systems, users will share a 3D virtual environment through their mobile devices in order to accomplish specific missions. Effective data management is vital due to the massive amount of data that need to be exchanged and displayed. When the mobile devices resource capabilities are smaller than the 3D virtual environment, we need an efficient approach to maintain and manage active data in the device memory. Traditional data management schemas become inadequate when applied in mobile environment, because it is important to guarantee the existence of the VE even when many users leave suddenly the virtual environment with critical data such as (3D geometric data, score credits etc...). To meet this challenge, we propose a novel approach using decision-based mobile agent that enables nodes to autonomously make intelligent decision about data computation and node state in the network. The resulting approach limits the damage of application interest and offers a realistic virtual environment. We also provide an example of how this approach can be implemented in a real-life emergency preparedness scenario.
Segmentation of medical images using metric topology – a region growing approachIjrdt Journal
A metric topological approach to the region growing based segmentation is presented in this article. Region based growing techniques has gained a significant importance in the medical image processing field for finest of segregation of tumor detected part in the image. Conventional algorithms were concentrated on segmentation at the coarser level which failed to produce enough evidence for the validity of the algorithm. In this article a novel technique is proposed based on metric topological neighbourhood also with the introduction of new objective measure entropy, apart from the traditional validity measures of Accuracy, PSNR and MSE. This measure is introduced to prove the amount of information lost after segmentation is reduced to greater extent which elucidates the effectiveness of the algorithm. This algorithm is tested on the well known benchmarking of testing in ground truth images in par with the proposed region based growing segmented images. The results validated show the validation of effectiveness of the algorithm.
Large scale grid amalgamation of renewable energy sources in indian power systemIjrdt Journal
Renewable energy sources integrated to utility grid always depends on the rate of power generation. Large scale power generations are connected to transmission systems where as small scale distributed power generation is connected to distribution systems. There are certain challenges and issues in the integration of both types of systems directly.
The plans for the development of electricity from renewable energy sources cause three major challenges. Firstly, renewable change the geographical distribution of generation centres compared to the load centres. Secondly, a share of the renewable will be connected to distribution grids and will thus change the vertical distribution of generation. Thirdly, wind and solar energy are two dominant technologies which depend directly on the natural supply of renewable energy and thus are variable and intermittent energy sources. This report addresses the most relevant measures which can be taken in order to deal with these challenges. This paper presents a review in the issues, challenges, causes, impacts and utilization of renewable energy sources Grid Integration.
Thickener waste management in mineral processing to prevent environmental pol...Ijrdt Journal
Water plays a vital role in mineral processing and about 2-3 tons of water is used for the treatment of one ton of ore. The objective of water recovery in thickener is to increase the solids concentration at the underflow to obtain clear water at the overflow. The particle size distribution, that follows the Rosin- Rammler equation, is considered as the most important factors affecting thickener choosing and waste water treatment. If solids below 200mesh include 8% or more of weight of feed, flocculant should be used to increase the sedimentation rate and the water clarity. Increasing the concentration of solids in the feed (up to 25 wt %) reduces the size and cost of the equipments required for separating. If a high concentration of solids in the feed is used with flocculant, thickener overflow can dilute feed and can increase sedimentation rate and clarity. An extra depth should be added to thickener depth due to the space lost by the turbulence of the fluid resistance force.
Multi turbine micro hydro power generationIjrdt Journal
Increase in human population has increased the demand for energy. Fossil fuels are the major source to meet the world energy requirements, but its rapidly dwindling supply and its adverse effects on our ecological system are of major concern. In India over 70 % of the electricity generated is from coal based power plants. Other renewable such as wind, geothermal, solar, and hydroelectricity represent a 2% share of the Indian fuel mix. Fossil fuels (coal) are a major source of power production in India. Our concept features the run of river active setup of micro hydro power generation using simple gear mechanism. This concept is based on the collection of mechanical energy from two rotors spinning by the effect of higher river velocity and transmission of power from the rotors to a small pinion gear which runs the generator shaft, through two large driver gears attached to the shafts of two rotors. This method of power production is comparatively simpler than others. The objectives of our project include low cost, higher output, environment friendly power production, multiple setups in one row, and decrease the power shortage in India.
Enhancement of heat transfer in tube in-tube heat exchangers using twisted in...Ijrdt Journal
Heat exchangers have several industrial and engineering applications. There are different methods to enhance heat transfer in heat exchangers. Passive technique of heat transfer is the most economical and best suited one. The role of inserts in internal forced convection has been widely acknowledged as a passive device in the heat transfer enhancement. One of such technique is introduction of twisted inserts which enhances the heat transfer coefficient. Twisted aluminium inserts when placed in the path of the fluid flow, creates a high degree of turbulence resulting in an increase in the heat transfer rate. By placing inserts, it is expected that the benefits due to the increased heat transfer coefficient overcome the higher cost involved because of the increased frictional losses. The work mainly focuses on increasing the heat transfer of tube-in-tube heat exchangers by using twisted aluminium inserts. The results obtained from the tube with twisted aluminium insert are compared with those without twisted insert using standard properties of heat transfer (LMTD & Effectiveness). The relations based on the data gathered during this work for predicting the heat transfer coefficient of the horizontal pipe with twisted taped insert are proposed. According to the results, in order to obtain maximum heat transfer, the twist ratio must be at the lowest level.
Improvement of signal coverage using wcdma signal repeater for 3 g systemsIjrdt Journal
Wireless communication has become an indispensable technology for the society. In broadband wireless data transmission technique, 3G cellular systems are expected to provide high data rate and less probability of error. This repeater finds application in areas of poor signal coverage and connectivity. The repeater consists of a patch panel antenna for receiving WCDMA signals from the base station and amplifying the signals using a wideband RF amplifier. The signals are then retransmitted to the weak coverage area using a directional Yagi-Uda antenna. The antenna characteristics such as return loss and VSWR are measured using a Network analyzer. The component of the repeater are mounted in a stand and the performance of the entire unit was evaluated using a WCDMA generator, act as a base station, transmitting at 869 MHz and 5dBm output power. A spectrum analyzer with WCDMA analyzer is used as a receiver, the RF signal level and constellation plots with error vector magnitude are determined
Final project report on grocery store management system..pdfKamal Acharya
In today’s fast-changing business environment, it’s extremely important to be able to respond to client needs in the most effective and timely manner. If your customers wish to see your business online and have instant access to your products or services.
Online Grocery Store is an e-commerce website, which retails various grocery products. This project allows viewing various products available enables registered users to purchase desired products instantly using Paytm, UPI payment processor (Instant Pay) and also can place order by using Cash on Delivery (Pay Later) option. This project provides an easy access to Administrators and Managers to view orders placed using Pay Later and Instant Pay options.
In order to develop an e-commerce website, a number of Technologies must be studied and understood. These include multi-tiered architecture, server and client-side scripting techniques, implementation technologies, programming language (such as PHP, HTML, CSS, JavaScript) and MySQL relational databases. This is a project with the objective to develop a basic website where a consumer is provided with a shopping cart website and also to know about the technologies used to develop such a website.
This document will discuss each of the underlying technologies to create and implement an e- commerce website.
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdffxintegritypublishin
Advancements in technology unveil a myriad of electrical and electronic breakthroughs geared towards efficiently harnessing limited resources to meet human energy demands. The optimization of hybrid solar PV panels and pumped hydro energy supply systems plays a pivotal role in utilizing natural resources effectively. This initiative not only benefits humanity but also fosters environmental sustainability. The study investigated the design optimization of these hybrid systems, focusing on understanding solar radiation patterns, identifying geographical influences on solar radiation, formulating a mathematical model for system optimization, and determining the optimal configuration of PV panels and pumped hydro storage. Through a comparative analysis approach and eight weeks of data collection, the study addressed key research questions related to solar radiation patterns and optimal system design. The findings highlighted regions with heightened solar radiation levels, showcasing substantial potential for power generation and emphasizing the system's efficiency. Optimizing system design significantly boosted power generation, promoted renewable energy utilization, and enhanced energy storage capacity. The study underscored the benefits of optimizing hybrid solar PV panels and pumped hydro energy supply systems for sustainable energy usage. Optimizing the design of solar PV panels and pumped hydro energy supply systems as examined across diverse climatic conditions in a developing country, not only enhances power generation but also improves the integration of renewable energy sources and boosts energy storage capacities, particularly beneficial for less economically prosperous regions. Additionally, the study provides valuable insights for advancing energy research in economically viable areas. Recommendations included conducting site-specific assessments, utilizing advanced modeling tools, implementing regular maintenance protocols, and enhancing communication among system components.
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Immunizing Image Classifiers Against Localized Adversary Attacksgerogepatton
This paper addresses the vulnerability of deep learning models, particularly convolutional neural networks
(CNN)s, to adversarial attacks and presents a proactive training technique designed to counter them. We
introduce a novel volumization algorithm, which transforms 2D images into 3D volumetric representations.
When combined with 3D convolution and deep curriculum learning optimization (CLO), itsignificantly improves
the immunity of models against localized universal attacks by up to 40%. We evaluate our proposed approach
using contemporary CNN architectures and the modified Canadian Institute for Advanced Research (CIFAR-10
and CIFAR-100) and ImageNet Large Scale Visual Recognition Challenge (ILSVRC12) datasets, showcasing
accuracy improvements over previous techniques. The results indicate that the combination of the volumetric
input and curriculum learning holds significant promise for mitigating adversarial attacks without necessitating
adversary training.
Cosmetic shop management system project report.pdfKamal Acharya
Buying new cosmetic products is difficult. It can even be scary for those who have sensitive skin and are prone to skin trouble. The information needed to alleviate this problem is on the back of each product, but it's thought to interpret those ingredient lists unless you have a background in chemistry.
Instead of buying and hoping for the best, we can use data science to help us predict which products may be good fits for us. It includes various function programs to do the above mentioned tasks.
Data file handling has been effectively used in the program.
The automated cosmetic shop management system should deal with the automation of general workflow and administration process of the shop. The main processes of the system focus on customer's request where the system is able to search the most appropriate products and deliver it to the customers. It should help the employees to quickly identify the list of cosmetic product that have reached the minimum quantity and also keep a track of expired date for each cosmetic product. It should help the employees to find the rack number in which the product is placed.It is also Faster and more efficient way.
Overview of the fundamental roles in Hydropower generation and the components involved in wider Electrical Engineering.
This paper presents the design and construction of hydroelectric dams from the hydrologist’s survey of the valley before construction, all aspects and involved disciplines, fluid dynamics, structural engineering, generation and mains frequency regulation to the very transmission of power through the network in the United Kingdom.
Author: Robbie Edward Sayers
Collaborators and co editors: Charlie Sims and Connor Healey.
(C) 2024 Robbie E. Sayers
Sachpazis:Terzaghi Bearing Capacity Estimation in simple terms with Calculati...Dr.Costas Sachpazis
Terzaghi's soil bearing capacity theory, developed by Karl Terzaghi, is a fundamental principle in geotechnical engineering used to determine the bearing capacity of shallow foundations. This theory provides a method to calculate the ultimate bearing capacity of soil, which is the maximum load per unit area that the soil can support without undergoing shear failure. The Calculation HTML Code included.
Hierarchical Digital Twin of a Naval Power SystemKerry Sado
A hierarchical digital twin of a Naval DC power system has been developed and experimentally verified. Similar to other state-of-the-art digital twins, this technology creates a digital replica of the physical system executed in real-time or faster, which can modify hardware controls. However, its advantage stems from distributing computational efforts by utilizing a hierarchical structure composed of lower-level digital twin blocks and a higher-level system digital twin. Each digital twin block is associated with a physical subsystem of the hardware and communicates with a singular system digital twin, which creates a system-level response. By extracting information from each level of the hierarchy, power system controls of the hardware were reconfigured autonomously. This hierarchical digital twin development offers several advantages over other digital twins, particularly in the field of naval power systems. The hierarchical structure allows for greater computational efficiency and scalability while the ability to autonomously reconfigure hardware controls offers increased flexibility and responsiveness. The hierarchical decomposition and models utilized were well aligned with the physical twin, as indicated by the maximum deviations between the developed digital twin hierarchy and the hardware.
1. International Journal For Research & Development in Technology
Volume: 2, Issue: 1, JULY-2014 ISSN (Online):- 2349-3585
7
Copyright 2014- IJRDT www.ijrdt.org
DESIGN AND IMPLEMENTATION OF UART ON SOC A.Dasthagiraiah1,N.Subramanyam2, E.Supraja3,Dr.H.K.P.Prasad4,K.V.Goutham5 1,2,3,5 Assistant Professors in Priyadarshini Institute Of Technology ,Nellore
4,Pricipal at Priyadarshini Institute Of Technology ,Nellore Abstract – Security is primary concern in our day-to-day life. Everyone wants to be as much as secure as possible. The UART (universal asynchronous receiver and transmitter) module provides asynchronous serial communication with external devices such as modems and other computers. The UART can be used to control the process of breaking parallel data from the PC down into serial data that can be transmitted and vice versa for receiving data. The UART allows the devices to communicate without the need to be synchronized. UART is a popular method of serial asynchronous communication. Typically, the UART is connected between a processor and a peripheral. To the processor, the UART appears as an 8-bit read-write parallel port that performs serial-to-parallel conversions for the processor, and vice versa for the peripheral. With the implementation of UART the serial communication is done in high data rate and no interrupts. Baud rate generator provides high data rate and interrupt controller handles all the interrupts. The UART serial communication interface device receives data and converts data from serial to parallel, where as the transmitter performs parallel to serial conversion. Key word:- SOC,UART I.INTRODUCTION The UART (universal asynchronous receiver and transmitter) module provides asynchronous serial communication with external devices such as modems and other computers. The UART can be used to control the process of breaking parallel data from the PC down into serial data that can be transmitted and vice versa for receiving data. The UART allows the devices to communicate without the need to be synchronized. UART is a popular method of serial asynchronous communication. Typically, the UART is connected between a processor and a peripheral. To the processor, the UART appears as an 8-bit read-write parallel port that performs serial- to-parallel conversions for the processor, and vice versa for the peripheral. The UART allows reliable data transfer at high speeds with its 16-byte first in, first out (FIFO) input register. The FIFO feature can buffer up to 16 bytes at a time, which improves serial communications by preventing data overruns in applications. The implementation of UART the serial communication is done with high data rate and no interrupts. The UART 16550 serial communication interface device
receives data and converts data from serial to parallel, where as the transmitter performs parallel to serial conversion. This thesis portrays a novel architecture of Universal Asynchronous Receiver Transmitter. UARTs are used for asynchronous serial data communication between remote embedded systems. The UART is for interfacing computers or microprocessors to an asynchronous serial data channel. The receiver converts serial start, data, parity and stop bits. The transmitter converts parallel data into serial form and automatically adds start, parity and stop bits. The data word length can be 5, 6, 7 or 8 bits. Parity may be odd or even. Parity checking and generation can be inhibited. The stop bits may be one or two or one and one-half when transmitting 5-bit code. The UART can be used in a wide range of applications including modems, printers, peripherals and remote data acquisition systems. Utilizing the advanced scaled SAJI IV CMOS process permits operation clock frequencies up to 8.0MHz (500K Baud). Power requirements, by comparison, are reduced from 300mW to 10mW. Status logic increases flexibility and simplifies the user interface. The basic application of UART is shown in Figure 1.1.
Figure 1.1 Basic Application of UART This design can also be instantiated many times to get multiple UARTs in the same device. For easily embedding the design into a larger implementation, instead of using tri-state buffers, the bi-directional data bus is separated into two buses, DIN and DOUT. The transmitter and receiver both share a common internal Clk16X clock. This internal clock which needs to be 16 times of the desired baud rate clock frequency is obtained from the on-board clock through the MCLK input directly.
2. International Journal For Research & Development in Technology
Paper Title:- DESIGN AND IMPLEMENTATION OF UART ON SOC (Vol.2,Issue-1) ISSN(O):- 2349-3585
8
Copyright 2014- IJRDT www.ijrdt.org
1.1 SYNCHRONOUS SERIAL TRANSMISSION Synchronous serial transmission requires that the sender and receiver share a clock with one another, or that the sender provide a strobe or other timing signal so that the receiver knows when to “read” the next bit of the data. In most forms of serial Synchronous communication, if there is no data available at a given instant to transmit, a fill character must be sent instead so that data is always being transmitted. Synchronous communication is usually more efficient because only data bits are transmitted between sender and receiver, and synchronous communication can be more costly if extra wiring and circuits are required to share a clock signal between the sender and receiver. A form of Synchronous transmission is used with printers and fixed disk devices in that the data is sent on one set of wires while a clock or strobe is sent on a different wire. Printers and fixed disk devices are not normally serial devices because most fixed disk interface standards send an entire word of data for each clock or strobe signal by using a separate wire for each bit of the word. In the PC industry, these are known as Parallel devices.
1.2 ASYNCHRONOUS SERIAL TRANSMISSION Asynchronous transmission allows data to be transmitted without the sender having to send a clock signal to the receiver. Instead, the sender and receiver must agree on timing parameters in advance and special bits are added to each word which are used to synchronize the sending and receiving units. When a word is given to the UART for Asynchronous transmissions, a bit called the "Start Bit" is added to the beginning of each word that is to be transmitted. The Start Bit is used to alert the receiver that a word of data is about to be sent, and to force the clock in the receiver into synchronization with the clock in the transmitter. These two clocks must be accurate enough to not have the frequency drift by more than 10% during the transmission of the remaining bits in the word. (This requirement was set in the days of mechanical tele-printers and is easily met by modern electronic equipment.) After the Start Bit, the individual bits of the word of data are sent, with the Least Significant Bit (LSB) being sent first. Each bit in the transmission is transmitted for exactly the same amount of time as all of the other bits, and the receiver “looks” at the wire at approximately halfway through the period assigned to each bit to determine if the bit is a 1 or a 0. For example, if it takes two seconds to send each bit, the receiver will examine the signal to determine if it is a 1 or a 0 after one second has passed, then it will wait two seconds and then examine the value of the next bit, and so on. The sender does not know when the receiver has “looked” at the value of the bit. The sender only knows when the clock says to begin transmitting the next bit of the word. When the entire data word has been sent, the transmitter may add a Parity Bit that the transmitter generates. The Parity Bit may be used by the receiver to perform simple error checking. Then at least one Stop Bit is sent by the transmitter.
When the receiver has received all of the bits in the data word, it may check for the Parity Bits (both sender and receiver must agree on whether a Parity Bit is to be used), and then the receiver looks for a Stop Bit. If the Stop Bit does not appear when it is supposed to, the UART considers the entire word to be garbled and will report a Framing Error to the host processor when the data word is read. The usual cause of a Framing Error is that the sender and receiver clocks were not running at the same speed, or that the signal was interrupted. II.BLOCK DIAGRAM OF UART Block diagram of UART is shown in Figure 2.1.
Figure:2.1 Block Diagram of UART 2.1TRANSMITTER A component, uart_tx is designed for transferring data using serial communication. Figure 2.2 shows the block diagram for the module uart_tx, which has clr and clk inputs used to reset and synchronize communication. A byte of data is input using tx_data[7:0]. When ready is asserted the byte of data is transmitted on the TxD output starting with the least significant bit first. After the transmission has completed, the transmit data ready pin, tdre, goes high.
Figure 2.2 Block diagram of Transmitter module Transmission begins with the TxD line transitioning from high to low for one bit time. This leading bit is called the start bit. The bit time depends on the baud rate. Immediately following the start bit, the first data bit, the least significant bit, transferred followed by the next, more significant bit until all eight bits of data have been transferred. Each bit remains on the TxD line for one bit time. After the most significant bit has been transferred, TxD goes high for one bit time. This trailing bit is called the stop bit. The state diagram for transmitting serial data is shown in Figure. 2.3
3. International Journal For Research & Development in Technology
Paper Title:- DESIGN AND IMPLEMENTATION OF UART ON SOC (Vol.2,Issue-1) ISSN(O):- 2349-3585
9
Copyright 2014- IJRDT www.ijrdt.org
. Figure 2.3 State diagram of UART transmitter The state machine starts in the mark state until the ready signal goes high. This state resets a signal for counting the number of bits transmitted, bit_count, to zero and asserts the tdre output high indicating that the component is not currently transmitting data. When the ready input goes high the state machine transitions to the start state for transmitting the start bit. Since the start bit is a logic low, TxD is set to zero, and must be held low for one bit time. A counter baud_count is used to count clock cycles until the bit time is reached, baud_count is reset to zero in start and tdre is brought low indicating that a transmission is in progress. On the rising edge of the clock, the next state is delay. The bit time counter, baud_count is incremented in the delay state and the state machine remains in the delay state while the baud_count is less than the bit_time. Bit_time is a constant number of cycles required for 0.104 milliseconds to Pass. Once the baud_count has counted up to a bit_time, execution continues to the shift state to transfer a data bit. The byte to transferred is stored in a buffer signal,txbuff[7:0]. In this case, the first data bit or least significant bit of the buffer, txbuff[0], is assigned to TxD in the shift state. Additionally, tdre remains low, txbuff is shifted one bit to the right, bit_count is incremented to count the number of bits transmitted, and baud_count is reset to zero. By shifting txbuff one bit to the right, txbuff[0] always contains the next bit to be transferred until all the eight bits have been transferred. On the next rising edge of the clock, the state machine transitions back to delay. Once again, baud_count is increment on each rising clock edge remaining in delay until one bit time has passed, when baud_count becomes equal to bit_time. Execution continues to shift, outputting the next bit and shifting the transfer buffer, txbuff. After TxD has been set to the next data bit in the shift state, the output remains the same while the state machine remains in the delay state for one bit time. Using a 25MHz clock to drive uart_tx, the bit_time is computed as follows. 25x106x0.104x10-3=2600(0xA28 in hex) Parameters involved: Baud_count: A counter parameter that increments at every positive edge of clock. Bit_time: The time for which each data bit must stay on the line. Bit_count: A parameter that keeps count of the no. of bits transmitted.
2.2 RECEIVER MODULE Receiving data is similar to transmitting data. Figure 2.4 shows the block diagram of the receiver. Eight bits of asynchronous data are input into RxD. Bits are shifted into the 8-bit shift register, rx_data[7:0], least-significant bit first. When rx_data[7:0] is full, the received-data ready flag rdrf, is set to 0 to signify that rx_data[7:0] contains a complete byte. The output rdrf is set to 0 by setting rdrf_clr to high. The framing error flag, FE, is set to 1 if the stop bit is not 1. This is one indication that the data on rx_data[7:0] may not be accurate. Fig shows the state diagram for the serial receiver.The state diagram in Figure 2.5 has the same states as the state machine developed for transmitting data. The transitions between these states are also the same. There is, however, one subtle, important difference. Instead of remaining in the start state for a whole bit time, the state machine transitions to the delay state after a half-bit time. Bit time is determined by the baud rate in the same way it was used in the transmitter.
Figure 2.4 Block diagram of Receiver module
Figure 2.5 State diagram of UART receiver Figure 2.6 illustrates the difference in timing between serially transmitting and receiving 8 bits of data.
4. International Journal For Research & Development in Technology
Paper Title:- DESIGN AND IMPLEMENTATION OF UART ON SOC (Vol.2,Issue-1) ISSN(O):- 2349-3585
10
Copyright 2014- IJRDT www.ijrdt.org
Figure 2.6 Timing differences between transmitting and receiving As stated earlier , the parameters used in design of an Rx module remains the same. A new parameter namely „half_bit_time‟ which represents half of the bit time. Due to the delay in transmission of data , the start bit appears only after half the bit time has elapsed. During transmission, the start bit is transmitted for an entire bit time just like the data bits and the stop bit. When receiving, by waiting only a half bit time after the start bit has been initiated, the data shifted into the shift register during the shift state is farthest away from the time the signal changes. That is, half way between the beginning and the ending time during which the bit is valid. The state diagram in Figure 2.5 starts in the mark state. The state resets a signal for counting the number of bits transmitted, bit_count, to zero and asserts the rdrf output low indicating that the data in rx_data[7:0] is not complete. When RxD goes low, signifying a start bit, the state diagram transitions to the start state it remains in the start state for one- half of a bit time, then transitions to the delay state. The bit time counter, baud_count is incremented in the delay state and the state diagram remains in the delay state while the baud_count is less than the bit_time. III.DEVELOPMENT OF CODE FOR UART IN ARDUINO The other end of the SOC model is an embedded core. In this project it is taken as an ARDUINO controller. Arduino is an open source single board microcontroller, descendant of the open source wiring platform, designed to make the process of using electronics in multidisciplinary projects more accessible. The hardware consists of a simple open hardware design for the Arduino board with an Atmel AVR processor and on-board input/output support. The software consists of a standard programming language compiler and the boot loader that runs on the board.The code dumped into the microcontroller performs to and fro serial communication from the board. The algorithm for the corresponding code is given below:
START
INITIALIZE LCD
READ_DATA (INPUT_PIN)
PRINT_LCD(INPUT_PIN)
WRITE_DATA(INPUT_PIN)
STOP
3.1 FPGA IMPLEMENTATION FLOW DIAGRAM
Figure 4.1 Flow chart for FPGA Flow chart for FPGA is shown Figure 4.1. Initially the market research should be carried out which covers the previous version of the design and the current requirements on the design. Based on this survey, the specification and the architecture must be identified. Then the RTL modeling should be carried out in VHDL with respect to the identified architecture. Once the RTL modeling is done, it should be simulated and verified for all the cases. The functional verification should meet the intended architecture and should pass all the test cases. Once the functional verification is clear, the RTL model will be taken to the synthesis process. Three operations will be carried out in the synthesis process such as
Translate
Map
Place and Route
The developed RTL model will be translated to the mathematical equation format which will be in the understandable format of the tool. These translated equations will be then mapped to the library that is, mapped to the hardware. Once the mapping is done, the gates were placed and routed. Before these processes, the constraints can be given in order to optimize the design. Finally the BIT MAP file will be generated that has the design information in the binary format which will be dumped in the FPGA board. 3.2 SIMULATION RESULT OF UART Figure 5.1 shows the simulation result of UART top level module. UART top module contains both transmitter module and receiver module..
5. International Journal For Research & Development in Technology
Paper Title:- DESIGN AND IMPLEMENTATION OF UART ON SOC (Vol.2,Issue-1) ISSN(O):- 2349-3585
11
Copyright 2014- IJRDT www.ijrdt.org
3.3 HARDWARE RESULT: COMMUNICATION BETWEEN TWO PROCESSORS USING UART PROTOCOL
Figure . Communication between FPGA based processor and Embedded processor IV.FUTURE SCOPE By using UART protocol we can communicate between only two processors. Hence to avoid this limitation we have introduced Modus protocol to operate various devices at a time. REFERENCE
[1] "Universal asynchronous receiver/transmitter", located on: http://en.wikipedia.org/wiki/Universal_asynchronous_receiver/transmitter [2] "Developing Multifunctional Serial-Parallel Data Communication Interface for PC-Based Control System", locatedon:http://journal.uii.ac.id/index.php/Snati/article/viewFile/1583/1358 [3] "Verilog design of input/output processor with
built-in-self-test",locatedon: http://eprints.utm.my/5959/1/GohKengHooMFKE2007TTT.pdf [4] "Embedded Monitoring Server", located on: http://www.doria.fi/bitstream/handle/10024/29686/nbnfi- fe20071990.pdf?sequence=1 [5] "AND THE COMMITTEE ON GRADUATE STUDIES", located on:
http://eil.stanford.edu/publications/yang_wang/yw_thesis.pdf [6] "Computer numerical controlled drilling machine interfaced to a computer aided design package", located on: http://dk.cput.ac.za/cgi/viewcontent.cgi?article=1058&context=td_ptech
Mr. A.Dasthagiraiah- He completed his Master of Technology in Electronics and communication Engineering from Hindustan University in the year 2011 with specialization in Embedded Systems. He has given guidance to many students in their thesis work of M.Tech. He has also contributed in the research work on Embedded Systems with his papers. He has four years teaching Experience and presently working as Asst. Professor in Priyadarshini Institute of Technology,SPSR Nellore. He has done Bachelor's of Technology from JNTUA University in the year 2009 in Electronics and Communication Engineering Mr. N.Subramanyam- He completed his Master of Technology in Electronics and communication Engineering from JNTUA in the year 2011 with specialization in Embedded Systems. He has given guidance to many students in their thesis work of M.Tech. He has also contributed in the research work on Embedded Systems with his papers. He has four years teaching Experience and presently working as Asst. Professor in Priyadarshini Institute of Technology,SPSR Nellore. He has done Bachelor's of Technology from ANNA University in the year 2009 in Electronics and Communication Engineering Mr. K.V.Goutham- He completed his Master of Technology in Electronics and communication
6. International Journal For Research & Development in Technology
Paper Title:- DESIGN AND IMPLEMENTATION OF UART ON SOC (Vol.2,Issue-1) ISSN(O):- 2349-3585
12
Copyright 2014- IJRDT www.ijrdt.org
Engineering from JNTUA in the year 2012 with specialization in Embedded Systems. He has given guidance to many students in their thesis work of M.Tech. He has also contributed in the research work on Embedded Systems with his papers. He has four years teaching Experience and presently working as Asst. Professor in Priyadarshini Institute of Technology,SPSR Nellore. He has done Bachelor's of Technology from JNTUA University in the year 2010 in Electronics and Communication Engineering
Mrs. E.Supraja:- She completed her Master of Technology in Electronics and communication Engineering fromPBRVITS,Kavali in the year 2013 with specialization in VLSI Systems. She has given guidance to many students in their thesis work of M.Tech She has 6 years teaching Experience and presently working as Asst. Professor in Priyadarshini Institute of Technology,SPSR Nellore. She has done Bachelor's of Technology from JNTUA University in the year 2006 in Electronics and Communication Engineering.