CMOS is a combination of NMOS and PMOS transistors used to manufacture analog and digital circuits. It has low power consumption and is highly immune to noise. CMOS fabrication involves growing wells and gates, and diffusing sources and drains. CMOS circuits use both NMOS and PMOS transistors arranged so that one is on and the other is off for any input, allowing logic functions with very low power use. It is widely used to manufacture microprocessors, memory chips, and other digital circuits.

1. CMOS
BY
A.SRIHARI
M.TECH(1-YEAR)
ECE DEPT
PONDICHERRY UNIVERSITY

2. CMOS
✶ It is defined as complementary metal oxide semiconductor
✶ CMOS is a combination of NMOS AND PMOS
✶ They are used to manufacture analog and digital circuits
✶ EXAMPLE:microprocessors and RF circuits

4. characteristics of CMOS
✶ They are highly immune to noise
✶ Power consumption is less
✶ This device does not produce much heat
✶ Wide range of logical operations can be performed

5. FABRICATION OF CMOS
✶ Fabrication of CMOS transistors as IC’s can be done in three
different methods.
✶ The N-well / P-well technology
✶ The Twin well technology
✶ The silicon On Insulator process

6. N- well/ P- well Technology
✶ CMOS using N well
✶ Step 1: First we choose a substrate as a base for
fabrication. For N- well, a P-type silicon substrate is
selected.

7. OXIDATION
✶ The selective diffusion of n-type impurities is accomplished
using SiO2 as a barrier which protects portions of the wafer
against contamination of the substrate. SiO2 is laid out by
oxidation process done exposing the substrate to high-quality
oxygen and hydrogen in an oxidation chamber at
approximately 10000c

8. Growing of Photoresist
✶ At this stage to permit the selective etching, the SiO2 layer is
subjected to the photolithography process. In this process, the
wafer is coated with a uniform film of a photosensitive
emulsion.

9. Masking
✶ This step is the continuation of the photolithography process. In
this step, a desired pattern of openness is made using a
stencil. This stencil is used as a mask over the photoresist. The
substrate is now exposed to UV rays the photoresist present
under the exposed regions of mask gets polymerized.

10. REMOVAL OF PHOTORESIST
✶ he mask is removed and the unexposed region of photoresist is
dissolved by developing wafer using a chemical such as
Trichloroethylene.

11. Etching
✶ The wafer is immersed in an etching solution of hydrofluoric
acid, which removes the oxide from the areas through which
dopants are to be diffused.

12. Removal of Whole Photoresist
Layer
✶ During the etching process, those portions of SiO2 which are
protected by the photoresist layer are not affected. The
photoresist mask is now stripped off with a chemical solvent
(hot H2SO4).

13. Formation of N-well
✶ The n-type impurities are diffused into the p-type substrate
through the exposed region thus forming an N- well.

14. Removal of SiO2
✶ The layer of SiO2 is now removed by using hydrofluoric acid.

15. Deposition of Polysilicon
✶ The misalignment of the gate of a CMOS transistor would lead
to the unwanted capacitance which could harm circuit. So to
prevent this “Self-aligned gate process” is preferred where gate
regions are formed before the formation of source and drain
using ion implantation.

16. Formation of Gate Region
✶ Except the two regions required for formation of the gate
for NMOS and PMOS transistors the remaining portion of
Polysilicon is stripped off.

17. Masking and Diffusion
✶ making regions for diffusion of n-type impurities using masking
process small gaps are made.

18. Removal of Oxide and P-type
Diffusion

19. Laying of Thick Field oxide
✶ Before forming the metal terminals a thick field oxide is laid out
to form a protective layer for the regions of the wafer where no
terminals are required.

20. Metallization
✶ This step is used for the formation of metal terminals which can
provide interconnections. Aluminum is spread on the whole
wafer

21. Formation of Terminals

22. Assigning the Terminal Names
✶ Names are assigned to the terminals of NMOS and PMOS
transistors.

23. CMOS IC Layout
✶ consider a 1-in-square wafer divided into 400 chips of surface
area 50 mil by 50 mils. It takes an area of 50 mil2 to fabricate a
transistor. Hence each IC contains 2 transistors thus there are
2 x 400 = 800 transistors built on each wafer. If 10 wafers are
processed each batch then 8000 transistors can be
manufactured simultaneously

24. Twin Tube Fabrication of CMOS
✶ A lightly doped n or p-type substrate is taken and the epitaxial
layer is used. Epitaxial layer protects the latch-up problem in the
chip
✶ The high purity silicon layers with measured thickness and exact
dopant concentration are grown.Formation of tubes for P and N
well
✶ Thin oxide construction for protection from contamination during
diffusion processes
✶ Source and drain are formed using ion implantation methods.
✶ Cuts are made for making portions for metal contacts.
✶ Metallization is done for drawing metal contacts

25. Working Principle
✶ In CMOS technology, both N-type and P-type transistors are used to design
logic functions. The same signal which turns ON a transistor of one type is
used to turn OFF a transistor of the other type. This characteristic allows the
design of logic devices using only simple switches, without the need for a
pull-up resistor.
✶ In CMOS logic gates a collection of n-type MOSFETs is arranged in a pull-
down network between the output and the low voltage power supply rail
(Vss or quite often ground). Instead of the load resistor of NMOS logic
gates, CMOS logic gates have a collection of p-type MOSFETs in a pull-up
network between the output and the higher-voltage rail (often named
Vdd).Thus, if both a p-type and n-type transistor have their gates connected
to the same input, the p-type MOSFET will be ON when the n-type
MOSFET is OFF, and vice-versa. The networks are arranged such that one
is ON and the other OFF for any input pattern

26. Advantages
• These gates are very simple
• Input impedance is high
• CMOS logic uses less power whenever it is held in a set state
• Stability of temperature
• Noise immunity is good
• Compact

27. Disadvantages
✶ The cost will be increased once the processing steps increases,
however, it can be resolved.
✶ The packing density of CMOS is low as compared with NMOS.
✶ MOS chips should be secured from getting static charges by
placing the leads shorted otherwise; the static charges obtained
within leads will damage the chip. This problem can be solved by
including protective circuits otherwise devices.
✶ Another drawback of the CMOS inverter is that it utilizes two
transistors as opposed to one NMOS to build an inverter, which
means that the CMOS uses more space over the chip as
compared with the NMOS. These drawbacks are small due to the
progress within the CMOS technology.

28. Applications
✶ Computer memories, CPUs
✶ Microprocessor designs
✶ Flash memory chip designing
✶ Used to design application-specific integrated circuits (ASICs)