SlideShare a Scribd company logo
Niek Timmers Albert Spruyt Cristofaro Mune
HARDENING SECURE BOOT ON
EMBEDDED DEVICES FOR
HOSTILE ENVIRONMENTS
niek@riscure.com
@tieknimmers
albert.spruyt@gmail.com c.mune@pulse-sec.com
@pulsoid
WHY THIS TALK?
SOME HISTORY...
2003
2008
2010
2011
2013
2016
2016
2017
2018
Hacking Nintendo
2016 @ 33c3
Secure
Initialization of
TEEs; when
secure boot falls
short @
Euskalhack
Bypassing Secure
Boot using Fault
Injection @ Black
Hat Europe
Nintendo Switch
20 ways past
secure boot @
HITB KUL
Xbox 360 reset
glitch
Console Hacking
2010 @ 27c3
Hacking the
iPhone @ 25c3
Hacking the Xbox
SECURE BOOT IS STILL OFTEN VULNERABLE...
OUR GOAL
Create a Secure Boot guidance for
designers, implementers and integrators.
WHITE PAPER
We are working on it!
"Notes on Designing Secure Boot."
THIS PRESENTATION
Offensive focus
Known and new attacks
New perspectives
AGENDA
Introduction
Secure Boot
Attacks and Mitigations
Demo
Takeaways
GENERIC DEVICE
System-on-a-Chip
SRAM ROM
CPU
Flash DDR
BL1
BL2
...
Device is turned off
GENERIC DEVICE
System-on-a-Chip
SRAM ROM
CPU
Flash DDR
BL1
BL2
...
BL1
ROM code loads BL1 into internal SRAM
GENERIC DEVICE
System-on-a-Chip
SRAM ROM
CPU
Flash DDR
BL1
BL2
...
BL1
BL2
BL1 initializes DDR and loads BL2 into DDR
GENERIC DEVICE
System-on-a-Chip
SRAM ROM
CPU
Flash DDR
BL1
BL2
...
BL1
BL2
...
And then, more is loaded and executed...
TWO MAJOR THREATS...
ATTACKERS
System-on-a-Chip
SRAM ROM
CPU
Flash DDR
BL1
BL2
...
BL1
BL2
Attacker 1: hardware hacker modifies flash
ATTACKERS
System-on-a-Chip
SRAM ROM
CPU
Flash DDR
BL1
BL2
...
BL1
BL2
Attacker 2: (remote) so ware hacker modifies flash
THEREFORE WE NEED SECURE BOOT
SECURE BOOT
Authentication of loaded images
Root of trust embedded in hardware
i.e. immutable code and data (e.g. ROM, OTP)
SECURE BOOT
System-on-a-Chip
SRAM ROM
CPU
Flash DDR
BL1
BL2
...
BL1
ROM has copied BL1 to SRAM
SECURE BOOT
System-on-a-Chip
SRAM ROM
CPU
Flash DDR
BL1
BL2
...
BL1
Signature
Signature
ROM calculates the BL1 hash
SECURE BOOT
System-on-a-Chip
SRAM ROM
CPU
Flash DDR
BL1
BL2
...
BL1
Signature
Signature
ROM compares the hash against the reference from the signature
SECURE BOOT
System-on-a-Chip
SRAM ROM
CPU
Flash DDR
BL1
BL2
...
BL1
BL1 is executed
THE REAL WORLD IS A LITTLE MORE COMPLEX...
SECURE BOOT FLOW
ROM Bootloader
TEE
bootloader
TEE OS
REE
bootloader
REE OS AppsHardware
SECURE BOOT FLOW
ROM Bootloader
TEE
bootloader
TEE OS
REE
bootloader
REE OS Apps
Privileges change/drop during boot.
Hardware
SECURE BOOT FLOW
ROM Bootloader
TEE
bootloader
TEE OS
REE
bootloader
REE OS Apps
Cannot be updated. Can be updated.
Privileges change/drop during boot.
Hardware
SECURE BOOT FLOW
ROM Bootloader
TEE
bootloader
TEE OS
REE
bootloader
REE OS Apps
Cannot be updated. Can be updated.
Manufacturer A Manufacturer B Manufacturer C Manufacturer N
Privileges change/drop during boot.
Hardware
Lots of different interests!
MITIGATING THREATS
Modifying code/data in flash
Insecure updates
Creating a persistent foothold
Access to keys, code and crypto engines
Escalating privileges (e.g. REE to TEE)
ATTACK SURFACE
Broken
design
Broken
implementation
OR
ATTACK SURFACE
Broken
design
Broken
implementation
Broken
software
Broken
hardware
OR OR
WHAT GOES WRONG IN THE FIELD...
Amlogic S905 SoC BootROM vulnerability
Broken
design
Broken
implementation
Broken
software
Broken
hardware
OR OR
Weak
Cryptographic
options
Secure Boot is bypassed, and BootROM is dumped, by downgrading from RSA to SHA
Credit: fredericb
MITIGATIONS:
Do not support weak cryptographic options
Limit the amount of options
Nintendo Switch BootROM vulnerability
Broken
design
Broken
implementation
Broken
software
Broken
hardware
OR OR
Buffer overflow
Buffer overflow in the USB recovery mode
Credit: andfail0verflow Cease & DeSwitch
MITIGATIONS:
Write secure so ware ;)
Make so ware exploitation hard
i.e. stack cookies, ASLR, CFI, etc.
Use memory protections to enforce W^X
e.g. MPU, MMU, IOMMU, etc.
SWITCH FAULT INJECTION
Broken
implementation
Broken
hardware
Broken
Implementation
OR OR
Fault Injection
Broken
software
Broken
design
SKIP HASH VERIFICATION USING VOLTAGE FAULT INJECTION
FAULT INJECTION (FI)
Make glitches with e.g.: EM, light, clock, power, heat
Use a glitch to introduce a fault in a device
Model faults:
Instruction skipping
Instruction/data corruption
FI ALTERS THE INTENDED BEHAVIOR OF HW AND SW
FAULT INJECTION MITIGATIONS
So ware
Redundancy (e.g. double checks)
Random delays
Hardware
Redundancy
Glitch detectors
Clock randomization
Viva La Vita Vida fault injection attack
Broken
implementation
Broken
hardware
Broken
Implementation
OR OR
Fault Injection
Broken
software
Broken
design
Introducing a classic buffer overflow using Voltage Fault Injection
Credit: Yifan Lu and Davee @ 35c3
MITIGATIONS:
It's Fault injection so use FI mitigations
It's So ware exploit so use exploit mitigations
DESIGNING SECURE BOOT AINT EASY!
ESPECIALLY CONSIDERING THE CONSTRAINTS...
Initializing hardware
Interfacing with peripherals
Performance
Code size
Keeping engineering cost low
Recoverability
Customer needs
IT'S IMPORTANT TO GET IT RIGHT
WRONG SECURITY IS EXPENSIVE
Tape out
Crisis management
PR damage
Time to market
Recall of devices/unsold inventory
Additional engineering time
HAS THE WORLD SEEN IT ALL?
FAULT INJECTION ON OTP TRANSFER
Broken
implementation
Broken
hardware
Broken
Implementation
OR OR
Fault Injection
Broken
software
Broken
design
Attacking Secure Boot before any code is executed!
LET'S LOOK AT THIS ONE IN DETAIL
OTP AND SECURE BOOT
ROM Bootloader
TEE
bootloader
TEE OS
REE
bootloader
REE OS Apps
Cannot be updated. Can be updated.
Manufacturer A Manufacturer B Manufacturer C Manufacturer N
Privileges change/drop during boot.
Hardware
ROM code uses values from OTP for enabling/disabling security features.
EXAMPLE
Value stored in shadow registers. Populated by OTP Transfer.
memcpy(I_SRAM, I_FLASH, I_SIZE); // 1. Copy image
memcpy(S_SRAM, S_FLASH, S_SIZE); // 2. Copy signature
if (*(OTP_SHADOW) >> 17 & 0x1) { // 3. Check if enabled
if(SHA256(I_SRAM, I_SIZE, I_HASH)) { // 4. Calculate hash
while(1);
}
if(verify(PUBKEY, S_SRAM, I_HASH)) { // 5. Verify image
while(1);
}
}
jump(); // 6. Jump to next image
POPULATING SHADOW REGISTERS
ROM Bootloader
TEE
bootloader
TEE OS
REE
bootloader
REE OS Apps
Cannot be updated. Can be updated.
Manufacturer A Manufacturer B Manufacturer C Manufacturer N
Privileges change/drop during boot.
Hardware
OTP Transfer performed in hardware. BEFORE any ROM code is executed.
OTP TRANSFER 1/5
System-on-Chip
A typical System-on-Chip (SoC)
OTP TRANSFER 2/5
System-on-Chip
OTP phy
OTP BANK 1
OTP BANK 2
OTP BANK 4
OTP BANK ...
OTP BANK 3
Contains a special OTP hardware block
OTP TRANSFER 3/5
System-on-Chip
OTP phy
OTP BANK 1
OTP BANK 2
OTP BANK 4
OTP BANK ...
OTP BANK 3
OTP
controller
CMD/RSP
Which is wrapped by a hardware controller
OTP TRANSFER 4/5
System-on-Chip
Shadow registersOTP phy
OTP BANK 1
OTP BANK 2
OTP BANK 4
OTP BANK ...
OTP BANK 3
OTP
controller
Register 1
Register 3
Register 2
Register 4
Register ...
CMD/RSP
This controller copies the OTP values to dedicated registers a er SoC reset
OTP TRANSFER 5/5
System-on-Chip
Shadow registersOTP phy
OTP BANK 1
OTP BANK 2
OTP BANK 4
OTP BANK ...
OTP BANK 3
OTP
controller
Register 1
Register 3
Register 2
Register 4
Register ...
CMD/RSP
CPU
BUS
CPU is released from reset. Shadow registers can be read using system bus.
WHERE CAN WE ATTACK?
ANYWHERE!
System-on-Chip
Shadow registersOTP phy
OTP BANK 1
OTP BANK 2
OTP BANK 4
OTP BANK ...
OTP BANK 3
OTP
controller
Register 1
Register 3
Register 2
Register 4
Register ...
CMD/RSP
CPU
BUS
Attack the bus between the OTP PHY and the OTP controller.
ANYWHERE!
System-on-Chip
Shadow registersOTP phy
OTP BANK 1
OTP BANK 2
OTP BANK 4
OTP BANK ...
OTP BANK 3
OTP
controller
Register 1
Register 3
Register 2
Register 4
Register ...
CMD/RSP
CPU
BUS
Attack the OTP controller directly.
ANYWHERE!
System-on-Chip
Shadow registersOTP phy
OTP BANK 1
OTP BANK 2
OTP BANK 4
OTP BANK ...
OTP BANK 3
OTP
controller
Register 1
Register 3
Register 2
Register 4
Register ...
CMD/RSP
CPU
BUS
Attack the bus between the OTP controller and the shadow registers.
WE CAN AFFECT
SIGNATURE VERIFICATION
AND/OR
STAGE ENCRYPTION
BYPASSING
(ENCRYPTED) SECURE BOOT
THAT WAS FUN; LET'S DO ANOTHER ONE!
FAULT INJECTION ON ENCRYPTED SECURE BOOT
Broken
implementation
Broken
hardware
Broken
Implementation
OR OR
Fault Injection
Broken
software
Broken
design
...WITHOUT AN ENCRYPTION KEY!
SIGNATURE VERIFICATION
memcpy(I_SRAM, I_FLASH, I_SIZE); // 1. Copy image
memcpy(S_SRAM, S_FLASH, S_SIZE); // 2. Copy signature
if (*(OTP_SHADOW) >> 17 & 0x1) { // 3. Check if enabled
if(SHA256(I_SRAM, I_SIZE, I_HASH)) { // 4. Calculate hash
while(1);
}
if(verify(PUBKEY, S_SRAM, I_HASH)) { // 5. Verify image
while(1);
}
}
jump(); // 6. Jump to next image
FAULT INJECTION FAULT MODEL
Faults can cause "instruction not to be executed"
Inaccurate but sufficient
Widely adopted (by academia and industry)
Useful for affecting the code flow
"Instruction skipping"
LET'S USE IT FOR BYPASSING SECURE BOOT!
A TEXTBOOK ATTACK 1/3
System-on-a-Chip
SRAM ROM
CPU
Flash DDR
BL1
BL2
...
Device is turned off
A TEXTBOOK ATTACK 2/3
System-on-a-Chip
SRAM ROM
CPU
Flash DDR
Code
BL2
...
Replace BL1 with a malicious image
A TEXTBOOK ATTACK 3/3
Skip verify function call and boot an malicious image
memcpy(I_SRAM, I_FLASH, I_SIZE); // 1. Copy image
memcpy(S_SRAM, S_FLASH, S_SIZE); // 2. Copy signature
if (*(OTP_SHADOW) >> 17 & 0x1) { // 3. Check if enabled
if(SHA256(I_SRAM, I_SIZE, I_HASH)) { // 4. Calculate hash
while(1);
}
if(verify(PUBKEY, S_SRAM, I_HASH)) { // 5. Glitch here!
while(1);
}
}
jump(); // 6. Jump to next image
GLITCH AT THE RIGHT MOMENT AND PROFIT!
WHAT IF BL1 IS ENCRYPTED?
ENCRYPTED SECURE BOOT
The image is decrypted a er it is copied and before it is verified!
memcpy(I_SRAM, I_FLASH, I_SIZE); // 1. Copy image
decrypt(SYM_KEY, I_SRAM, I_SIZE); // NEW: Decrypt image
memcpy(S_SRAM, S_FLASH, S_SIZE); // 2. Copy signature
if (*(OTP_SHADOW) >> 17 & 0x1) { // 3. Check if enabled
if(SHA256(I_SRAM, I_SIZE, I_HASH)) { // 4. Calculate hash
while(1);
}
if(verify(PUBKEY, S_SRAM, I_HASH)) { // 5. Glitch here!
while(1);
}
}
jump(); // 6. Jump to next image
THE MISSING KEY...
Encryption key needed for creating a malicious image
THAT'S WHY...
FI attacks are o en considered infeasible when
encrypted Secure Boot is used.
UNTIL NOW!
FAULT INJECTION FAULT MODEL
Faults can modify instructions
Destination register could be changed
Fairly new application
Great for modifying code and getting control
"Instruction corruption"
BYPASSING ENCRYPTED SECURE BOOT 1/4
System-on-a-Chip
SRAM ROM
CPU
Flash DDR
BL1
BL2
...
Device is turned off.
BYPASSING ENCRYPTED SECURE BOOT 2/4
System-on-a-Chip
SRAM ROM
CPU
Flash DDR
Code
BL2
...
Pointers
Replace encrypted BL1 with plain text code and pointers to SRAM.
BYPASSING ENCRYPTED SECURE BOOT 3/4
System-on-a-Chip
SRAM ROM
CPU
Flash DDR
Code
BL2
...
Pointers
Code
Pointers
Glitch is injected a er code copy and while pointers are being copied.
BYPASSING ENCRYPTED SECURE BOOT 4/4
Glitch during pointers copy to assign a pointer to the program counter (PC).
memcpy(I_SRAM, I_FLASH, I_SIZE); // Glitch here!
decrypt(SYM_KEY, I_SRAM, I_SIZE); // Before decryption
memcpy(S_SRAM, S_FLASH, S_SIZE); // and
if(SHA256(I_SRAM, I_SIZE, I_HASH)) { // before
while(1);
}
if(verify(PUB_KEY, S_SRAM, I_HASH)) { // verification!
while(1);
}
jump(); // CPU will never reach here
RESULTING CODE EXECUTION
Control flow is hijacked. The decryption and verification of the image is bypassed!
memcpy(I_SRAM, I_FLASH, I_SIZE); // Glitch here!
.
.
.
.
.
.
.
.
.
.
.
((void *)())(pointer)();
CONCRETELY SAID...
WE TURN
ENCRYPTED SECURE BOOT
INTO
PLAINTEXT UNPROTECTED BOOT
USING
A SINGLE GLITCH AND NO KEY!
PWN3D!
Timing no so relevant
Full PC control
Bypass any SW FI countermeasure
FAULT INJECTION DEMO
ON ENCRYPTED SECURE BOOT!
Important:
We are attacking a demo implementation!
FAULT INJECTION SETUP
Riscure Spider (Glitcher)
You can use NewAE's too!ChipWhisperer
FAULT INJECTION SETUP
Laptop
Riscure Spider (Glitcher)
USB
You can use NewAE's too!ChipWhisperer
FAULT INJECTION SETUP
Laptop
Riscure Spider (Glitcher)
USB Serial
STM32F4 Development Board
You can use NewAE's too!ChipWhisperer
FAULT INJECTION SETUP
Laptop
Riscure Spider (Glitcher)
USB Serial
STM32F4 Development Board
Voltage
You can use NewAE's too!ChipWhisperer
FAULT INJECTION SETUP
Laptop
Riscure Spider (Glitcher)
USB Serial
STM32F4 Development Board
Voltage
Reset
You can use NewAE's too!ChipWhisperer
REAL WORLD FI SETUP
Even for simple setups there are cables everywhere...
VALID IMAGE
Hardware BL1 BL2
BL1 loads, decrypts and
authenticates BL2 successfully
MALICIOUS IMAGE
Hardware BL1 BL2
BL1 loads, decrypts but
fails to authenticate BL2
FLASH IMAGE MODIFICATION
VALID IMAGE
Hardware BL1 BL2
BL1 loads, decrypts and
authenticates BL2 successfully
MALICIOUS IMAGE
Hardware BL1 BL2
BL1 loads, decrypts but
fails to authenticate BL2
FLASH IMAGE MODIFICATION
TARGET BEHAVIOR
Valid image
Malicious image
Let's bypass it using fault injection!
[BL1]: Successfully started.
[BL1]: Loading BL2 successful.
[BL1]: Decrypting BL2 successful.
[BL1]: Authenticating BL2 successful.
[BL1]: Jumping to BL2...
[BL2]: Successfully started.
[BL1]: Successfully started.
[BL1]: Loading BL2 successful.
[BL1]: Decrypting BL2 successful.
[BL1]: Authenticating BL2 unsuccessful. Stopping!
LET'S SWITCH TO THE OTHER LAPTOP
OSCILLOSCOPE 1/2
We reset the chip for each experiment.
OSCILLOSCOPE 2/2
We inject the glitch during the copy of BL2 by BL1.
FIPY 1/3
Experiments that had no affect on the target are colored green.
FIPY 2/3
Experiments that resulted in a CPU expection are colored magenta.
FIPY 3/3
Experiments that resulted in a successful bypass of secure boot are colored red.
WHAT NOW?
WHITE PAPER
Coming soon!
"Notes on designing secure boot."
HARDENING SECURE BOOT
Keep it simple
Minimize attacker choices
Authenticate everything
No weak crypto
Make so ware exploitation hard
Drop privileges
Make fault injection hard
Support anti-rollback
WHAT ELSE
SECURE SYSTEM/SW DEVELOPMENT LIFE CYCLE
(SECURE SDLC)
Continuous so ware review & testing
Hardware security review & testing
KEY TAKEAWAYS
1. Secure boot is o en not optimally hardened
2. Attack surface of secure boot is larger than expected
3. New perspectives on attacking secure boot
Niek Timmers Albert Spruyt Cristofaro Mune
THANK YOU. QUESTIONS?
niek@riscure.com
@tieknimmers
albert.spruyt@gmail.com c.mune@pulse-sec.com
@pulsoid

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Blue Hat IL 2019 - Hardening Secure Boot on Embedded Devices for Hostile Environments