الإعتيان والتبديل التمثيلي الرقمي

Sampling ‫اإلعتيان‬
‫مست‬ ‫إشارة‬ ‫من‬ ‫زمنيا‬ ‫محددة‬ ‫نقاط‬ ‫عند‬ ‫حقيقية‬ ‫قيم‬ ‫قراءة‬‫مرة‬.
Analog signal
‫تمثيلية‬ ‫إشارة‬
‫زمنيا‬ ‫مستمرة‬
Sample
and
Hold
Sampled signal
‫معتانة‬ ‫إشارة‬
‫زمنيا‬ ‫مقطعة‬
‫القادري‬ ‫منذر‬ ‫محمد‬ ‫المهندس‬ ‫الدكتور‬
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‫اإلشارة‬ ‫وتسجيل‬ ‫اإلعتيان‬
‫الهندسية‬ ‫القياسات‬ ‫في‬,‫المستمرة‬ ‫اإلشارة‬ ‫تسجل‬ ‫ما‬ ‫عادة‬
continuous signal y(t)‫العينات‬ ‫من‬ ‫مجموعة‬ ‫بواسطة‬ys(t)
‫مقطعة‬ ‫زمنية‬ ‫بفواصل‬ttimediscrete intervals of
y(t)
t
yS(t)
t
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‫اإلعتيان‬ ‫تردد‬
Sampling Frequency
‫اإلعتيان‬ ‫تردد‬ ‫يعرف‬fS‫الثانية‬ ‫في‬ ‫اإلشارة‬ ‫من‬ ‫المأخوذة‬ ‫العينات‬ ‫بعدد‬
yS(t)
t
t
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Continuous
Function
f(t)
Sampler
(t)
Series of
samples
T
Reconstruction ?
‫البناء‬ ‫إعادة‬
‫البناء‬ ‫وإعادة‬ ‫اإلعيان‬ ‫عملية‬
Sampling process
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‫المسجلة‬ ‫العينات‬ ‫من‬ ‫األصلية‬ ‫اإلشارة‬ ‫بناء‬ ‫إعادة‬
If a signal is sampled and recorded relative rapidly, the
sampled data will closely resemble the original signal.
Original signal
Sampled signal
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‫اإلشارة‬:‫والرقمية‬ ‫المقطعة‬ ‫و‬ ‫التمثيلية‬
• Analog, x(t)
– Continuous Amplitude
– Continuous Time
• Discrete, x(n)
– Continuous Amplitude
– Discrete Time
• Digital, xq(n)
– Discrete Amplitude
– Discrete Time‫القادري‬ ‫منذر‬ ‫محمد‬ ‫المهندس‬ ‫الدكتور‬
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Sampling and Hold
‫العينة‬ ‫وماسك‬ ‫اإلعيان‬
Almost any analog to digital converter will have some form of
voltage “hold” before sampling. A sampling and hold unit is
used to hold each samples value until the next pulse occurs.
The sample and hold unit is necessary because the analog-to-
digital converter requires a finite amount of time.
y(t)
t
yS(t)
t
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Sampling Schemes
• Impulse Sampling (Theoretical – not implemented in practice)
• Natural Sampling (Theoretical - multiplier is a switch)
• Zero-order hold Sampling (Ideal Sample/Hold -
instantaneous acquisition time is impractical)
• Track/Hold (Real Sample/Hold – Result is sampled and stored in a
memory element)
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‫العينة‬ ‫آخذ‬ ‫مبدأ‬
+
–
“Sample”
“Sample ”input
vavSH
FET
switch
Voltage
follower
(buffer)
C
vSH
Sample-and-hold
amplifier
Functional representation
of FET bilateral switch
Bilateral switch
symbol for FET
“Sample ”input
va
vSH
va
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‫المعتانة‬ ‫المعطيات‬
Sampled data
t0 t1 t2 t3 t4 tn – 1 tn
va (t)
vSH(t)
V(t)
t
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‫المعطيات‬ ‫تحصيل‬ ‫نظام‬ ‫في‬ ‫العينات‬ ‫آخذ‬
Data acquisition system
External
clock
Control
logic
Analog
input
signals
Sample
and
hold
Digital
output
Internal
clock
Trigger
A/D
End of
conversion
Analog multiplexer
V1
V2
V3
V4
Trigger
Amplifier
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‫المعتانة‬ ‫المعطيات‬ ‫إنتخاب‬
Multiplexed sampled data
External clock (sampling signal)
t
A/D
Time available for A/D
t
t
t
t
v 1
v 2
v 3
v 4
A/D
A/D
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‫اإلعتيان‬ ‫في‬ ‫نايكوست‬ ‫نظرية‬
Nyquist Sampling Theorem
A continuous signal can be represented by,
and reconstituted from, a set of sample
values providing that the number of
samples per second is at least twice the
highest frequency presented in the signal.
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So..What Frequency Do I Sample At???
‫المثالي‬ ‫اإلعتيان‬ ‫تردد‬ ‫ماهو‬
• Generally, faster is better, but ...
• Limited by physical constraints
– Switch resistance
– Amplifier settling time
– Required component values
 Rule of thumb:
sample at greater than 10X
signal BW
 minimises sampling effects
(amplitude distortion)
 eases the anti-aliasing filter
requirements (reduced filter
order)
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Over sampling
 Sample faster than needed and use digital filtering
to remove unwanted data is a cost-saving approach.
 Oversampling can improve the data quality when
the signal from the sensing elements is weak and
noisy.
 However, the stream of data produced from
oversampling will generate much more work load
for data analysis.
 An common application in reducing oversampled
data is to remove every nth data point, but it may
cause deterioration in the remaining data.
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Under Sampling
‫المنخفض‬ ‫اإلعتيان‬ ‫تردد‬
‫األصلية‬ ‫اإلشارة‬ ‫على‬ ‫كبير‬ ‫تشوه‬ ‫سيحدث‬ ‫جدا‬ ‫منخفض‬ ‫اإلعيان‬ ‫تردد‬ ‫كان‬ ‫إذا‬,
‫القياس‬ ‫في‬ ‫أخطاء‬ ‫وبالتالي‬
Original signal Sampled data
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Aliasing ‫اإلعتيان‬ ‫خطأ‬
High frequency signal to be sampled by a low sampling rate may
cause to “fold” the sampled data into a false lower frequency signal.
Such folded frequency false signal is often said to be “aliased”
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Antialiasing ‫مرشحات‬
‫نايكوست‬ ‫تردد‬ ‫من‬ ‫األقل‬ ‫الترددات‬ ‫لحذف‬ ‫مرشح‬ ‫إلى‬ ‫بحاجة‬ ‫نحن‬
Analog
signal
Sample
and
Hold
Sampled
signal
Antialiasing
Filter
Not digital devices!!!
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System ‘Purity’ Summary
• Linearity (THD or SFDR)
– Is a measure of how much a system distorts a signal.
• Dynamic Range or Resolution
– is a measure of the largest signal a system can handle, to the smallest that
can be discerned from noise, THD etc.
• Both can be expressed in ‘bits’
– (i.e. how accurate would an A/D converter need to be to achieve the same
linearity or resolution?)
– 8 bit accuracy = 1 in 28 = 0.39% = -48dB
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Sample-Hold ‫عملية‬
• All S/H’s require 4 main components:
– Buffer Amp: buffers source & provides high current gain to charge the hold
capacitor
– Hold Capacitor: Retains the sampled voltage in Hold mode
– Output Buffer: High impedance to keep held voltage from discharging
– Switch & Control: Mechanism by which the hold capacitor is switched from
track to hold
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‫العينات‬ ‫وماسك‬ ‫آخذ‬ ‫دارة‬
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‫خلفية‬ ‫تغذية‬ ‫باستخدام‬ SH ‫دارة‬
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‫الصغيرة‬ ‫لإلشارات‬ ‫عينات‬ ‫آخذ‬ ‫دارة‬
‫مقارن‬ ‫دارئ‬
vi
vo
T1
T2
S
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‫والتبديل‬ ‫التكميم‬ ‫مبادئ‬
1 LSB
0 1/8 2/8 3/8 4/8 5/8 6/8 7/8 Fs
000
001
010
011
100
101
110
111
1/8
2/8
3/8
4/8
5/8
6/8
7/8
8/8
‫التمثيلي‬ ‫الدخل‬
‫الرقمي‬ ‫الخرج‬
Q=LSB=Fs/2n
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‫والتبديل‬ ‫التكميم‬ ‫مبادئ‬
0
0
0
1
0
0
1
0
0
0
1
0
0
1
0
1
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
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‫المطال‬ ‫تكميم‬ ‫تأثير‬
• Quantizer error signal depends on
the input signal dynamic range and
#quantization levels
• With high #levels, the error signal
is modeled as an additive noise
signal with a uniform probability
distribution
• Quantization error signal power is
given by it’s variance














2/
2/
2
2
2/
2/
22
12
1
)( deedeepee
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Unipolar, Linear, Uniform Quantizer
(& Binary Coder)
• “Linear” progression of
quantization steps of “Uniform”
width
• Max. input voltage = Vref
• Quantizer step width, , refers
to the minimum change in input
to change output code by 1,
given by
• ADC DC specs derived from
non-ideal transfer function
m
refV
2

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‫المستمرة‬ ‫اإلشارات‬ ‫تكميم‬
• A digital signal is a sequence of
numbers (samples) in which
each number is represented by a
finite number of digits (finite
resolution)
• The process of converting a
discrete-time continuous-
amplitude signal into a digital
signal is called quantization
• The error introduced in
representing the continuous-
valued signal by a finite set of
discrete values is called
quantization error, or
quantization noise
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Analog/Digital Conversion Interface
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‫الرقمي‬ ‫التمثيلي‬ ‫للتبديل‬ ‫األساسية‬ ‫المراحل‬
• Sampler
– Samples the signal at discrete time intervals
• Quantizer
– Approximates the sampled voltage with a level from a fixed set of 2n possible voltage
levels via ROUNDING or TRUNCATION
• Encoder
– Encodes the measurement in a convenient format for communication or processing
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‫األساسية‬ ‫العملية‬ ‫هو‬ ‫اإلستيفاء‬
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‫نايكوست‬ ‫نظرية‬
• Analog input to sample-and-hold can be precisely
reconstructed from its output, provided that sampling
proceeds at  double of the highest frequency found
in the input voltage (and provided voltages remain
analog). [Nyquist 1928, Shannon, 1949]
Does not capture effect of value quantization:
Quantization noise prevents precise reconstruction.
S/H A/D-converter D/A-converter
= ?
Interpolate
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‫تمثيلي‬ ‫الرقمي‬ ‫المبدل‬
‫المبدل‬
‫ذو‬
‫الموزونة‬ ‫المقاومات‬ ‫شبكة‬
‫المبدل‬
‫ذو‬
‫السلمية‬ ‫المقاومات‬ ‫شبكة‬
D/AC
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








3
0
3
0123
2
842
i
i
i
ref
refrefrefref
x
R
V
R
V
x
R
V
x
R
V
x
R
V
xI
0'1  IRV
'II 





3
0
131
)(
8
2
i
ref
i
iref xnat
R
R
Vx
R
R
VV
Due to Kirchhoff‘s laws:
Due to Kirchhoff‘s laws:
Current into Op-Amp=0:
Finally:
Output voltage  no. represented by x
‫السلمية‬ ‫المقاومات‬ ‫شبكة‬ ‫مبدل‬
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‫الموزونة‬ ‫المقاومات‬ ‫شبكة‬ ‫مبدل‬‫الموزونة‬ ‫التيارات‬
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AD558 ‫للمبدل‬ ‫الداخلية‬ ‫البنية‬
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‫الصغري‬ ‫المعالج‬ ‫مع‬ ‫التمثيلي‬ ‫الرقمي‬ ‫المبدل‬ ‫ربط‬
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Analog-to-Digital Converter Methods of Conversion
Flash
  S
Delta - Sigma
(Over sampling)
Successive Approximation
P-i-p-e-l-i-n-e-d
V to F Converter
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Flash ADC Architecture
‫الومضي‬ ‫أو‬ ‫التفرعي‬ ‫المبدل‬ ‫بنية‬
• Input signal is concurrently compared
to all possible quantization levels
• 2N comparators, along with a voltage
divider, generate 2N reference voltages
• Comparator outputs them passed
through a “thermometer” decoder to
produce an N-bit digital word
• Highest throughput (> 100MSPs)
• Med-to-low Resolution (8-10bits)
• Highest Power consumption
Conversion Clk & Track/Hold not shown
0.5R
R
R
0.5R
e.g. TDC1048
8 to 3
e.g.
74f148
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‫المتزايد‬ ‫العدادي‬ ‫المبدل‬
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Tracking ADC ‫المالحق‬ ‫العدادي‬ ‫المبدل‬
Comparator
Analog
‫التمثيلي‬ ‫الجهد‬
Up
Down
Digital
output
+
–
Clock
Up-down
counter
D/A
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Converting Analog to Digital
‫المتتالي‬ ‫التقريب‬ ‫ذو‬ ‫المبدل‬ ‫بنية‬
•‫الصحيحة‬ ‫الثنائية‬ ‫القيمة‬ ‫عن‬ ‫البحث‬
Successive
Approximation
(Binary search)
a>b?
a
b
D/A
Conversion
Result
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• Most popular
– 8-18 bits resolution,
– throughput up to 5MSPs,
– no latency,
– power scales with conversion rate
• SAR Logic + DAC recursively supply N reference voltages
to the comparator, to be compared with the sampled input.
– 16-bit converter generates 16 comparisons per conversion
cycle
• Input Track/Hold is required (Vin assumed constant)
‫المتتالي‬ ‫التقريب‬ ‫ذو‬ ‫الرقمي‬ ‫التمثيلي‬ ‫المبدل‬ ‫بنية‬
1 2 3 4 5 6
OUTPUT CODE:
101011
D/A OUTPUT
3/4 FS
1/2 FS
1/4FS
DIGITAL
OUTPUT
DATA
REF
Clock
Successive
Approximation
Register
D/A
Converter
COMPARATOR
VIN
-
+
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‫المتتالي‬ ‫التقريب‬ ‫ذو‬ ‫الرقمي‬ ‫التمثيلي‬ ‫المبدل‬
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4-Bit SAR ‫مثال‬:‫المتتالي‬ ‫التقريب‬ ‫ذو‬ ‫مبدل‬
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‫المكامل‬ ‫الرقمي‬ ‫التمثيلي‬ ‫المبدل‬
+
–
Clock
va
C
R
Reset
‫الرقمي‬ ‫الخرج‬
Vref
‫مكامل‬
‫مقارن‬
+
–
‫عداد‬
‫تحكم‬ ‫دارة‬
‫الدخل‬ ‫جهد‬
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ADC dual-slop integration
‫الميل‬ ‫ثنائي‬ ‫التكاملي‬ ‫المبدل‬
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Two-step ADC employing pipelining
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2-Step Pipelined
• Flash architecture suffers From
exponential growth in power,
area and input capacitance, as
resolution is increased
• multi-step conversion
architectures trade throughput
for these 3 parameters by
spreading the quantization load
over M stages
• The front-end SHA, Coarse
Flash, DAC and Subtractor can
begin operating on the next
signal sample‫القادري‬ ‫منذر‬ ‫محمد‬ ‫المهندس‬ ‫الدكتور‬
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Latency in Pipelined Architecture
• Creates a latency between the time a signal is sampled, to
when its digital representation is available at the ADC output
• In contrast, the output of a SAR ADC is available before the
next sample clock (zero latency)‫القادري‬ ‫منذر‬ ‫محمد‬ ‫المهندس‬ ‫الدكتور‬
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N-Stage Pipelined Architecture
• Quantization load spread over N stages
– Each stage quantizes/encodes a small part of the overall conversion
• Modern devices have 6-10 stages
• High Throughput (10-100MSPs)
• Medium-High Resolution (up to 14 bits)
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Real ADC Errors
• Real ADCs have other errors in addition to the nominal quantization error
discussed
– Divided into the categories of STATIC & DYNAMIC, depending on
the rate of change of the input signal at time of digitization
• STATIC errors usually result from non-ideal spacing of code transition
levels
• DYNAMIC errors occur because of the additional sources of error
induced by the time variation of the analog signal being sampled
– Harmonic distortion from the S/H stage
– Signal-dependent variations in the sample instant
– Frequency-dependent variation in the spacing of the quantization
levels
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Model of Anti-Aliasing Check
0 dB
3 dB
Amplitude
Frequency
fd fc fs0.5fs
No Aliasing
in this region
Valid Data
Bandwidth
Data Spectrum Mirrored Data Spectrum
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Possible to reconstruct analog value from digitized
value?
•Let fs be the sampling frequency
•Input signals with frequency components > fs/2 cannot be
distinguished from signals with frequency components <
fs/2.
•Example: Signal: 5.6 Hz; Sampling: 9 Hz
-1.5
-1
-0.5
0
0.5
1
1.5
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Frequency spectrum of sampled signal
• Let Xc(): frequency
spectrum of the
continuous signal, cut-
off frequency
ΩN=2π fN
• Let Ωs=2π fs: sampling
frequency
• Let Xs: frequency
spectrum of the
sampled signal
• Xs consists of multiple
copies of Xc, separated
by Ωs
Formally: Xs = Xc folded with S,
with S: frequency spectrum of clock
Cannot be distinguished in sampled signal
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Aliasing
• If Ωs < ΩN/2 copies
of spectrum will
overlap
• (we don’t know the
original frequencies
any more)
No problem for signal reconstruction if this is avoided.
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Which ADC Architecture to Use??
Characteristic Flash Pipelined SAR Sigma
Delta
Throughput (samples/sec) 1 2 3 4
Resolution (ENOB) 4 3 2 1
Latency (Sample-to-Output) 1 3 2 4
Suitability for converting
Multiple Signals per ADC
1 2 1 3
Capability to convert non-
periodic multiplexed signals
1 2 1 3
Simplified anti-aliasing filter
requirements
**
Power Consumption Constant Constant Scales with
Sample Rate
Constant‫القادري‬ ‫منذر‬ ‫محمد‬ ‫المهندس‬ ‫الدكتور‬
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TI ADC Architectures & Sample Rates
Conversion Rate ( sps)
1K10010 10K 100K 1M 10M 100M
24
20
16
12
8
PipelineSAR
S
Oversampling
ConverterResolution-bits
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Rs Ri = 1k
Ci = 50pF
Vc = Vs 1 - e
- t c
R t C i
R t = Rs + R i
Vs
Vc 1/2 LSB = Vs-
Vs
2N
t c 1/2 LSB ln(131072)C i
= Rs + R i x x
For a 16-bit system we have:
ADC Input Structure
Acquisition Time - Calculation
Input Step 0 -Vs
Source resistance – 5K settling time 3.5uS
- 100 settling time is 0.65uS
RS=Input Buffer
Source Resistance
Ri=Sample Switch
ON Resistance
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DC Specs
• Differential Nonlinearity (DNL)
– Maximum deviation in the
difference between two code
transition points beyond the ideal
value of 1 LSB
–
• Integral Nonlinearity (INL), or
simply “Linearity”
– Maximum deviation (in #LSBs)
from “Ideal” ADC transfer function
• Offset Error
– Refers to output code with input
voltage of 0volts
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111
110
101
100
011
010
001
000
0 1 2 3 4 5 6 7
OutputCode
Input Voltage
Ideal transfer characteristic
Actual transfer
characteristic
DC Specs: Offset Error
• Defined as the difference between
the nominal and actual offset
points.
• For an ADC, the offset point is
the midstep value when the
digital output is zero.
• This error affects all codes by the
same amount and can usually be
compensated for by a trimming
process.
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111
110
101
100
011
010
001
000
0 1 2 3 4 5 6 7
OutputCode
Input Voltage
DC Specs: Gain Errors
• The deviation of the straight line
through the transfer function at
the intercept of full scale.
• Gain error is usually expressed as
a percentage of Full-Scale Range
(FSR), but can also be described
in volts or LSBs.
• Gain error is dominated by errors
in the converter’s reference
voltage.
11
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OutputCodeDC Specs: Differential Non-Linearity (DNL) Error
• Each code transition should
occur at an interval equal to
1LSB
• Differential Nonlinearity
(DNL)
– Maximum deviation in the
difference between two
code transition points
beyond the ideal value of 1
LSB
• DNL > 1LSB means that there
will be missing codes in the
output
• DNL impacts the SNR of the
converter
12
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‫الحاسب‬ ‫بإعتماد‬ ‫تحصيل‬ ‫لبطاقة‬ ‫صندوقي‬ ‫مخطط‬
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‫قياس‬ ‫أجهزة‬ ‫بعض‬ ‫أسماء‬:
1-‫باستخدام‬ ‫حرارة‬ ‫مقياس‬RTD
2-‫ترموكبل‬ ‫باستخدام‬ ‫حرارة‬ ‫مقياس‬
3-‫النواقل‬ ‫أنصاف‬ ‫باستخدام‬ ‫حرارة‬ ‫مقياس‬
4-‫الطيفي‬ ‫التحليل‬ ‫باستخدام‬ ‫حرارة‬ ‫مقاس‬
5-‫رطوبة‬ ‫مقياس‬
6-‫إضاءة‬ ‫شدة‬ ‫مقياس‬‫الشمسي‬ ‫اإلشعاع‬
7-‫ال‬ ‫فوق‬ ‫الترددات‬ ‫باستخدام‬ ‫سائل‬ ‫تدفق‬ ‫مقياس‬‫صوتية‬
8-‫التوربين‬ ‫باستخدام‬ ‫تدفق‬ ‫مقياس‬
9-‫اإلنكودر‬ ‫باستخدام‬ ‫محرك‬ ‫سرعة‬
10-‫رياح‬ ‫سرعة‬ ‫مقاس‬
11-‫مسافة‬ ‫مقياس‬
12-‫الكبل‬ ‫طول‬ ‫مقياس‬
13-‫سائل‬ ‫مستوى‬ ‫مقياس‬
14‫المتناوب‬ ‫الكهربائي‬ ‫التيار‬ ‫شدة‬ ‫مقياس‬
15-‫المستمر‬ ‫التيار‬ ‫شدة‬ ‫مقياس‬
16-‫الفعال‬ ‫الجهد‬ ‫مقياس‬
17-‫استطاعة‬ ‫مقياس‬
18-‫ممانعة‬ ‫مقاس‬
19-‫جدا‬ ‫صغيرة‬ ‫مقاومات‬ ‫مقياس‬
20-‫جدا‬ ‫كبيرة‬ ‫مقاومات‬ ‫مقياس‬
21-‫ساكنة‬ ‫شحنة‬ ‫مقياس‬
22-‫كمثف‬ ‫سعة‬ ‫مقياس‬
23-‫تحريضية‬ ‫مقياس‬
24-‫تسارع‬ ‫مقياس‬
25-‫ساكن‬ ‫عزم‬ ‫مقياس‬
26-‫ديناميكي‬ ‫عزم‬ ‫مقياس‬
27-‫تسارع‬ ‫مقياس‬
28-‫خطي‬ ‫انحراف‬‫ازاحة‬
29-‫زاوي‬ ‫نحراف‬ ‫مقياس‬
munthear@gmail.com

30-‫وزن‬ ‫خلية‬
31-‫ضغط‬ ‫مقياس‬
32-‫زمني‬ ‫عداد‬
33-‫تردد‬ ‫عداد‬
34-‫الجهد‬ ‫تشوه‬ ‫مقياس‬
35-‫إشارة‬ ‫راسم‬ ‫باستخدام‬ ‫طيف‬ ‫محلل‬
36-‫اشارة‬ ‫راسم‬ ‫باستخدام‬ ‫ترانزستور‬ ‫خواص‬ ‫راسم‬
37-
munthear@gmail.com

الإعتيان والتبديل التمثيلي الرقمي

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الإعتيان والتبديل التمثيلي الرقمي