The document presents the final report of a folded cascode amplifier design project. Key aspects of the design include: 1) The amplifier was designed to meet specifications including a gain of 85 dB, output swing of 1.4 V, and slew rate of 10 V/us. 2) A folded cascode topology was chosen to provide high output swing. Transistor sizes were calculated to meet the gain, slew rate, and output swing requirements. 3) Simulation results showed the design met all specifications, with an actual gain of 85.76 dB, phase margin of 60.1 degrees, and slew rate of 9.52 V/us.

1. Final report of Folded Cascode Amplifier
Instructor: Hoi Lee
Hao Yu (hxy141630)
Aalay Kapadia (adk130330)
Hao Xi (Hxx141730)
Fall 2015
EECT6326 Analog Circuit Design
Final Project Report

2. SPECIFICATIONS
The purpose of this project is to design a single-stage differential input and single-ended
output) Amplifier. 0.35-um CMOS process and a supply voltage of 1.8 V is required in
this design. The desired specifications is shown in Table I. Among the single-stage
topologies, the folded-cascade topology is chosen to meet the requirement for a high
output swing design.
Parameter Value Unit
Differential voltage gain, Avd >= 85 dB
Output voltage swing range, OVSR >= 1.4 V
Average Slew rate 10 V / us
Common mode rejection ratio, CMRR 80 dB
Unity-gain bandwidth, GBW >= 8 MHz
Phase margin, PM >=60 degree
Power dissipation <= 0.35 mW
Capacitive load 3 pF
Supply voltage 1.8 V
Table 1: Design specifications and Criteria
Design Consideration:
Parametercollection:
Before calculation, we firstly need to know the basic parameters of NMOS and PMOS in
the given library.
Using an easy testing circuit we can get the following parameters which shown in table2:
PMOS NMOS
Vth0 -696mV 556mV
μCox 72.35e-6 A/V2
164.73e-6 A/V2
Table 2: parameters collection in tested library
TopologyChosen:
This design we choose folded-cascode structure for its quality of high output swing. One
major consideration to use folded-cascode structure is that, compared to mirror-cascode
structure, the folded cascode stage can provide less current which means a larger output
impedance or a higher gain.

3. Powerconsumption consideration:
The power consumption is required to be less than 0.35mW which means the total current
under 1.8V supply voltage is 194μA. The current budget of 194μA mostly should be
distributed to the amplifier stage. Assume the differential pair tail current 𝐼 𝐵𝐼𝐴𝑆 is
31μA, the folded cascode tail current is 35μA. It is reasonable that the total power
consumption can be met.
Slew Rate consideration:
In folded Slew rate tail
L
I
SR
C
 >= 10V/μs (as required) where LC is 3pF. We get
𝐼 𝐵𝐼𝐴𝑆 is larger than 30 μA. We assume the 𝐼 𝐵𝐼𝐴𝑆 is 31μA.
Open loop gain consideration:
The open-loop gain is a function of transconductance and the output impedance,
where transconductance is proportional to √ 𝐼 𝐵𝐼𝐴𝑆 /2 and the output impedance is
proportional to
1
𝐼𝐿𝑜𝑎𝑑
. The expression for the open-loop gain is given below with respect
to circuit diagram in Figure 1:
outv RgmA 2,1 ; lowerupperout RRR // ]1[ 1190911 rogmroroRuppper  ;
)]//(1[)//( 12029101202 rrgmrrrRlower 
From equation, we can find that, for a bigger open loop gain, a small 𝐼𝐿𝑜𝑎𝑑 in folded
cascode part and a big load of 𝐼 𝐵𝐼𝐴𝑆 is needed
W/L ratio calculationfor differential pair:
For the required GBW >= 10MHz, from equation m
L
g
GBW
C
 ,we get the minimum
transconductance
*m Lg GBW C
= 10MHz * 2*π*3pF = 188.49 μA/V.

4. Since we know the current passing through differential pair i.e. 20uA and also we need
know minimum gm requirement, we can calculate minimum W/L ratio of differential pair
according to equation𝑔 𝑚 = √2𝐼 ∗ μCox(W/L), we get (W/L) 1, 2 min= 3.47
Therefore,the W/L ratio for differential input transistor should be at least 4
Output Voltage Swing considerationand W/L ratio calculationfor
folded cascode part.
The below equation shows the output voltage upper bound and lower bound.
𝑉𝑂𝑈𝑇,𝑚𝑎𝑥 = 𝑉𝐷𝐷 − |2𝑉𝑜𝑣| = 1.8 − 0.2 = 1.6 (1.7)
𝑉𝑂𝑈𝑇,𝑚𝑖𝑛 = 𝑉𝑆𝑆 + 2𝑉𝑜𝑣 = 0 + 0.2 = 0.2 (1.8)
Therefore,to get the desired output swing value, we need to limit the 𝑉𝑜𝑣 within 100
mV.
According to the equation:𝑉𝑜𝑣=√2I/μCox(w/l) ,include before assumption of I =
35μA, we can get the min(W/L)M18,M15 = 96.75;
(W/L)min[M0,M3,M4,M6] =23.67 ; (W/L)min[M5,M19] = 53 (where In = I- Ibias/2
= 19.5uA)
As calculated, we know that to get a high output swing, the minimum W/L for bottom
Nmos is 24, for top Pmos is 97 and 53 separately.

5. Schematics ofThe Folded-cascodeAmplifier
The schematic of the amplifier
Figure 1 shows the schematics of the folded cascade Amplifier structure and Table 2 is the
corresponding values for each transistor and parameter in the designed folded cascade
Amplifier.
Figure 1: Schematics of the folded cascode amplifier
Device Used Value
M18,M15 360u /2u
M19,M5 55u/1.5u
M6,M0 48u/2u
M4,M3 12u/1u
M22,M23 85u/1u
M21 35u/1u
Table 3: parameters of the amplifier
This structure we follows as professor instructs, in order to increase the gain and avoid
signal loss when signal goes to the folded part, we choose long channel device for the top part
of Pmos transistors.

6. The schematic of the current sink and start up circuity.
Figure 2: schematics of the current source and start-up circuity
Device Used Value
M1,M9 5.7u /1u
M7 2.6u/1u
M2 5.2u/600n
M10 650n/6u
M11 500n/15u
M12 20u/2u
M13 650n/2u
R 197K
Table 4: parameters of current source
For start-up circuity work properly, we add one more transistor M10 used for control the
Vth of M11
This current source using the topology of threshold voltage reference current source
which rely on threshold voltage. Therefore,we scan M2’s W/L ratio to find a better model for
us to use when generate a more stable threshold voltage.
The performance of start-up circuity will be presented in the simulation result part.

7. Schematic of Biasing Circuity
Figure 3: schematics of Biasing Circuitry
Device Used Value
M14 6.022u/1u
M24,M16,M26,M25,M30,M28,M29 1.9u/1u
M17 1.043u/1u
M20 1.648u/1u
M32,M33,M35,M36 206u/1u
M34 21.56u/1u
M37 20u/1u
Table 5: parameters of Biasing Circuity
The biasing circuity we mainly use the structure of cascade current mirror, because we
have a large current budget in this design, we can use a more accurate mirror in order to
decrease the mirror error.
The purpose of biasing circuity is to provide a high reliable biasing circuity to the
amplifier part. Hence,the stabitliy is the most important for us to consider in our design.
Problemencountered andTrade off:
In order to realize a high voltage gain and a good phase margin, there has a trade of
between the two. In previous consideration, there supposed to be no worry about phase
margin in a one stage design. However,the mirror pole and even the poles or zero generated
from biasing circuitry will influence the final result.

8. SIMULATION RESULT
Open-Loop Gain Testing and Result.
Figure 4: open-loop gain test bench
Figure 5: Result of open loop gain, phase margin and UGF
As result shows, the Gain = 85.76dB, PM = 60.1 degree and UGF = 22.84MHz

9. Powerconsumption result:
Figure 6 test bench of power consumption
Setting is same as the open-loop gain testing, we can see that V0 which is Vdd in test
bench, the current through is 140.5μA which is the total current. The value is much smaller
than 194μA in the required parameter.
Slew Rate Result
Figure 7: test bench of slew rate testing

10. Figure 8: result of slew rate measurement
The top figure is the output transient response followed by an input to give a pulse jump
from 410mV to 700mV. The below one is the derivation of above figure, we can find the top
and the valley of the wave is the positive slew rate and negative slew rate.
As simulated, the positive slew rate is 10.58 V/μs while negative slew rate is 8.46
V/μs.
Therefore, the simulated average slew rate is 9.52 V/μs.
Output swing Result
Figure 9: test bench of output swing measurement

11. Figure 10: Result of output swing followed waves
We can see that the upper bound can be followed to 1.5999V =1.6 V with input DC =
900mV. Because we cannot measure the lower bound, we can calculate the total output swing
using symmetric principle: (1.6 – 0.9) *2 = 1.4 V
CMRR measurement
Figure 11: test bench of Common mode rejection ratio

12. Figure 11: Result of open loop gain and common mode gain
We can see from the result above that the final CMRR = 85.76dB + 38.28 dB = 124.04 dB.
Start-up Circuity biasing part testing:
We test the current source with start-up circuity under the test bench of open loop gain
setting.
Figure 12: start up circuity when circuit works properly

13. Figure 13: start up circuity simulated when no current flows in circuity.
Figure 12 shows the result when the current source works properly, we can see that the
current we generated is 2.999μA as well as the start-up circuity do not work (transistor
M13 is closed)
Figure 13 simulated the condition when the input of start-up circuity goes to 0 which
will turn on the start-up circuity transistor M13 to push more current to the current
source.
Simulation ResultConclusion
Parameter Specifications data Simulated
Gain (1) 85.00 85.76 dB
Phase margin (2) 60.00 60.10 degree
Unity gain bandwidth (3) 10.00 22.83 MHz
Output voltage range (4) OVSR >= 1.40 1.4 V
Average slew rate (5) SR >= 10.00 9.52 V / us
Common mode rejection ratio (6) CMRR >= 80.00 124.04 dB
Dissipated power (7) Pdiss <= 0.35 0.29 mW
Table 6: Simulation result comparsion between specification and Simulated data.

14. CONCLUSION
For a high gain, high output swing and good phase margin one stage design, it is
difficult to realize all the parameters. The slew rate is hard to realize because we need
to limit the current flowing which could influence on other parameters. There always
be a trade-off condition when we are doing a design.
Final result andscores calculation
Using the metric presented in the project guideline, the following score is tabulated
for the design.
Parameter Simulated Unit Specification Scale
Calculated
Score
Gain (1) 85.76 dB 85.00 15.00 15
Phase margin (2) 60.10 degree 60.00 10.00 10.00
Unity gain bandwidth (3) 22.83 MHz 10.00 20.00 20.00
Output voltage range (4) 1.4 V 1.40 10.00 10
Average slew rate (5) 9.52 V / us 10.00 9.52 9.52
Common mode
rejection ratio (6)
124.04 dB
80.00 10.00 10.00
Dissipated power (7) 0.29 mW <= 0.35 15.00 15.00
Biasing 10 10
Total
Score: 99.52