The document describes the design of a differential input, single-ended output two-stage operational amplifier. A current mirror topology is used to meet the design specifications, including a differential voltage gain of at least 80 dB, output voltage swing range of at least 1.45 V, slew rate of at least 10 V/μs, and power dissipation of less than 0.35 mW. The design approach, schematic, analysis of DC operating points, AC performance, and output voltage swing are presented. Simulation results show the amplifier meets all specifications except for a slightly reduced slew rate of 9.79 V/μs.

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The University of Texas at Dallas
Department of Electrical Engineering
EECT 6326 ANALOG INTEGRATED CIRCUITS DESIGN
“Differential Current Mirror Two-Stage
Operational Amplifier”
Sriharini Ranganathan (2021255555)
Ilango Jeyasubramanian (202170958)
Ramkishan Gujuluva Nagarajan Dhanlakshmi (2021279911)

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CONTENTS
1. INTRODUCTION 3
2. DESIGN SPECIFICATIONS 3
3. DESIGN APPROACH 3
4. DESIGN SCHEMATIC 4
5. DC ANALYSIS 5
6. AC ANALYSIS 6
7. OUTPUT VOLTAGE SWING RANGE ANALYSIS 7
8. SLEW RATE 9
9. COMMON MODE REJECTION RATIO 10
10. POWER DISSIPATIONS 11
11. RESULTS 11
12. CONCLUSION 12
13. REFERENCES 12

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1. INTRODUCTION
The aim of the project is to design a differential input and single ended Two-Stage amplifier.
The amplifier is driven by the 1.8V power source and all the bias currents were generated using
self-biasing current sources and current mirrors instead of ideal current sources. A startup-circuit
has also been used along with the biasing circuit.
To meet the design specifications given below we chose to design a Differential Amplifier with
Current Mirror topology.
2. DESIGN SPECIFICATIONS
• Differential voltage gain: Avd >= 80 dB
• Output voltage swing range: OVSR = Vo(max) – Vo(min) >= 1.45 V
• Average slew rate: SR >= 10V/µs
• Common mode rejection ratio: CMRR >= 80 dB
• Unity-gain bandwidth: GBW >= 8 MHz
• Phase margin: f(GBW) >= 60°
• Power dissipation (VDD): Pdiss ≤ 0.35 mW (1.8V)
• Capacitive load: 3 pF
3. DESIGN APPROACH
1. The first step in the design approach is to calculate the miller-capacitor Cm from the given
load capacitor CL.
2. We know that the transconductance gm1 is much greater than gm6 and assuming the case
we calculated the value of Cm.
3. The value of Slew-rate to be met is given in the Specification chart and from the value of
Cm the tail current I5 is calculated.
4. Similarly Unity Gain Frequency is known and also Cm is known and so the
transcoductance gm1 is calculated. Thus gm6 is also obtained by our assumption.
5. The current flowing through the transistors M1 and M2 is half the current of tail current
I5.
6. With the values of I5 and gm1 the (W/L)1 is calculated and as a current mirror
(W/L)5=(W/L)1.
7. From the Output-swing Voltage Range the VGS under M6 is calculated and also from the
value of gm6 the current I6 is calculated. With the current the (W/L)6 is obtained.
8. The VGS of M6, M4 and M3 are same due to the current mirror configuration and as the
current flowing through them is known (W/L)4=(W/L)3 is calculated.
9. Similarly from the Output-swing the VGS under M7 is also obtained and so the current
flowing through M6 and M7 is same the gm7 is calculated and in turn we get the value of
(W/L)7.

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10. From the Power dissipation spec the maximum current is known and we set the current
as 16uA that is obtained from the self-biasing current source.
11. As the self-biasing transistor and M7 are current mirrors the (W/L) ratio of the self-
biasing transistor is obtained and so the (W/L)5 is obtained in the similar way.
12. The current mirror circuit is been designed to supply the subsequent bias-voltages in
such a way that all the transistors are in the saturation region (region=2).
13. The start-up circuit was designed as per the lecture notes using the inverter. The desired
current is set by tuning the tail resistor of the start-up mechanism.
14. The desired gain is achieved by the tuning the size of the M5 and also the output
resistance by marginally increased.
15. The major challenge faced by us is to achieve decent slew rate. To achieve a decent
slew rate the output current is controlled which is controlled by the current across M3
and M4.
4. DESIGN SCHEMATIC
Fig1. Schematic of Current Mirror Two-Stage Operational Amplifier

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The table containing the transistor size is given below:
TRANSISTORS W/L(um)
M1, M2 50/1.7
M25, M3 25/1
M28 121/1
M0 17/1
Mb 6/1
M23 5/1
The schematic of start-up circuit is also given below
Fig2. Schematic of Start-up Circuit
5. DC ANALYSIS
To check the transistors in saturation region we compute the DC analysis by perfect biasing.
In order to observe the saturation region of the transistors we annotate the output and can
be observed that “region=2” is equivalent to the saturation mode from the figure.

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Fig3. Transistors in the saturation region
As the start-up circuit contains an inverter it is not required that all the transistors should be
in saturation region. In the beginning start-up transistor should always be off and the nmos
of the inverter will be in triode region. Other than these all were in saturation region.
Fig4. Start-up Circuit DC analysis
6. AC ANALYSIS
Before starting the AC analysis the symbol view of the amplifier is created and the
connections VDD, GND, Vin+, Vin- and Vo is created.

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From the AC analysis the Differential Gain, Phase Margin and Unity Gain Bandwidth are
obtained. To simulate AC analysis the following setup is done with biasing current of 16uA,
VDD at 1.8V, load capacitance 3pF, non-inverting input DC-800mV AC-800mV, and
inverting input DC-800mV AC-800mV. Analysis is done from 0-100MHz and the graph is
plotted.
Fig5. AC Analysis Setup
Fig6. Result: Gain vs Frequency and Phase vs Frequency
It can be seen from the graph that out gain is about 82.74dB. The unity gain bandwidth was
read as 33.54MHz. The phase margin was found to be 60°.
7. OUTPUT VOLTAGE SWING RANGE ANALYSIS
The Output Voltage Swing range is defined as the difference between the maximum and
minimum value that can be achieved by the output voltage. To obtain the analysis following
setup is done.

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 Apply a DC variable from 0V to 1.8V to the positive input terminal and set 1V DC to
the negative input terminal.
 Apply 16uA to input terminal.
 Apply 1.8V DC between VDD and GND terminal.
 Simulated and the graph obtained is shown below.
Fig7. OVSR Measurement
Fig8. Result of the OVSR simulation
From the above figure OVSR = VO(max) – VO(min) = 1.665 V – 0.09331 V = 1.57169 V

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8. SLEW RATE
The below shown setup is done to compute the slew rate. Using the current source of 30uA,
the output is connected as a feedback to the inverting input in parallel with the load capacitance.
In the non-inverting input a pulse wave with low of 800mV and high 1.8V is given along with the
rise and fall time of 0s and on-time 1us with period of 2us. Transient analysis with stop time till
5us is simulated and the output is observed by plotting the figure.
Fig9. Slew-rate setup
Fig10. Result of Slew-rate
The result of slew rate are given as below:
Positive slew rate (SR+) = 9.316 V/us
Negative slew rate (SR-) = 10.2731 V/us
Average slew rate ((SR+ + SR-)/2) = 9.7945 V/us

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9. COMMON MODE REJECTION RATIO
The following setup is done to simulate the CMRR by shorting both the input terminals and are
given a DC and AC voltage 900mV and do AC analysis.
Fig11. CMRR setup
Fig12. Result of Common mode Gain
From the above figure ACM-DM is -5.733 dB
Thus CMRR = 82.74 – (-5.733) = 88.473 dB

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10. POWER DISSIPATION
From the setup shown below the total current drawn from the source is 123uA. Thus the total
power dissipated is given as Pdiss = 123uA*1.8V = 0.22mW
Fig13. Power dissipation observed through voltage source
11. RESULTS
Parameters Value
Differential Voltage Gain 82.74dB
Phase Margin 60°
Unity Gain Bandwidth 33.54 MHz
Slew Rate 9.7945 V/μs
Output Voltage Swing Range 1.57169V
Common Mode Rejection Ratio 88.473 dB
Power Dissipation 0.22mW
Table1. Result of Current Mirror Operational Amplifier
FINAL SCORE
The final score of the design is calculated using the formula:
As we have used the self-biasing circuit, 10 for biasing

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Avd(dB) OVSR SR CMRR GBW PM Pdiss
Required ≥80 dB ≥1.45 V ≥10V/us ≥80 dB ≥8 MHz ≥60° ≤0.35 mW
Simulated 82.74dB 1.57169V 9.7945V/us 88.473dB 33.54MHz 60° 0.22mW
Table2. Score for the design
SCORE = 15 + 10 + 9.79 + 10 + 20 + 10 + 15 + 10 = 99.79
12. CONCLUSION
As a whole the Differential Current Mirror Two-Stage Amplifier designed provides higher gain
with higher output voltage swing. In our design only the slew rate is compromised by very
minimal value since it was found to be inversely proportional to the gain.
13. REFERENCES
1. Lee, H, Summer 2015, Analog Integrated Circuit Design, EECT 6326 Class notes,The University of
Texas at Dallas, United States
2. Razavi, B, 2003. Design of Analog CMOS Integrated Circuits. 2nd ed. United States: McGraw Hill
3. Gray, P, 2003. Analysis and Design of Analog Integrated Circuits. 5th ed. United States: Wiley