This document summarizes the design and simulation of an operational amplifier with high gain and bandwidth for switched capacitor filters. The authors designed a single-stage folded cascode operational amplifier using a 180nm CMOS technology. They applied a gain boosting technique to increase the amplifier's gain without affecting bandwidth. Simulations showed the gain increased by 88% after applying this technique, reaching 76dB, while maintaining a bandwidth of 1.17GHz. The authors also designed a first-order high-pass filter using this amplifier with a cutoff frequency of 10MHz. Simulations verified the filter functioned as expected, filtering out low frequencies.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
Design of 10 to 12 GHz Low Noise Amplifier for Ultrawideband (UWB) SystemIJECEIAES
Balanced amplifier is the structure proposed in this article, it provides better performance. In fact, the single amplifier meets the specification for noise figure and gain but fails to meet the return loss specification due to the large mis-matches on the input & outputs. To overcome this problem one solution is to use balanced amplifier topography. In this paper, a wide-band and highgain microwave balanced amplifier constituted with branch line coupler circuit is proposed. The amplifier is unconditionally stable in the band [9-13] GHz where the gain is about 20dB. The input reflection (S11) and output return loss (S22) at 11 GHz are -33.4dB and -33.5dB respectively.
Investigation of TTMC-SVPWM Strategies for Diode Clamped and Cascaded H-bridg...ijeei-iaes
This paper presents a concept of two types multilevel inverters such as diode clamped and cascaded H-bridge for harmonic reduction on high power applications. Normally, multilevel inverters can be used to reduce the harmonic problems in electrical distribution systems. This paer focused on the performance and analysis of a three phase seven level inverter including diode clamped and cascaded H-bridge based on new tripizodal triangular space vector PWM technique approaches. TTMC based modified Space vector Pulse width modulation technique so called tripizodal triangular Space vector Pulse width modulation (TTMC-SVPWM) technique. In this paper the reference sine wave generated as in case of conventional off set injected SVPWM technique. It is observed that the TTMC-Space vector pulse width modulation ensures excellent, close to optimized pulse distribution results and THD is compared to seven level, diode clamped and cascaded multi level inverters. Theoretical investigations were confirmed by the digital simulations using MATLAB/SIMULINK software.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
Design of 10 to 12 GHz Low Noise Amplifier for Ultrawideband (UWB) SystemIJECEIAES
Balanced amplifier is the structure proposed in this article, it provides better performance. In fact, the single amplifier meets the specification for noise figure and gain but fails to meet the return loss specification due to the large mis-matches on the input & outputs. To overcome this problem one solution is to use balanced amplifier topography. In this paper, a wide-band and highgain microwave balanced amplifier constituted with branch line coupler circuit is proposed. The amplifier is unconditionally stable in the band [9-13] GHz where the gain is about 20dB. The input reflection (S11) and output return loss (S22) at 11 GHz are -33.4dB and -33.5dB respectively.
Investigation of TTMC-SVPWM Strategies for Diode Clamped and Cascaded H-bridg...ijeei-iaes
This paper presents a concept of two types multilevel inverters such as diode clamped and cascaded H-bridge for harmonic reduction on high power applications. Normally, multilevel inverters can be used to reduce the harmonic problems in electrical distribution systems. This paer focused on the performance and analysis of a three phase seven level inverter including diode clamped and cascaded H-bridge based on new tripizodal triangular space vector PWM technique approaches. TTMC based modified Space vector Pulse width modulation technique so called tripizodal triangular Space vector Pulse width modulation (TTMC-SVPWM) technique. In this paper the reference sine wave generated as in case of conventional off set injected SVPWM technique. It is observed that the TTMC-Space vector pulse width modulation ensures excellent, close to optimized pulse distribution results and THD is compared to seven level, diode clamped and cascaded multi level inverters. Theoretical investigations were confirmed by the digital simulations using MATLAB/SIMULINK software.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Improving Light-Load Efficiency by Eliminating Interaction Effect in the Grid...IJAPEJOURNAL
A wind turbine equipped with doubly-fed induction generator (DFIG) is used in wind power plant industry. This paper studies the maximum power extraction of DFIG via evaluation of state-space equations in closed loop control condition for improving light-load efficiency. The DFIG state-space equations have been considered in the form of a multi-input- multi output (MIMO) system. Also, the tracing table has been used to determine the speed which the generated power will be proportional to the maximum load. The tracing table input is the generator speed, and its output is the optimum active power that has been considered as the reference power of the active power control system of the convertor. A controller is presented for the tracing table and the extracted power is able to follow the reference power with minimum ripple. Then, the results are compared with the single-input and single-output (SISO) case, for the values up to 0.2 times of the rated load. Therefore, in MIMO modeling, in the case that the DFIG connected to the grid, by eliminating the interaction effect, the efficiency in light-load can be increased
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
DESIGN OF 2.4 GHZ MMIC FEED FORWARD AMPLIFIER FOR WIRELESS APPLICATIONS jmicro
This paper proposes a design of 0.15μm Monolithic Microwave Integrated Circuit (MMIC) power amplifier using GaAs pHEMT technology at 2.4 GHz which employs feed forward linearization technique to improve linearity. The amplifier is designed to operate in personal communication systems (PCS) frequency range using WIN semiconductor GaAs pHEMT technology. Single stage power amplifier is designed in lumped and distributed components with its layout. Linearity of PA is improved by Feed forward Linearization technique. To evaluate the performance of proposed linearized amplifier, Advanced Design system (ADS) tool is used. The designed circuit results with 13.65dBm output power at 1dB compression point (P1dB), 6dB power gain and maximum Power added efficiency of 16.4%. Linearity achieved by feed forward linearizer circuit with third order intermodulation suppression of 30dBc for the output power level of 8.217dBm and 1dB compression point at an input power of 15 dBm whereas 6 dBm for the Power amplifier without feed forward linearizer circuit. The designed Power amplifier system with feed forward linearizer had IMD3 suppression of 30dBc which is in appreciable range with improvement in 1dB compression point
In modern society every sector needs continuous power on demand. To achieve this voltage,
current and frequency, these parameters of the power system should be at rated values. Because of
remote generation, transmission and distribution, we are failing to receive the reliable power. To
overcome this problem, the Distribution energy sources (DES) become more suitable solution. This
generated power from DES is supplied to local loads and this can be connected to the main grid
through the Micro-Grid (MG). Micro-grids will operate in two modes, A Grid-connected mode and in
an Islanded mode. During islanding mode, one Distributed Generation (DG) unit should share output
generation power with other unit in exact accordance with the load. Need to control Real and Reactive
power effectively for the load to operate without disturbance. Hence in the present work, Voltage
Source Inverter (VSI) and Proportional Integral Derivative(PID) controller in power conversion
process to get required real and reactive power for the normal operation of micro-grid. The proposed
method has been applied to a designed test Simulink model for different types of Grid connected and
Isolated modes. The simulation results obtained show that, this method can improves the reliability and
smooth operation of the micro-grid system.
DESIGN OF 2.4 GHZ MMIC FEED FORWARD AMPLIFIER FOR WIRELESS APPLICATIONS jmicro
This paper proposes a design of 0.15μm Monolithic Microwave Integrated Circuit (MMIC) power amplifier
using GaAs pHEMT technology at 2.4 GHz which employs feed forward linearization technique to improve
linearity. The amplifier is designed to operate in personal communication systems (PCS) frequency range
using WIN semiconductor GaAs pHEMT technology. Single stage power amplifier is designed in lumped
and distributed components with its layout. Linearity of PA is improved by Feed forward Linearization
technique. To evaluate the performance of proposed linearized amplifier, Advanced Design system (ADS)
tool is used. The designed circuit results with 13.65dBm output power at 1dB compression point (P1dB),
6dB power gain and maximum Power added efficiency of 16.4%. Linearity achieved by feed forward
linearizer circuit with third order intermodulation suppression of 30dBc for the output power level of
8.217dBm and 1dB compression point at an input power of 15 dBm whereas 6 dBm for the Power amplifier
without feed forward linearizer circuit. The designed Power amplifier system with feed forward linearizer
had IMD3 suppression of 30dBc which is in appreciable range with improvement in 1dB compression
point.
Design and Realization of 2.4GHz Branch-line CouplerQuang Binh Pham
In the scope of this paper, a branch-line coupler working at 2.4GHz is designed and realized. The experiment results are consequently compared to the simulation results.
Research Inventy : International Journal of Engineering and Scienceinventy
Research Inventy : International Journal of Engineering and Science
Research Inventy : International Journal of Engineering and Science is published by the group of young academic and industrial researchers with 12 Issues per year. It is an online as well as print version open access journal that provides rapid publication (monthly) of articles in all areas of the subject such as: civil, mechanical, chemical, electronic and computer engineering as well as production and information technology. The Journal welcomes the submission of manuscripts that meet the general criteria of significance and scientific excellence. Papers will be published by rapid process within 20 days after acceptance and peer review process takes only 7 days. All articles published in Research Inventy will be peer-reviewed
DESIGN OF 2.4 GHZ MMIC FEED FORWARD AMPLIFIER FOR WIRELESS APPLICATIONSjmicro
This paper proposes a design of 0.15μm Monolithic Microwave Integrated Circuit (MMIC) power amplifier
using GaAs pHEMT technology at 2.4 GHz which employs feed forward linearization technique to improve
linearity. The amplifier is designed to operate in personal communication systems (PCS) frequency range
using WIN semiconductor GaAs pHEMT technology. Single stage power amplifier is designed in lumped
and distributed components with its layout. Linearity of PA is improved by Feed forward Linearization
technique. To evaluate the performance of proposed linearized amplifier, Advanced Design system (ADS)
tool is used. The designed circuit results with 13.65dBm output power at 1dB compression point (P1dB),
6dB power gain and maximum Power added efficiency of 16.4%. Linearity achieved by feed forward
linearizer circuit with third order intermodulation suppression of 30dBc for the output power level of
8.217dBm and 1dB compression point at an input power of 15 dBm whereas 6 dBm for the Power amplifier
without feed forward linearizer circuit. The designed Power amplifier system with feed forward linearizer
had IMD3 suppression of 30dBc which is in appreciable range with improvement in 1dB compression
point.
A survey of low power wallace and dadda multipliers using different logic ful...eSAT Journals
Abstract In recent years, power dissipation is one of the biggest challenge in VLSI design. Multipliers are the main source of power dissipation in DSP block. Power of any multiplier can be reduced by designing a full adder which will consume very less power. So a lot of researches have been made to decrease the power consumption of the full adder. Here a structured approach for analysing the Wallace and Dadda multiplier is introduced. These multiplier are designed using existing full adders like 28T,16T,14T, and TGFA. These designs are studied and the analysis is made based on the simulation parameter like no of transistors count and power consumption using micro wind tool. Keywords: Full Adder, Wallace Tree Multiplier, Dadda Multiplier, Power Consumption.
A 10 d bm 25 dbm, 0.363 mm2 two stage 130 nm rf cmos power amplifierVLSICS Design
This paper proposes a 2.4 GHz RF CMOS Power amplifi
er and variation in its main performance
parameters i.e, output power, S-parameters and powe
r added efficiency with respect to change in supply
voltage and size of the power stage transistor. The
supply voltage was varied form 1 V to 5 V and the
range
of output power at 1dB compression point was found
to be from 10.684 dBm to 25.08 dBm respectively.
The range of PAE is 16.65 % to 48.46 %. The width o
f the power stage transistor was varied from 150 μm
to 500 μm to achieve output power of range 15.47 dB
m to 20.338 dBm. The range of PAE obtained here is
29.085 % to 45.439 %. The total dimension of the la
yout comes out to be 0.714 * 0.508 mm
2
.
Gain improvement of two stage opamp through body bias in 45nm cmos technologyeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
A Review on Modeling and Analysis of Multi Stage with Multi Phase DC DC Boost...YogeshIJTSRD
A new version of the new Hybrid Boost DC DC ready to draw power from two different DC sources for standard DC bus feeds is presented in this paper. An important feature of the proposed converter is that both sources provide simultaneous power to a lower load than the reduced current rate. This feature is very attractive for DC grid applications. With the analysis of the time zone, steady state performance is established and the transformational power correction parameters are obtained. In this paper, a powerful converter is introduced, with its operating principles based on charging pumps and converters of reinforcement series. In addition, although three switches are used, no separate gate driver is required instead of one bridge gate driver and one gate driver on the lower side. As such, the proposed converter is easy to analyze and easy to operate. In addition, additional test results are provided to confirm the effectiveness of the proposed converter. Mukesh Kuma | Manoj Kumar Dewangan | Maheedhar Dubey "A Review on Modeling and Analysis of Multi Stage with Multi Phase DC-DC Boost Converter" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-5 | Issue-3 , April 2021, URL: https://www.ijtsrd.com/papers/ijtsrd39985.pdf Paper URL: https://www.ijtsrd.com/engineering/electrical-engineering/39985/a-review-on-modeling-and-analysis-of-multi-stage-with-multi-phase-dcdc-boost-converter/mukesh-kuma
26 GHz phase shifters for multi-beam nolen matrix towards fifth generation (5...journalBEEI
This paper presents the designs of phase shifters for multi-beam Nolen matrix towards the fifth generation (5G) technology at 26 GHz. The low-cost, lightweight and compact size 0° and 45° loaded stubs and chamfered 90°, 135° and 180° Schiffman phase shifters are proposed at 26 GHz. An edge at a corner of the 50 Ω microstrip line Schiffman phase shifter is chamfered to reduce the excess capacitance and unwanted reflection. However, the Schiffman phase shifter topology is not relevant to be applied for the phase shifter less than 45° as it needs very small arc bending at 26 GHz. The stubs are loaded to the phase shifter in order to obtain electrical lengths, which are less than 45°. The proposed phase shifters provide return loss better than 10 dB, insertion loss of -0.97 dB and phase difference imbalance of ± 4.04° between 25.75GHz and 26.25 GHz. The Rogers RT/duroid 5880 substrate with dielectric constant of 2.2 and substrate thickness of 0.254 mm is implemented in the designs.
A 300 GHz CMOS Transmitter Front-End for Ultrahigh-Speed Wireless CommunicationsIJECEIAES
This paper presents a 300 GHz transmitter front-end suitable for ultrahigh-speed wireless communications. The transmitter front-end realized in TSMC 40 nm CMOS consists of a common-source (CS) based doubler driven by a two-way D-band power amplifier (PA). Simulation results show that the two-way D-band PA obtains a peak gain of 21.6 dB over a -3 dB bandwidth from 132 GHz to 159 GHz. It exhibits a saturated power of 7.2 dBm and a power added efficiency (PAE) of 2.3%, all at 150 GHz. The CS based doubler results in an output power of 0.5 mW at 300 GHz. The transmitter front-end consumes a DC power of 205.8 mW from a 0.9 V supply voltage while it occupies an area of 2.1 mm 2 .
Abstract:
This paper reports on the design of an ultra wideband power amplifier using 0.25um GaN- HEMT Technology device obtained from the Triquint Semiconductor. There is huge interest in transistors based on Gallium Nitride in recent years due to its high breakdown voltage and its capability to operate in High frequency applications. The load pull analysis is carried out to obtain both the required source and load impedances. The
power amplifier with over 10W output power and 42% power added efficiency in the frequency range of 3-5GHz is presented in this paper. The PA is designed using a computer aided design tool called Advanced System Design (ADS).ADS provide two different simulation opportunities. These are referred as schematic simulation and
electromagnetic simulation called Momentum. Schematic Simulations are performed on the proposed PA in this paper.
Keywords:- GaN-HEMT Technology, Load pull analysis, Advanced system design(ADS)
Low Power and Fast Transient High Swing CMOS Telescopic Operational AmplifierIJERA Editor
CMOS telescopic operational amplifier with high-swing and high-performance is described in this paper. The
swing is attained by using the tail and current source-transistors in deep-linear region. The resultant deprivation
in parameters like differential gain, CMRR and added characteristics are recompensed by using regulatedcascode
differential gain enhancement and a replica-tail feedback technique. Operating at power supply of 3.3V,
the power consumption, slew rate and settling time are improved using transmission controlled pass circuitry
and level amplifier. It is shown through simulations that the Op-Amp preserves its high CMRR and unity gain
frequency.
Wideband power amplifier based on Wilkinson power divider for s-band satellit...journalBEEI
This paper presents design and simulation of wideband power amplifier based on multi-section Wilkinson power divider. Class-A topology and ATF-511P8 transistor have been used. Advanced Design System (ADS) software used to simulate the designed power amplifier. The simulation results show an input return loss (S11)<-10dB, gain (S21)>10 dB over the entire bandwidth, and an output power around 28dBm at the Centre frequency of 3GHz. The designed amplifier is stable over the entire bandwidth (K>1). Inter-modulation distortion is -65.187dBc which is less than -50dBc. The designed amplifier can be used for the microwave applications which include weather radar, satellite communication, wireless networking, mobile, and TV.
Improving Light-Load Efficiency by Eliminating Interaction Effect in the Grid...IJAPEJOURNAL
A wind turbine equipped with doubly-fed induction generator (DFIG) is used in wind power plant industry. This paper studies the maximum power extraction of DFIG via evaluation of state-space equations in closed loop control condition for improving light-load efficiency. The DFIG state-space equations have been considered in the form of a multi-input- multi output (MIMO) system. Also, the tracing table has been used to determine the speed which the generated power will be proportional to the maximum load. The tracing table input is the generator speed, and its output is the optimum active power that has been considered as the reference power of the active power control system of the convertor. A controller is presented for the tracing table and the extracted power is able to follow the reference power with minimum ripple. Then, the results are compared with the single-input and single-output (SISO) case, for the values up to 0.2 times of the rated load. Therefore, in MIMO modeling, in the case that the DFIG connected to the grid, by eliminating the interaction effect, the efficiency in light-load can be increased
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
DESIGN OF 2.4 GHZ MMIC FEED FORWARD AMPLIFIER FOR WIRELESS APPLICATIONS jmicro
This paper proposes a design of 0.15μm Monolithic Microwave Integrated Circuit (MMIC) power amplifier using GaAs pHEMT technology at 2.4 GHz which employs feed forward linearization technique to improve linearity. The amplifier is designed to operate in personal communication systems (PCS) frequency range using WIN semiconductor GaAs pHEMT technology. Single stage power amplifier is designed in lumped and distributed components with its layout. Linearity of PA is improved by Feed forward Linearization technique. To evaluate the performance of proposed linearized amplifier, Advanced Design system (ADS) tool is used. The designed circuit results with 13.65dBm output power at 1dB compression point (P1dB), 6dB power gain and maximum Power added efficiency of 16.4%. Linearity achieved by feed forward linearizer circuit with third order intermodulation suppression of 30dBc for the output power level of 8.217dBm and 1dB compression point at an input power of 15 dBm whereas 6 dBm for the Power amplifier without feed forward linearizer circuit. The designed Power amplifier system with feed forward linearizer had IMD3 suppression of 30dBc which is in appreciable range with improvement in 1dB compression point
In modern society every sector needs continuous power on demand. To achieve this voltage,
current and frequency, these parameters of the power system should be at rated values. Because of
remote generation, transmission and distribution, we are failing to receive the reliable power. To
overcome this problem, the Distribution energy sources (DES) become more suitable solution. This
generated power from DES is supplied to local loads and this can be connected to the main grid
through the Micro-Grid (MG). Micro-grids will operate in two modes, A Grid-connected mode and in
an Islanded mode. During islanding mode, one Distributed Generation (DG) unit should share output
generation power with other unit in exact accordance with the load. Need to control Real and Reactive
power effectively for the load to operate without disturbance. Hence in the present work, Voltage
Source Inverter (VSI) and Proportional Integral Derivative(PID) controller in power conversion
process to get required real and reactive power for the normal operation of micro-grid. The proposed
method has been applied to a designed test Simulink model for different types of Grid connected and
Isolated modes. The simulation results obtained show that, this method can improves the reliability and
smooth operation of the micro-grid system.
DESIGN OF 2.4 GHZ MMIC FEED FORWARD AMPLIFIER FOR WIRELESS APPLICATIONS jmicro
This paper proposes a design of 0.15μm Monolithic Microwave Integrated Circuit (MMIC) power amplifier
using GaAs pHEMT technology at 2.4 GHz which employs feed forward linearization technique to improve
linearity. The amplifier is designed to operate in personal communication systems (PCS) frequency range
using WIN semiconductor GaAs pHEMT technology. Single stage power amplifier is designed in lumped
and distributed components with its layout. Linearity of PA is improved by Feed forward Linearization
technique. To evaluate the performance of proposed linearized amplifier, Advanced Design system (ADS)
tool is used. The designed circuit results with 13.65dBm output power at 1dB compression point (P1dB),
6dB power gain and maximum Power added efficiency of 16.4%. Linearity achieved by feed forward
linearizer circuit with third order intermodulation suppression of 30dBc for the output power level of
8.217dBm and 1dB compression point at an input power of 15 dBm whereas 6 dBm for the Power amplifier
without feed forward linearizer circuit. The designed Power amplifier system with feed forward linearizer
had IMD3 suppression of 30dBc which is in appreciable range with improvement in 1dB compression
point.
Design and Realization of 2.4GHz Branch-line CouplerQuang Binh Pham
In the scope of this paper, a branch-line coupler working at 2.4GHz is designed and realized. The experiment results are consequently compared to the simulation results.
Research Inventy : International Journal of Engineering and Scienceinventy
Research Inventy : International Journal of Engineering and Science
Research Inventy : International Journal of Engineering and Science is published by the group of young academic and industrial researchers with 12 Issues per year. It is an online as well as print version open access journal that provides rapid publication (monthly) of articles in all areas of the subject such as: civil, mechanical, chemical, electronic and computer engineering as well as production and information technology. The Journal welcomes the submission of manuscripts that meet the general criteria of significance and scientific excellence. Papers will be published by rapid process within 20 days after acceptance and peer review process takes only 7 days. All articles published in Research Inventy will be peer-reviewed
DESIGN OF 2.4 GHZ MMIC FEED FORWARD AMPLIFIER FOR WIRELESS APPLICATIONSjmicro
This paper proposes a design of 0.15μm Monolithic Microwave Integrated Circuit (MMIC) power amplifier
using GaAs pHEMT technology at 2.4 GHz which employs feed forward linearization technique to improve
linearity. The amplifier is designed to operate in personal communication systems (PCS) frequency range
using WIN semiconductor GaAs pHEMT technology. Single stage power amplifier is designed in lumped
and distributed components with its layout. Linearity of PA is improved by Feed forward Linearization
technique. To evaluate the performance of proposed linearized amplifier, Advanced Design system (ADS)
tool is used. The designed circuit results with 13.65dBm output power at 1dB compression point (P1dB),
6dB power gain and maximum Power added efficiency of 16.4%. Linearity achieved by feed forward
linearizer circuit with third order intermodulation suppression of 30dBc for the output power level of
8.217dBm and 1dB compression point at an input power of 15 dBm whereas 6 dBm for the Power amplifier
without feed forward linearizer circuit. The designed Power amplifier system with feed forward linearizer
had IMD3 suppression of 30dBc which is in appreciable range with improvement in 1dB compression
point.
A survey of low power wallace and dadda multipliers using different logic ful...eSAT Journals
Abstract In recent years, power dissipation is one of the biggest challenge in VLSI design. Multipliers are the main source of power dissipation in DSP block. Power of any multiplier can be reduced by designing a full adder which will consume very less power. So a lot of researches have been made to decrease the power consumption of the full adder. Here a structured approach for analysing the Wallace and Dadda multiplier is introduced. These multiplier are designed using existing full adders like 28T,16T,14T, and TGFA. These designs are studied and the analysis is made based on the simulation parameter like no of transistors count and power consumption using micro wind tool. Keywords: Full Adder, Wallace Tree Multiplier, Dadda Multiplier, Power Consumption.
A 10 d bm 25 dbm, 0.363 mm2 two stage 130 nm rf cmos power amplifierVLSICS Design
This paper proposes a 2.4 GHz RF CMOS Power amplifi
er and variation in its main performance
parameters i.e, output power, S-parameters and powe
r added efficiency with respect to change in supply
voltage and size of the power stage transistor. The
supply voltage was varied form 1 V to 5 V and the
range
of output power at 1dB compression point was found
to be from 10.684 dBm to 25.08 dBm respectively.
The range of PAE is 16.65 % to 48.46 %. The width o
f the power stage transistor was varied from 150 μm
to 500 μm to achieve output power of range 15.47 dB
m to 20.338 dBm. The range of PAE obtained here is
29.085 % to 45.439 %. The total dimension of the la
yout comes out to be 0.714 * 0.508 mm
2
.
Gain improvement of two stage opamp through body bias in 45nm cmos technologyeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
A Review on Modeling and Analysis of Multi Stage with Multi Phase DC DC Boost...YogeshIJTSRD
A new version of the new Hybrid Boost DC DC ready to draw power from two different DC sources for standard DC bus feeds is presented in this paper. An important feature of the proposed converter is that both sources provide simultaneous power to a lower load than the reduced current rate. This feature is very attractive for DC grid applications. With the analysis of the time zone, steady state performance is established and the transformational power correction parameters are obtained. In this paper, a powerful converter is introduced, with its operating principles based on charging pumps and converters of reinforcement series. In addition, although three switches are used, no separate gate driver is required instead of one bridge gate driver and one gate driver on the lower side. As such, the proposed converter is easy to analyze and easy to operate. In addition, additional test results are provided to confirm the effectiveness of the proposed converter. Mukesh Kuma | Manoj Kumar Dewangan | Maheedhar Dubey "A Review on Modeling and Analysis of Multi Stage with Multi Phase DC-DC Boost Converter" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-5 | Issue-3 , April 2021, URL: https://www.ijtsrd.com/papers/ijtsrd39985.pdf Paper URL: https://www.ijtsrd.com/engineering/electrical-engineering/39985/a-review-on-modeling-and-analysis-of-multi-stage-with-multi-phase-dcdc-boost-converter/mukesh-kuma
26 GHz phase shifters for multi-beam nolen matrix towards fifth generation (5...journalBEEI
This paper presents the designs of phase shifters for multi-beam Nolen matrix towards the fifth generation (5G) technology at 26 GHz. The low-cost, lightweight and compact size 0° and 45° loaded stubs and chamfered 90°, 135° and 180° Schiffman phase shifters are proposed at 26 GHz. An edge at a corner of the 50 Ω microstrip line Schiffman phase shifter is chamfered to reduce the excess capacitance and unwanted reflection. However, the Schiffman phase shifter topology is not relevant to be applied for the phase shifter less than 45° as it needs very small arc bending at 26 GHz. The stubs are loaded to the phase shifter in order to obtain electrical lengths, which are less than 45°. The proposed phase shifters provide return loss better than 10 dB, insertion loss of -0.97 dB and phase difference imbalance of ± 4.04° between 25.75GHz and 26.25 GHz. The Rogers RT/duroid 5880 substrate with dielectric constant of 2.2 and substrate thickness of 0.254 mm is implemented in the designs.
A 300 GHz CMOS Transmitter Front-End for Ultrahigh-Speed Wireless CommunicationsIJECEIAES
This paper presents a 300 GHz transmitter front-end suitable for ultrahigh-speed wireless communications. The transmitter front-end realized in TSMC 40 nm CMOS consists of a common-source (CS) based doubler driven by a two-way D-band power amplifier (PA). Simulation results show that the two-way D-band PA obtains a peak gain of 21.6 dB over a -3 dB bandwidth from 132 GHz to 159 GHz. It exhibits a saturated power of 7.2 dBm and a power added efficiency (PAE) of 2.3%, all at 150 GHz. The CS based doubler results in an output power of 0.5 mW at 300 GHz. The transmitter front-end consumes a DC power of 205.8 mW from a 0.9 V supply voltage while it occupies an area of 2.1 mm 2 .
Abstract:
This paper reports on the design of an ultra wideband power amplifier using 0.25um GaN- HEMT Technology device obtained from the Triquint Semiconductor. There is huge interest in transistors based on Gallium Nitride in recent years due to its high breakdown voltage and its capability to operate in High frequency applications. The load pull analysis is carried out to obtain both the required source and load impedances. The
power amplifier with over 10W output power and 42% power added efficiency in the frequency range of 3-5GHz is presented in this paper. The PA is designed using a computer aided design tool called Advanced System Design (ADS).ADS provide two different simulation opportunities. These are referred as schematic simulation and
electromagnetic simulation called Momentum. Schematic Simulations are performed on the proposed PA in this paper.
Keywords:- GaN-HEMT Technology, Load pull analysis, Advanced system design(ADS)
Low Power and Fast Transient High Swing CMOS Telescopic Operational AmplifierIJERA Editor
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swing is attained by using the tail and current source-transistors in deep-linear region. The resultant deprivation
in parameters like differential gain, CMRR and added characteristics are recompensed by using regulatedcascode
differential gain enhancement and a replica-tail feedback technique. Operating at power supply of 3.3V,
the power consumption, slew rate and settling time are improved using transmission controlled pass circuitry
and level amplifier. It is shown through simulations that the Op-Amp preserves its high CMRR and unity gain
frequency.
Wideband power amplifier based on Wilkinson power divider for s-band satellit...journalBEEI
This paper presents design and simulation of wideband power amplifier based on multi-section Wilkinson power divider. Class-A topology and ATF-511P8 transistor have been used. Advanced Design System (ADS) software used to simulate the designed power amplifier. The simulation results show an input return loss (S11)<-10dB, gain (S21)>10 dB over the entire bandwidth, and an output power around 28dBm at the Centre frequency of 3GHz. The designed amplifier is stable over the entire bandwidth (K>1). Inter-modulation distortion is -65.187dBc which is less than -50dBc. The designed amplifier can be used for the microwave applications which include weather radar, satellite communication, wireless networking, mobile, and TV.
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Qualitative Analysis of Darlington Feedback Amplifier at 45nm TechnologyjournalBEEI
The transistors are the key element of present communication system having high data rate. Some applications need high gain by using very low frequency, and then transistors are used. Amplifier is the key element in many applications of present high data rate communication system such as low noise amplifier (LNA), broadband amplifier, distributed and power amplifier. The Darlington pair amplifier is analyzed for high frequency performance and related effect of bandwidth. Broadband feedback Darlington pair amplifier is designed with enhanced gain, bandwidth and slew rate. This paper presents the comparison of single stage and three stage feedback Darlington feedback amplifier with reference to gain, bandwidth and slew rate. This paper is simulated on cadence analog design environment at GPDK 45nm technology. This paper shows that increase in gain, bandwidth and slew rate of three stage Darlington feedback amplifier can show better stability over the single stage Darlington feedback amplifier.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
An Ultra-Low Power Robust Koggestone Adder at Sub-Threshold Voltages for Impl...VLSICS Design
The growing demand for energy constrained applications and portable devices have created a dire need for ultra-low power circuits. Implantable biomedical devices such as pacemakers need ultra-low power circuits for a better battery life for uninterrupted biomedical data processing. Circuits operating in subthreshold region minimize the energy per operation, thus providing a better platform for energy constrained implantable biomedical devices. This paper presents 8, 16 and 32-bit ultra-low power robust Kogge-Stone adders with improved performance. These adders operate at subthreshold supply voltages which can be used for low power implantable bio-medical devices such as pacemakers. To improve the performance of these adders in sub-threshold region, forward body bias technique and multi-threshold transistors are used. The adders are designed using NCSU 45nm bulk CMOS process library and the simulations were performed using HSPICE circuit simulator. Quantitative power-performance analysis is performed at slow-slow (SS), typical-typical (TT) and fast-fast (FF) corners clocked at 50 KHz for temperature ranging from 25̊C to 120̊C. For a supply voltage 0.3V, all the adders had the least PDP. Using 0.3V as the supply voltage, multi threshold voltage and forward body biasing techniques were applied to
further improve the performance of the adders. The PDP obtained using the forward body biasing technique shows an effective improvement compared to high threshold voltage and multi threshold voltage techniques. The forward biasing technique maintains a balance between delay reduction and increase in average power, thus reducing the power delay product when compared to the other two techniques.
AN ULTRA-LOW POWER ROBUST KOGGESTONE ADDER AT SUB-THRESHOLD VOLTAGES FOR IMPL...VLSICS Design
The growing demand for energy constrained applications and portable devices have created a dire need for
ultra-low power circuits. Implantable biomedical devices such as pacemakers need ultra-low power
circuits for a better battery life for uninterrupted biomedical data processing. Circuits operating in subthreshold
region minimize the energy per operation, thus providing a better platform for energy
constrained implantable biomedical devices. This paper presents 8, 16 and 32-bit ultra-low power robust
Kogge-Stone adders with improved performance. These adders operate at subthreshold supply voltages
which can be used for low power implantable bio-medical devices such as pacemakers. To improve the
performance of these adders in sub-threshold region, forward body bias technique and multi-threshold
transistors are used. The adders are designed using NCSU 45nm bulk CMOS process library and the
simulations were performed using HSPICE circuit simulator. Quantitative power-performance analysis is
performed at slow-slow (SS), typical-typical (TT) and fast-fast (FF) corners clocked at 50 KHz for
temperature ranging from 25̊C to 120̊C. For a supply voltage 0.3V, all the adders had the least PDP. Using
0.3V as the supply voltage, multi threshold voltage and forward body biasing techniques were applied to
further improve the performance of the adders. The PDP obtained using the forward body biasing
technique shows an effective improvement compared to high threshold voltage and multi threshold voltage
techniques. The forward biasing technique maintains a balance between delay reduction and increase in
average power, thus reducing the power delay product when compared to the other two techniques.
GENERIC SYSTEM VERILOG UNIVERSAL VERIFICATION METHODOLOGY BASED REUSABLE VERI...VLSICS Design
In this paper, we present Generic System Verilog Universal Verification Methodology based Reusable Verification Environment for efficient verification of Image Signal Processing IP’s/SoC’s. With the tight schedules on all projects it is important to have a strong verification methodology which contributes to First Silicon Success. Deploy methodologies which enforce full functional coverage and verification of corner cases through pseudo random test scenarios is required. Also, standardization of verification flow is needed. Previously, inside imaging group of ST, Specman (e)/Verilog based Verification Environment for IP/Subsystem level verification and C/C++/Verilog based Directed Verification Environment for SoC Level Verification was used for Functional Verification. Different Verification Environments were used at IP
level and SoC level. Different Verification/Validation Methodologies were used for SoC Verification across multiple sites. Verification teams were also looking for the ways how to catch bugs early in the design cycle? Thus, Generic System Verilog Universal Verification Methodology (UVM) based Reusable Verification Environment is required to avoid the problem of having so many methodologies and provides a standard unified solution which compiles on all tools.
A 28 GHz high efficiency fully integrated 0.18 µm combined CMOS power amplifi...journalBEEI
A 28 GHz power amplifier (PA) using CMOS 0.18 µm Silterra process technology for milimeter wave applications is reported. Maximizing the power added efficiency (PAE) and output power are achieved by optimize the circuit with power divider and cascade configuration. In addition, reverse body bias is also employed for realizing excellent PAE and power consumption. A three stage CMOS PA with power combiner is designed and simulated. The simulation results show that the proposed PA consumes 62.56 mW and power gain (S21) of 8.08 dB is achieved at 28 GHz. The PA achieves saturated power (Psat) of 12.62 dBm and maximum PAE of 23.74% with output 1-dB compression point (OP1dB) 10.85 dBm. These results demonstrate the proposed power amplifier architecture is suitable for 5G applications.
Design of Low Voltage Low Power CMOS OP-AMPIJERA Editor
Operational amplifiers are an integral part of many analog and mixed signal systems. As the demand for mixed
mode integrated circuits increases, the design of analog circuits such as operational amplifiers in CMOS
technology becomes more critical. This paper presents a two stage CMOS operational amplifier, which operates
at ±1.8V power supply using TSMC 0.18um CMOS technology. The OP-AMP designed exhibit unity gain
frequency of 12.6 MHz, and gain of 55.5db with 300uw power dissipation. The gain margin and phase margin
of OP-AMP is 45˚ and 60˚ respectively. Design and simulation has been carried out in P Spice tool.
Review on Design and Performance Analysis of Low Power Transceiver Circuit in...iosrjce
IOSR Journal of Electronics and Communication Engineering(IOSR-JECE) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of electronics and communication engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in electronics and communication engineering. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
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Connector Corner: Automate dynamic content and events by pushing a buttonDianaGray10
Here is something new! In our next Connector Corner webinar, we will demonstrate how you can use a single workflow to:
Create a campaign using Mailchimp with merge tags/fields
Send an interactive Slack channel message (using buttons)
Have the message received by managers and peers along with a test email for review
But there’s more:
In a second workflow supporting the same use case, you’ll see:
Your campaign sent to target colleagues for approval
If the “Approve” button is clicked, a Jira/Zendesk ticket is created for the marketing design team
But—if the “Reject” button is pushed, colleagues will be alerted via Slack message
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LF Energy Webinar: Electrical Grid Modelling and Simulation Through PowSyBl -...DanBrown980551
Do you want to learn how to model and simulate an electrical network from scratch in under an hour?
Then welcome to this PowSyBl workshop, hosted by Rte, the French Transmission System Operator (TSO)!
During the webinar, you will discover the PowSyBl ecosystem as well as handle and study an electrical network through an interactive Python notebook.
PowSyBl is an open source project hosted by LF Energy, which offers a comprehensive set of features for electrical grid modelling and simulation. Among other advanced features, PowSyBl provides:
- A fully editable and extendable library for grid component modelling;
- Visualization tools to display your network;
- Grid simulation tools, such as power flows, security analyses (with or without remedial actions) and sensitivity analyses;
The framework is mostly written in Java, with a Python binding so that Python developers can access PowSyBl functionalities as well.
What you will learn during the webinar:
- For beginners: discover PowSyBl's functionalities through a quick general presentation and the notebook, without needing any expert coding skills;
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Generating a custom Ruby SDK for your web service or Rails API using Smithyg2nightmarescribd
Have you ever wanted a Ruby client API to communicate with your web service? Smithy is a protocol-agnostic language for defining services and SDKs. Smithy Ruby is an implementation of Smithy that generates a Ruby SDK using a Smithy model. In this talk, we will explore Smithy and Smithy Ruby to learn how to generate custom feature-rich SDKs that can communicate with any web service, such as a Rails JSON API.
Smart TV Buyer Insights Survey 2024 by 91mobiles.pdf91mobiles
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Accelerate your Kubernetes clusters with Varnish CachingThijs Feryn
A presentation about the usage and availability of Varnish on Kubernetes. This talk explores the capabilities of Varnish caching and shows how to use the Varnish Helm chart to deploy it to Kubernetes.
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The UiPath Test Manager overview with SAP heatmap webinar offers a concise yet comprehensive exploration of the role of a Test Manager within SAP environments, coupled with the utilization of heatmaps for effective testing strategies.
Participants will gain insights into the responsibilities, challenges, and best practices associated with test management in SAP projects. Additionally, the webinar delves into the significance of heatmaps as a visual aid for identifying testing priorities, areas of risk, and resource allocation within SAP landscapes. Through this session, attendees can expect to enhance their understanding of test management principles while learning practical approaches to optimize testing processes in SAP environments using heatmap visualization techniques
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1. Insights into SAP testing best practices
2. Heatmap utilization for testing
3. Optimization of testing processes
4. Demo
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Execution from the test manager
Orchestrator execution result
Defect reporting
SAP heatmap example with demo
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UI automation Sample
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State of ICS and IoT Cyber Threat Landscape Report 2024 previewPrayukth K V
The IoT and OT threat landscape report has been prepared by the Threat Research Team at Sectrio using data from Sectrio, cyber threat intelligence farming facilities spread across over 85 cities around the world. In addition, Sectrio also runs AI-based advanced threat and payload engagement facilities that serve as sinks to attract and engage sophisticated threat actors, and newer malware including new variants and latent threats that are at an earlier stage of development.
The latest edition of the OT/ICS and IoT security Threat Landscape Report 2024 also covers:
State of global ICS asset and network exposure
Sectoral targets and attacks as well as the cost of ransom
Global APT activity, AI usage, actor and tactic profiles, and implications
Rise in volumes of AI-powered cyberattacks
Major cyber events in 2024
Malware and malicious payload trends
Cyberattack types and targets
Vulnerability exploit attempts on CVEs
Attacks on counties – USA
Expansion of bot farms – how, where, and why
In-depth analysis of the cyber threat landscape across North America, South America, Europe, APAC, and the Middle East
Why are attacks on smart factories rising?
Cyber risk predictions
Axis of attacks – Europe
Systemic attacks in the Middle East
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https://sectrio.com/resources/ot-threat-landscape-reports/sectrio-releases-ot-ics-and-iot-security-threat-landscape-report-2024/
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G011124753
1. IOSR Journal of Electrical and Electronics Engineering (IOSR-JEEE)
e-ISSN: 2278-1676,p-ISSN: 2320-3331, Volume 11, Issue 1 Ver. II (Jan. – Feb. 2016), PP 47-53
www.iosrjournals.org
DOI: 10.9790/1676-11124753 www.iosrjournals.org 47 | Page
Design and Simulation of an Operational Amplifier with High
Gain and Bandwidth for Switched Capacitor Filters
Amin Teimoori1
Mahdi Vadizadeh2
JamshidMohammadiAchmoush1
1
(Department of Electrical Engineering, Miyaneh Branch, Islamic Azad University, Miyaneh, Iran)
2
(Department of Electrical Engineering, Abhar Branch, Islamic Azad University, Abhar, Iran)
Abstract: Operational amplifiers can be found in buffer, adder, comparator, negative impedance converter,
and integrator and differentiator circuits. In fact, operational amplifiers are basic blocks of analog and digital
circuits. In this article, a single-stage operational amplifier with CMOS 180nm technology was designed. The
amplifier was simulated with the help of HSPICE. Gain Boosting (GB) technique was used to increase the
amplifier gain. The simulation results showed an increase of 88% in the gain after applying GB technique. The
amplifier bandwidth was about 1.17 GHz which was much higher than amplifiers with the same gain. A high-
pass filter with a cutoff frequency of 3 dB-10 MHz was designed using the proposed amplifier.
Keywords: Operational amplifier, swing, switched capacitor filter, Gain Boosting technique
I. Introduction
High gain and bandwidth amplifiers are required in integrated analog circuits such as switched
capacitor filters, Delta Sigma modulators, and analog-to-digital converters to guarantee the accuracy and speed
of the system. The speed and accuracy of an amplifier are characterized by its large signal behavior. Fast settling
time means a high unit gain frequency. On the other hand, accuracy is achieved with a high DC gain [1].
Realization of amplifier structures is a practical challenge and needs a compromise between gain, bandwidth,
swing, etc. Different structures, each with several advantages and disadvantages, have been proposed for
amplifiers. Due to intrinsic low gain of short channel transistors, it is difficult to achieve a high gain using
conventional topologies [1]. To overcome this problem, the proposed methods are applied on the main body of
amplifiers to improve specifications [2, 3]. Gain Boosting (GB) technique is one of the methods to increase the
gain. This technique improves DC gain of an amplifier without affecting the speed by adding a sub-circuit in the
output stage cascode transistors. Accordingly, the amplifier gain is improved by increasing the output
impedance. In this method, high-frequency behavior of a single-stage amplifier is combined with the high-gain
of a multistage amplifier [4]. The aim of the present study is to design a high gain and bandwidth amplifier to be
used in a switched capacitor filter. Various types of amplifiers are discussed in Section 2. In the third section,
the design method and GB technique used in this topology and the structure of switched capacitor filter are
discussed. Simulation results are presented in Section 4. The conclusions are presented in the last section.
II. Theoretical Background
Generally, a transistor with a load on its output can be used as an amplifier. However, different
applications require amplifiers with different specifications. Depending on the application, gain, bandwidth,
power consumption, swing and other parameters become more important. Thus, various structures have been
proposed as basic topologies in the design of amplifiers [5]. The simplest type of amplifier is shown in Figure 1.
This structure is known as the fastest amplifier with maximum bandwidth and minimum gain [5]. The gain for
this amplifier is calculated from equation (1) [5].
Av = 𝑔 𝑚𝑁 × 𝑅 𝑜𝑢𝑡 = 𝑔 𝑚𝑁 × (𝑟𝑂𝑁 ||𝑟𝑂𝑃 ) (1)
where Av is gain, gmn transistor transconductance, and Rout is output resistance. Because of low number of output
transistors, this structure will have a maximumswing. Swing in this structure is calculated from:
S𝑤𝑖𝑛𝑔 = 2 × 𝑉𝐷𝐷 − 𝑉𝑜𝑑 ,𝑛1 − 𝑉𝑜𝑑 ,𝑠𝑠 − 𝑉𝑜𝑑 ,𝑝1
(2)
where VDD is DC voltage of amplifier and Vod,n1, Vod,p1, 𝑉𝑜𝑑 ,𝑠𝑠 are effective voltages of transistors n1, p1, and the
current source, respectively.
This structure is not suitable for common applications and needs some modifications. The first solution
is to use series of transistors in the output. This structure is known as cascode structure. Cascode transistors
increase output resistance and significantly improve the amplifier gain [5].
In this structure, gain significantly increases. However, bandwidth is much reduced as compared with the single-
stage structure because of smaller dominant pole. Cascode amplifiers are fast, but swing is significantly reduced
because of adding transistors to increase the output impedance. Accordingly, they are not suitable in
applications with low supply voltage. So, the main disadvantage of this structure is limited swing [5].
2. Design And Simulation Of An Operational Amplifier With High Gain And Bandwidth For Switched…
DOI: 10.9790/1676-11124753 www.iosrjournals.org 48 | Page
VBias
Vin+ Vin-
VDD
VBias
Vout
Mp1 Mp2
Mn1 Mn2
Mss
Figure 1: Single-stage amplifier
To increase the swing of cascade structure, folded cascode structure has been proposed [5]. In this
method, by eliminating the transistor of cascode sequence, the number of cascode transistors in the output is
reduced and thus swing increases by the effective voltage of a transistor [4]. By folding the output stage,
cascode transistors are not located on input transistors. As a result, the input voltage range is larger than that in
cascode structure. This structure can be used with low voltage sources in the case where the output voltage has a
high swing. In addition, the input and output common mode levels can be equally adjusted. The voltage gain of
this structure is less than cascode amplifier. Folded cascode amplifiers are slower than telescopic amplifie rs.
Despite their many advantages, folded cascode amplifiers suffer from higher power losses, lower voltage gains
and more noises [6].
However, in cases where a higher swing is required, this structure is the first choice and is widely used
for the same reason [6].
Increasing gain in single-stage operational amplifiers will reduce the output voltage range. To solve
this problem, a two-stage topology can be used in which the first stage increases the gain and the second stage
increases the range of output voltage. Increasing the number of stages increases the gain and at the same time
leads to a complicated circuit with a lower speed [7].
Thus, multistage structures must be used to achieve a high gain. Multistage amplifiers are fast, but have
a complicated circuit structure with much more power consumption. Table 1 compares the amplifiers presented
in this section [5].
The structure of an amplifier is selected based on objective requirements in accordance with Table 1.
For switched capacitor filters with high bandwidths, cascode or folded cascode amplifier can be used. Single-
stage structure is not suitable due to very low gain. Despite the high gain of two-stage structure, it is unable to
provide the required bandwidth [8].
Table 1: Comparison of amplifiers with different structures
GainBandwidthSwingStructure
LowVery highVery highSingle-stage
HighModerateLowCascode
ModerateHighModerateFolded
cascode
Very highLowVery highTwo-stage
III. Amplifier Design
According to Second II, the optimal structure was to be selected first. For a switched capacitor filter, an
amplifier with high gain and bandwidth is desirable. On the other hand, the system speed should also be
acceptable. As a result, a structure with a proper settling time should be designed. All these requirements cannot
be satisfied. However, a compromise must be made between the above parameters. The differential structure is a
very good choice due to its unique characteristics [9].
3. Design And Simulation Of An Operational Amplifier With High Gain And Bandwidth For Switched…
DOI: 10.9790/1676-11124753 www.iosrjournals.org 49 | Page
3.1. Folded Cascode Amplifier
This amplifier has a moderate gain and bandwidth. But in low voltage applications, it is preferred to
use this structure because of high swing. On the other hand, the input dynamic range in this structure is larger.
Power loss is one of disadvantages of this structure. To decrease power loss, the branches connected to the
source are located on the bottom. As a result, the dominant pole is closer to the source and therefore the
bandwidth will be affected [10]. Figure 2 shows the optimal structure of amplifier.
VDD
VBias
Vout
VBias
VBias
Mp1
Mp2
Mp3 Mp4
Mn3 Mn4
Mn1 Mn2
VBias
VBias
Mpss
Mpin1 Mpin2
Vin
Figure 2: Folded cascode amplifier [3]
3-2. Gain Boosting (GB) technique
In new technologies, the inherent declining gain of the amplifier due to channel length reduction causes
restrictions when high-gain amplifiers are designed. Certainly a folded cascode stage will not have a proper gain
to be used in a filter. Low gain will lead to a gain error. Increasing the gain by adding a second stage will
increase the power loss. By adding a second pole, the overall bandwidth of the system will distort. The same
factors provide the ground for research on structures with low cost and high efficiency. One of these structures
is GB technique. The main idea of this technique is shown in Figure 3 [10].
Figure 3: The main idea of Gain Boosting technique, (a) the block diagram, (b) circuit structure [10]
Adding a second stage with a gain of A increases the output resistance. The output resistance of GB is
obtained from equation (3) [10].
RO = A. gm2 ro1 ro2 (3)
where A0 is open loop gain of the amplifier block, ro1 and ro2 are respectively output resistances of input
transistor and cascode and gm2 is transconductance of cascode transistor. A transistor can be used instead of an
amplifier block. In this case, A will be the gain of transistor. The resistance of the structure shown in Fig. 3 (b)
is calculated fromequation (4).
RO = Gm RO gm2ro1 ro2 (4)
whereGmRO is the gain of additional stage. Taking into account the GB stage, the gain of folded cascode
amplifier can be obtained from equation (5)
𝐴 𝑣 = 𝑔 𝑚𝑝𝑖𝑛 𝑔 𝑚𝐴 7 𝑟𝑜𝐴 7 ||𝑟𝑜𝐴 5 (𝑔 𝑚𝑛3 + 𝑔 𝑚𝑛𝑏 3 )𝑟𝑜𝑛 3 (𝑟𝑜𝑛 1 ||𝑟𝑜𝑝𝑖𝑛 ) || 𝑔 𝑚𝐴 3 𝑟𝑜𝐴 3 ||𝑟𝑜𝐴 1 (𝑔 𝑚𝑝3 + 𝑔 𝑚𝑝𝑏 3 )𝑟𝑜𝑝1 𝑟𝑜𝑝 3
(5)
where Gm is transconductance of transistors and ro is observed resistance of the output transistors. Figure 4
shows the final structure of the proposed folded cascode amplifier with GB stage.
4. Design And Simulation Of An Operational Amplifier With High Gain And Bandwidth For Switched…
DOI: 10.9790/1676-11124753 www.iosrjournals.org 50 | Page
Figure 4: The proposed amplifier
IV. Switched Capacitor Filter
Operational amplifiers are mainly used to design switched capacitor filters. The filters are obtained by
replacing a resistance with a capacitor and two stringent switches [5]. Figure 5 shows a filter designed using the
amplifier. This is a high-pass filter of the first order with a cutoff frequency of 3 dB-10 MHz
C1
C2
+
-
VO(z)Vi(z)
-
+
φ2
φ1
φ1
φ1
φ2φ2
φ1
φ1
φ2 φ2
φ1
φ2
Ceq1
Ceq2
C1
C2
Ceq1
Ceq2
Figure 5: Differential first-order high-pass filter [11]and a sampling frequency of 100 MHz. According to
Niquest criterion, the input signal frequency is considered to be less than half the sampling frequency, i.e. less
than 50 MHz [11].
V. Simulation
The proposed amplifier with CMOS 180nm technology was simulated in HSPICE. Figure 6 shows the
frequency response of the amplifier. As can be seen, DC amplifier gain is about 76 dB. This shows an increase
of 88% compared with the frequency response of the folded cascode amplifier (Figure 7). With a significant
increase in gain, reduction in unit gain bandwidth is quite obvious. Figure 6 shows a bandwidth of 1.17 GHz for
the amplifier which is well suited for the intended use. In addition, the phase margin is close to 77 degrees
indicating the stability and proper linearity of the proposed structure.
5. Design And Simulation Of An Operational Amplifier With High Gain And Bandwidth For Switched…
DOI: 10.9790/1676-11124753 www.iosrjournals.org 51 | Page
Figure 6: Frequency response of the folded Cascode amplifier
Figure 7: Frequency response of the proposed amplifier
6. Design And Simulation Of An Operational Amplifier With High Gain And Bandwidth For Switched…
DOI: 10.9790/1676-11124753 www.iosrjournals.org 52 | Page
Figure 8: Amplifier response to step input
To calculate settling time, spin rate, and speed, amplifier response to a step input is used. Figure 8
shows the amplifier response to a step input. As can be seen, the settling time for the rising edge is lower than
the falling edge. The spin rate indicates an acceptable speed of the proposed amplifier. Table 2 compares the
results. As shown, the power loss of the proposed amplifier is significantly lower than similar amplifiers. The
spin rate is also acceptable. In addition, increased gain decreases bandwidth and this remains as a design
challenge.
Table 2: Comparing the proposed amplifier with other similar amplifiers
Proposed amplifier[7][9][11]Specifications
180180180180Technology (nm)
7668.4884110DC gain (dB)
1170247.145.12821Unit gain bandwidth (MHz)
7726.38170Phase margin (degrees)
1.5592.4997.8Power loss (mW)
1112.39853.7Settling time (nS)
10092.89735Spin rate (V/us)
Figure 9: Output of high-pass filter designed with the proposed amplifier
7. Design And Simulation Of An Operational Amplifier With High Gain And Bandwidth For Switched…
DOI: 10.9790/1676-11124753 www.iosrjournals.org 53 | Page
To ensure proper functioning in the proposed amplifier, the amplifier was used along with a high -pass
filter in Figure 5 and simulated by HSPISE. Figure 9 shows the first-order high-pass filter output. As can be
seen, this structure filters out low frequencies and passes high frequencies. However, there is a small error in the
output caused by nonlinear factors in circuit elements.
VI. Conclusion
A single-stage amplifier with high gain and bandwidth was designed and simulated for subsequent use
in switched capacitor filters. Gain Boosting (GB) technique was used to achieve a high gain in the single-stage
structure. A large phase margin was considered to increase stability of the amplifier. According to the
simulation results, gain was reasonably increased. Despite a reduction as compared with the original structure,
the bandwidth was also reasonable. A large-signal response was used to calculate the settling time for the rising
and falling edges. According to the relevant definitions, the slope of the resulting line was considered as spin
rate. The spin rate was also acceptable due to the fast rising edge in the propos ed structure. Despite the
advantages described for the proposed structure, the settling time of the falling edge is lower than the rising edge
and this drawback must be eliminated in future studies.
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