Designed a differential input and single ended output high gain (>= 85 dB) operational amplifier using CMOS 0.35um technology using a single independent current source. The amplifier was also designed to achieve a CMRR (>= 80dB), Average Slew Rate (>= 15 V/us), UGF (>= 15 MHz) & Output Voltage Swing ( >= 1.4V). The maximum power dissipation through the complete circuit including the current source branch was limited to 0.3 mW.
Of the many ways of implementing opamp in mixed mode VLSI design, two stage design is often preferred. This presentation illustrates the design process. Download for better view as it has animations
Single Stage Differential Folded Cascode AmplifierAalay Kapadia
The purpose of this project is to design a single-stage differential input and single-ended output) Amplifier. 0.35-um CMOS process and a supply voltage of 1.8 V is required in this design. The desired specifications is given. Among the single-stage topologies, the folded-cascade topology is chosen to meet the requirement for a high output swing design.
Of the many ways of implementing opamp in mixed mode VLSI design, two stage design is often preferred. This presentation illustrates the design process. Download for better view as it has animations
Single Stage Differential Folded Cascode AmplifierAalay Kapadia
The purpose of this project is to design a single-stage differential input and single-ended output) Amplifier. 0.35-um CMOS process and a supply voltage of 1.8 V is required in this design. The desired specifications is given. Among the single-stage topologies, the folded-cascade topology is chosen to meet the requirement for a high output swing design.
• Designed a single stage folded cascode op-amp which had atleast 50 dB gain and 135 MHz Unity Gain Bandwidth for the three temperature corners (typical, slow and fast), in Cadence.
• The op-amp had a phase margin of atleast 64º and an output swing of atleast 1.46 V for the temperature corners (27,-40,100).
• Designed a common mode feedback for the amplifier and achieved a common mode accuracy of 0.01 V.
Field-effect transistor amplifiers provide an excellent voltage gain with the added feature of high input impedance. They are also low-power-consumption configurations with good frequency range and minimal size and weight.
JFETs, depletion MOSFETs, and MESFETs can be used to design amplifiers having similar voltage gains.
The depletion MOSFET (MESFET) circuit, however, has a much higher input impedance than a similar JFET configuration.
DIFFERENTIAL AMPLIFIER using MOSFET, Modes of operation,
The MOS differential pair with a common-mode input voltage ,Common mode rejection,gain, advantages and disadvantages.
Field Effect Transistor, JFET, Metal Oxide Semiconductor Field Effect Transistor, Depletion MOSFET, Enhancement MoSFET, Construction, Basic operation, Regions of Operation, Drain Characteristics, Transfer Characteristics, Biasing, Non-Ideal Characteristics of E-MOSFET, DC Analysis, AC equivalent circuit and Parameters, E-MOSFET as an Amplifier, AC analysis, MOSFET as a Switch, MOSFET as a diode, MOSFET as a resistor, High frequency equivalent circuit, Miller Capacitance, Frequency Response, NMOS and CMOS inverter
• Designed a single stage folded cascode op-amp which had atleast 50 dB gain and 135 MHz Unity Gain Bandwidth for the three temperature corners (typical, slow and fast), in Cadence.
• The op-amp had a phase margin of atleast 64º and an output swing of atleast 1.46 V for the temperature corners (27,-40,100).
• Designed a common mode feedback for the amplifier and achieved a common mode accuracy of 0.01 V.
Field-effect transistor amplifiers provide an excellent voltage gain with the added feature of high input impedance. They are also low-power-consumption configurations with good frequency range and minimal size and weight.
JFETs, depletion MOSFETs, and MESFETs can be used to design amplifiers having similar voltage gains.
The depletion MOSFET (MESFET) circuit, however, has a much higher input impedance than a similar JFET configuration.
DIFFERENTIAL AMPLIFIER using MOSFET, Modes of operation,
The MOS differential pair with a common-mode input voltage ,Common mode rejection,gain, advantages and disadvantages.
Field Effect Transistor, JFET, Metal Oxide Semiconductor Field Effect Transistor, Depletion MOSFET, Enhancement MoSFET, Construction, Basic operation, Regions of Operation, Drain Characteristics, Transfer Characteristics, Biasing, Non-Ideal Characteristics of E-MOSFET, DC Analysis, AC equivalent circuit and Parameters, E-MOSFET as an Amplifier, AC analysis, MOSFET as a Switch, MOSFET as a diode, MOSFET as a resistor, High frequency equivalent circuit, Miller Capacitance, Frequency Response, NMOS and CMOS inverter
Gain improvement of two stage opamp through body bias in 45nm cmos technologyeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Differntial Input to Single Ended Output, Two stage Op-ampKarthik Rathinavel
Designed a two stage Differential Input to Single Ended Output Op-amp in Cadence. The following Simulated specifications were achieved:-
Open loop gain = 67.97 dB
Phase Margin = 75.3°
Unity Gain Frequency = 15.29 MHz
•Designed a two stage OPAMP with a current mirror amplifier and a second CS stage along with miller compensation to provide sufficient Phase margin for stability.The circuit is also provided with temperature independent self-biased startup circuit.
•Our OPAMP exhibited a gain of 82.74dB, OVSR of 1.57V, Slew rate of 9.79V/us, Phase margin of 60 deg, GBW of 18.6 MHz, CMRR of 88.473dB, Power dissipation of 0.22mW with a 1.8V power supply.
Design and Implementation of Schmitt Trigger using Operational AmplifierIJERA Editor
A Schmitt trigger is an electronic circuit, a Comparator that is used to detect whether a voltage has crossed over a given reference level. It has two stable states and is very useful as signal conditioning device. When an input waveform in the form of sinusoidal waveform, triangular waveform, or any other periodic waveform is given, the Schmitt trigger will produce a Rectangular or square output waveform that has sharp leading and trailing edges. Such fast rise and fall times are desirable for all digital circuits. The state of the art presented in the paper is the design and implementation of Schmitt trigger using operational amplifier µA-741, generating a Rectangular waveform. Furthermore, the Schmitt trigger exhibiting hysteresis is also presented in the paper. Due to the phenomenon of hysteresis, the output transition from HIGH to LOW and LOW to HIGH will take place at various thresholds.
Analysis and Characterization of Different Comparator TopologiesAalay Kapadia
Comparator is one of the most important analog circuits required in many analog integrated circuits. It is used for the comparison between two different or same electrical signals. The design of Comparator becomes an important issue when technology is scaled down. Due to the non-linear behavior of threshold voltage (VT) when technology is scaled down, performance of Comparator is affected. Many versions of comparator are proposed to achieve desirable output in sub-micron and deep sub-micron technologies. The selection of particular topology is dependent upon the requirements and application. In this paper, we have shown the implementation of different topologies in 0.5 μm technology using the Mentor Graphics Tool. We have done the pre-layout simulation of two different topologies. We have performed DC, AC and transient analysis. We have also calculated output impedance. We have prepared a comparative analysis about them.
Comparative Study of CMOS Op-Amp In 45nm And 180 Nm TechnologyIJERA Editor
In this paper we have provided a method for designing a Two Stage CMOS Operational Amplifier which operates at 1.8V power supply using Cadence Virtuoso 45nm CMOS technology. Further, designing the two stage op-amp for the same power supply using Cadence Virtuoso 180nm CMOS Technology, keeping the slew rate of the op-amp same as that 45nm technology. The trade-off curves are computed between various characteristics such as Gain, Phase Margin,GBW,3db Gain etc. and the results obtained for 45n CMOS Technology is compared with those obtained for 180nm CMOS Technology It has been demonstrated that on lowering the technology and keeping the slew rate constant, the Power dissipation decreases.
Design of a Sample and Hold Circuit using Rail to Rail Low Voltage Compact Op...IJERA Editor
This paper presents a low power high performance and higher sampling speed sample and hold circuit. The
proposed circuit is designed at 180 nm technology and has high linearity. The circuit can be used for the ADC
frontend applications and supports double sampling architecture. The proposed sample and hold circuit has
common mode range beyond rail to rail and uses two differential pairs transistor stages connected in parallel as
its input stage.
Low power low voltage operation of operational amplifiereSAT Journals
Abstract The increasing demand for high performance, battery-operated, system-on-chip (SoC) in communication and computing has shifted the focus from traditional constraints (such as area, performance, cost and reliability) to power consumption. With the increasing integration level, energy consumption has become an important issue. Consequently much effort has been put in achieving lower dissipation at all levels of the design process. Minimizing power saves energy, simplifies cooling and contributes to device longibility.The low power design can increase operation time and /or utilize a smaller size and a light-weight battery. Low voltage operation is demanded because it is desirable to use as few batteries as possible for size and weight consideration. Low voltage analog circuit design techniques considerably differ from high voltage design technique .There are so many strategies available for low voltage design. In the field of Analog electronics we generally apply ±15 V or ±12V for proper operation of operational amplifier. In this paper it is shown that if we apply ±5V, then also all the op-amp electrical parameters(such as input offset voltage, input bias current, input offset current, CMRR) maintain datasheet specification for a particular type of IC. Here LM741C IC has been chosen to represent the operation of operational amplifier at ±5V. Here MULTISIM is used for the simulation purpose and the change in the external biasing circuitry is made to meet the datasheet specification of LM741 IC. Research is needed to provide intelligent policies for careful management of the power consumption while still providing the appearance of continuous connection to system service and application. Keywords: low power, low voltage, input offset voltage, input bias current, CMRR.
A novel voltage reference without the operational amplifier and resistorsIJRES Journal
novel voltage reference has been proposed and simulated using a 0.18μm CMOS process in
this paper. A near-zero temperature coefficient voltage is achieved in virtue of the bias voltage subcirciut which
consists of two MOSFETs operating in the saturation region. The kind of bias voltage subcirciut is used to
adjust the output voltage and compensate the curvature. The output voltage is equal to the extrapolated
threshold voltage of a MOSFET at absolute zero temperature, which was about 591.5 mV for the MOSFETs we
used. The power supply rejection ratio (PSRR) is improved with three feedback loops. Although the output
voltage fluctuates with process variation, the circuit can monitor the process variation in MOSFET threshold
voltage. The simulation results show that the line regulation is 0.75 mV/V in a supply voltage range from 1.6 V
to 3.1 V and the temperature coefficient is around 10.8 ppm/℃ to 28.5 ppm/℃ at 9 different corners in a
temperature range from -20℃ to 120 ℃.
The PSRR is -70 dB at 100Hz with a supply voltage at 1.8 V, and the
layout size is 0.012mm2. The results of simulation and post layout simulation are almost the same.
N K Kaphungkui, "Two stage Cascade BJT Amplifierl", International Research Journal of Engineering and Technology (IRJET), Vol2,issue-01 March 2015. p-ISSN:2395-0056, e-ISSN:2395-0072. www.irjet.net ,published by Fast Track Publications
Abstract
Two stage BJT amplifiers for very small signal amplification is presented in this work. With maximum 20V supply voltage and 6mV peak to peak input signal, a fraction of input signal 130uV goes to the first pre amplifier stage and produces an output signal of 11.25V peak to peak at the second stage. The overall gain of the circuit is 86538 times the small signal appearing across the input terminal of the first stage. The design circuit works best for input voltage swing from 100uV peak to peak till 6 mv peak to peak signal voltage. The variation of amplifier gain wrt Vcc is also analyzed. From 7V till 20V if Vcc is varied the gain linearly increases. Maximum gain of 65.24db without output distortion is obtained when the supply voltage is 20V with the least bandwidth. Minimum gain of 31db is obtained with the least 7V voltage supply but having the highest bandwidth. The output noise voltage is from 1.6uV/Hz till 270uV/Hz as supply voltage increases. The main objective of this work is to optimized and enhanced both gain and bandwidth of the amplifier for very small and low frequency signal amplification.
- Defined the specifications and designed an architecture of the MSDAP chip that performs convolution of two signals in least possible area & power.
- Implemented a RTL model of the MSDAP chip which consists of a Controller, ALU, Memories and Serial communication Unit.
- Synthesized the design in Synopsys Design Vision and functionality was verified using the Modelsim
- Final physical design was generated using the IC Compiler.
Designed a 21b X 21b multiplier using Booth-2 algorithm by constructing schematic of decoder, partial product generation & compression and Adder (Carry Look Ahead). Performed Hspice simulation to verify the correct functionality, library characterization of assembled Netlist using Siliconsmart ACE, RTL synthesis of generated library. Timing and power consumed is analyzed through static timing analysis using Synopsys Primetime.
Designed a fully customized 128x10b SRAM by constructing schematic & virtuoso layout of memory cell array (6T cell), row & column decoder, pre-charge circuit, write circuit and sense amplifier using Cadence. Manually placed and routed all components, performed DRC & LVS debugging of constructed schematic and layout and ran PEX to generate the final Netlist, Hspice Spectre simulation of final design for verification of the correct functionality and analysis of best read, best write cycles & the worst case timing for read and write. Timing and power consumed is analyzed through STA-Primetime (Static timing Analysis)
Customizable Microprocessor design on Nexys 3 Spartan FPGA BoardBharat Biyani
- Designed a 4 stage pipelined, 16-bit customizable microprocessor in VHDL which can execute instructions (direct & memory mapped addressing modes), handle interrupts (IVT based), communicate with IO devices including keyboard and VGA monitor and facilitates with a single port BLOCK RAM for Stack, Instruction , Data & IVT memory. Keyboard and VGA controller provides input-output interface gives user flexibility of keying in the instructions through Keyboard that is interfaced with Nexys 3 through USB 2.0; VGA interface to display the output. Keyboard and VGA controllers are also coded in VHDL.
- Implemented the VHDL code on Nexys 3 Spartan FPGA board which involved simulation, synthesis and bit file generation using Xilinx ISE,programming the FPGA with Digilent Adept.
- Employed the debug mode to make the design more user friendly
- An outhouse project completed at Progressive Powercon Pvt. Ltd., Pune, India. Aim is to design and implement a low cost solar electricity generation system for household use.
- Designed DC-DC Converter, Inverter, Micro controller circuitry and some additional accessories to improve the overall performance of the system.
- PIC 16f876A is used as a microcontroller fro PWM Control. All the simulation are performed in PSIM 6.0. PCB layout is carried out in ALTIUM DESIGNER Summer 09 Software.
- Designed a standard cells with gates including Inverter, two input NAND, two Input NOR, two Input XOR, 2:1 Multiplexer, AOI22, OAI3222 and D Flip Flop with minimum area & diffusion breaks by using IBM130 nm process technology.
- Involved library characterization using NCX, RTL synthesis of VHDL code of 32 bit ALU Chip design using Synopsys Design Vision.
Compared the performance of several branch predictor types with different RAS configurations and Branch Target Buffer configurations for three individual benchmarks namely GCC,GO and ANAGRAM using the SIMPLESCALAR simulator. Cycles per instruction(CPI),Address rate and Direction rate were the parameters used to compare and draw conclusions.
Cache Design for an Alpha MicroprocessorBharat Biyani
Fine tuned the cache hierarchy of an Alpha microprocessor for three individual benchmarks namely GCC,ANAGRAM and GO by modifying various cache design parameters like cache levels, cache types ( in case of more than one level of cache), sizes, associativity, block sizes and block replacement policy. compared the performance of individual benchmarks for different configurations based on CPI and COST function.
Automated Traffic Density Detection and Speed MonitoringBharat Biyani
Designed and proposed an RF system to detect speed and traffic density with a RADAR unit in remote areas and to provide real-time monitoring of the traffic density data with a satellite link. Based on calculated parameters, required RF components from real vendors were identified. The system model is then simulated with the obtained parameters in AWR Virtual System Simulator and analyzed nominal and worst case cascaded gain, noise figure, P1dB and OIP3. The general deviation expected in these parameters was determined by performing yield analysis.
32 bit ALU Chip Design using IBM 130nm process technologyBharat Biyani
- Implemented a 32 bit Arithmetic/Logic unit in VHDL using behavioral Modeling which involves all basic ALU operations including special functionality like binary-to-grey code conversion, parity check, sum of first N numbers. Simulation is performed in ModelSim IDE.
- Involved design using Cadence (Virtuoso Layout/Schematic) and Hspice simulation of standard library cell.
- Involved library characterization using NCX, RTL synthesis of VHDL code using Synopsys Design Vision, auto placement & routing using Encounter, static timing analysis using Synopsys Primetime.
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptxR&R Consult
CFD analysis is incredibly effective at solving mysteries and improving the performance of complex systems!
Here's a great example: At a large natural gas-fired power plant, where they use waste heat to generate steam and energy, they were puzzled that their boiler wasn't producing as much steam as expected.
R&R and Tetra Engineering Group Inc. were asked to solve the issue with reduced steam production.
An inspection had shown that a significant amount of hot flue gas was bypassing the boiler tubes, where the heat was supposed to be transferred.
R&R Consult conducted a CFD analysis, which revealed that 6.3% of the flue gas was bypassing the boiler tubes without transferring heat. The analysis also showed that the flue gas was instead being directed along the sides of the boiler and between the modules that were supposed to capture the heat. This was the cause of the reduced performance.
Based on our results, Tetra Engineering installed covering plates to reduce the bypass flow. This improved the boiler's performance and increased electricity production.
It is always satisfying when we can help solve complex challenges like this. Do your systems also need a check-up or optimization? Give us a call!
Work done in cooperation with James Malloy and David Moelling from Tetra Engineering.
More examples of our work https://www.r-r-consult.dk/en/cases-en/
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Operational Amplifier Design
1. P a g e | 1
The University of Texas at Dallas
Department of Electrical Engineering
EECT 6326 ANALOG IC DESIGN
“DESIGN OF AN OPERATIONAL AMPLIFIER”
BHARAT ARUN BIYANI (2021152193)
MOINAK PYNE (2021185405)
RAVI TEJA ELESWARAPU (2021185138)
2. P a g e | 2
TABLE OF CONTENT
Sr. No. Description Page #
1 Design Specifications 3
2 Design Procedure 4
3 Design Layout 5
4 Region Testing 6
5 Measurement of GAIN, PHASE MARGIN, GBW 7
6 Measurement of CMRR 9
7 Measurement of POWER DISSIPATION 11
8 Measurement of SLEW RATE 12
9 Measurement of OUPUT VOLTAGE SWING RANGE 14
10 Summary of Simulated Values 16
11 Final Score 17
12 Conclusion 17
13 Reference 17
3. P a g e | 3
DESIGN SPECIFICATIONS
Design a differential input and single-ended output amplifier. The amplifier is to be
powered from a 1.8V power supply. The amplifier should consist of ONE current reference that
can be realized by either an ideal current source or a supply independent current source. The
current mirrors required for biasing different transistors in the amplifier can be derived from
the current mirrors. Use capacitive load as 3pF. Use CMOS 0.35-μm technology given in this
course or other relevant 0.35-μm CMOS to best meet the following specifications:
Sr. No. Parameters Value
1 Differential Voltage Gain (Avd) ≥ 85 dB
2 Output Voltage Swing- Range (OVSR = Vo(max) - Vo(min) ) ≥ 1.4 V
3 Average Slew Rate (SR) ≥ 15 V/µs
4 Common Mode Rejection Ratio (CMRR) ≥ 80 dB
5 Unity Gain-Bandwidth (GBW) ≥ 15 MHz
6 Phase Margin ( f(GBW)) ≥ 60o
7 Power Dissipation (Pdiss) ≤ 0.3 mW
Table 1: Design Specifications
Note
Average slew rate = (SR++SR-)/2
Power Dissipation including dissipation form the current reference and current mirrors.
4. P a g e | 4
DESIGN PROCEDURE
In order to achieve required gain, we need to use two-stage amplifier. We are using Two
Stage Miller Compensated Amplifier for our design.
Figure 1: A Two-Stage Miller Compensated Amplifier
On the similar page, two-stage amplifier introduces second pole which brings instability
to our system. In order to compensate this effect we need to use a capacitor (Cm), connecting
the output of the first stage and output of second stage to pull two poles away from each
other.
In addition, two-stage amplifier reduces the phase margin of our system. In order to
increase the Phase Margin (f (GBW)) we need to use a resistor (Rm), connecting the output of
the first stage and output of second stage which won’t affect the pole position.
5. P a g e | 5
DESIGN LAYOUT
Figure 2 is the schematic of our design which we implemented using Cadence. Dimensions of each
component are listed in the Table 2.
Figure 2: Design Layout
Sr. No. Device Size (W/L)
1 Differential Amplifier pMOS (M0, M1) 25µm/1µm
2 Differential Amplifier nMOS (M3, M6) 60µm/3.5µm
3 First Branch nMOS (M7) 18µm/3µm
4 Differential Amplifier tail Current Source nMOS (M4) 108µm/3µm
5 Second Stage pMOS (M2) 290µm/2µm
6 Second Stage nMOS (M5) 360µm/3µm
7 Resistor (r) 3.4 kΩ
8 Capacitor(c) 2.1pf
Table 2: Component Dimensions
6. P a g e | 6
REGION TESTING
Figure 3: Transistor Region Testing Circuit
For our design, all the transistors should be in Saturation region. In order to check this we need to
perform DC analysis. As shown in Figure 3
1. Apply 1V DC to both the input terminals (INP & INN).
2. Apply 1V AC to positive input terminal (INP). This will generate 1V AC differential voltage
between the two terminals.
3. Apply 6µA Reference Current Source (Iref) to input terminal (Ibias).
4. Apply 1.8V DC between VDD and GND terminal.
5. Check the region by choosing Result > annotation > DC operation point,.
From Figure 3, it can be seen that all the transistors are in REGION 2 which implies that they are in
SATURATION.
7. P a g e | 7
MEASUREMENT of GAIN, PHASE MARGIN, GBW
After generating a symbol view of Figure 2, we can apply the test vector to this symbol view
as shown in Figure 4 to calculate the Gain, Phase Margin and GBW.
6. Apply 1V DC to both the input terminals (INP & INN).
7. Apply 1V AC to positive input terminal (INP). This will generate 1V AC differential voltage
between the two terminals.
8. Apply 6µA Reference Current Source (Iref) to input terminal (Ibias).
9. Apply 1.8V DC between VDD and GND terminal.
10. Check the result at the OUT terminal.
Figure 4: Test Circuit to Calculate GAIN, PHASE MARGIN, GBW
8. P a g e | 8
Waveform 1: GAIN & GBW calculation
Waveform 2: PHASE MARGIN calculation
9. P a g e | 9
From the waveform 1, we get the Differential Voltage Gain (Avd) of our system as 80.13dB.
Frequency at which is Gain becomes 0dB is Unity Gain-Bandwidth (GBW). From
waveform 1, we get the Unity Gain-Bandwidth (GBW) of our system as 19.26MHz.
We know the Phase at Unity Gain-Bandwidth (GBW) is nothing but the Phase Margin
(PM). From waveform 2, we get the Phase as -119.4 o at 19.26MHz which is GBW of our system
from waveform 1.But as the waveform 2 starts from 0 o, the actual Phase Margin (PM) is,
Phase Margin (PM) = 180o - 119.4 o = 60.6 o
Hence, we get Phase Margin (PM) of our system as 60.6 o.
Measurement of CMRR
A good differential amplifier generally has very low common mode gain such that even
drastic common mode variations are not very significant. The output is purely generated by the
comparative conditions of the symmetric circuits and this depresses the disturbances giving a
faithful output.
Common mode Rejection ratio (CMRR) is difference between the differential voltage
gain (Avd) and common mode voltage gain (Av_cm) in dB.
After generating a symbol view of Figure 2, we can apply the test vector to this symbol view as
shown in Figure 5 to calculate Common Mode Voltage Gain (Av_cm). We already know the
Differential Voltage Gain (Avd) of our system as 80.13dB.
1. Apply 1V DC to both the input terminals (INP & INN).
2. Apply 1V AC to both the input terminals (INP & INN). This will generate a 1V AC common
mode voltage between the two terminals.
3. Apply 6µA Reference Current Source (Iref) to input terminal (Ibias).
4. Apply 1.8V DC between VDD and GND terminal.
5. Check the result at the OUT terminal.
10. P a g e | 10
Figure 5: Test Circuit to calculate COMMON MODE VOLATGE GAIN (Av_cm)
Waveform 3: COMMON MODE VOLATGE GAIN (Av_cm) calculation
11. P a g e | 11
Form Waveform 3, we get the COMMON MODE VOLTAGE GAIN (Av_cm) as -5.4 dB. So,
CMRR = Differential Voltage Gain (in dB) - COMMON MODE VOLTAGE GAIN (in dB)
= 80.13 dB – (- 5.4 dB) = 85.53 dB.
Hence, we get Common Mode Rejection Ratio (CMRR) of our system as 85.53 dB.
MEASUREMENT OF POWER DISSIPATION
Power Dissipation (Pdiss) in the circuit is product of voltage and current. As we have
three branches in our design, Power Dissipation is nothing but the supply voltage multiplied by
the total current through the circuit (sum of currents from all the branches).We knows that our
supply voltage is 1.8V. In order to calculate total current, we need to perform DC analysis.
After generating a symbol view of Figure 2, we can apply the test vector to this symbol
view as shown in Figure 6 to calculate total current in circuit.
Figure 6: Test Circuit to calculate Power Dissipation (Pdiss)
12. P a g e | 12
Choose the Result > annotation > DC operation point, it can clearly show the total current
through our system is -165.3uA. This can be clearly seen from figure 4. So,
Power Dissipation (Pdiss) = Voltage * Current.
= 1.8V * 165.3µA = 297.54W
Hence, we get Power Dissipation (Pdiss) of our system as 297.54W or 0.29754mW.
MEASUREMENT OF SLEW RATE
Slew Rate (SR) is how fast output changes with respect to input. The slope of output
voltage (dVo/dt) is defined as the Slew Rate (both positive and negative). Slew Rate should be as
high as possible which denotes that the output voltage waveform follows the input voltage
waveform more closely. In order to calculate Slew Rate we need to perform transient analysis.
After generating a symbol view of Figure 2, we can apply the test vector to this symbol view
as shown in Figure 7 to calculate Average Slew Rate of the circuit.
1. Connect the negative input terminal (INN) to the output terminal (OUT).
2. Apply a Pulse Voltage to the positive input terminal (INP) with below specification.
Pulse Width = 200ns, Period = 400ns, V1 = 0V, V2= 1.8V.
(Note that above specification we have used for our design to generate the Pulse voltage)
3. Apply 6µA Reference Current Source (Iref) to input terminal (Ibias).
4. Apply 1.8V DC between VDD and GND terminal.
5. Check the result at the OUT terminal.
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Figure 7: Test Circuit to calculate Slew Rate (SR)
Waveform 4: SLEW RATE calculation
14. P a g e | 14
We need to calculate positive slew rate and negative slew rate, in other words positive
slope and negative slope. As seen from the waveform 4-
Positive Slope or Positive Slew Rate (SR+) = (1.542-0.4485)/ (0.4699-0.4106) V/µs = 18.44 V/µs
Negative Slope or Negative Slew Rate (SR-) = (1.654-0.6477)/ (0.618-0.6953) V/µs = 13.018 V/µs
(Neglected negative sign for Negative Slope or Negative Slew Rate)
So,
Average slew rate = (SR++SR-)/2
= (18.44 + 13.018)/2 = 15.729 V/µs
Hence, we get Average Slew Rate (SR) of our system as 15.729 V/µs.
MEASUREMENT OF OUPUT VOLATGE SWING RANGE
Output Voltage Swing range is the difference between the maximum and the minimum
value that can be achieved by the output voltage.
Figure 8: Test Circuit to calculate Output Voltage Swing Range (OVSR)
15. P a g e | 15
Waveform 5: Output Voltage Swing Range calculation
16. P a g e | 16
After generating a symbol view of Figure 2, we can apply the test vector to this symbol view
as shown in Figure 8 to calculate Output Voltage Swing Range (OVSR) of the circuit.
1. Apply a variable DC from 0 V to 1.8 V to the positive input terminals (INP).
2. Apply 1V DC to negative input terminal (INN) through a 1KΩ resistor.
3. Output terminal (OUT) is connected to the input terminal through a 10KΩ resistor.
4. Apply 6µA Reference Current Source (Iref) to input terminal (Ibias).
5. Apply 1.8V DC between VDD and GND terminal.
6. Check the result at the OUT terminal.
From waveform 5, the bottom plot is the derivative of the top plot. The derive value on the
bottom plot shows the rising point and falling point of the output when input values are
0.9003V and 1.045V respectively. Thus we can find out the same input voltage value on the top
plot and check out the output voltage value which is 64.52mV and 1.488V respectively. So,
Output Voltage Swing Range (OVSR) = Vo (max) – Vo (min)
= 1.488 V – 64.52mV = 1.42348 V
Hence, we get Output Voltage Swing Range (OVSR) of our system as 1.42348 V.
SUMMARY OF SIMULATED VALUES
PARAMETER VALUE
Differential Voltage Gain (Avd ) 80.13 dB
Output Voltage Swing Range (OVSR) 1.42348V
Slew Rate (SR) 15.729 V/µs
Common Mode Rejection Ratio (CMRR) 85.53 dB
Unity Gain-Bandwidth (GBW) 19.26MHz
Phase Margin, f(GBW) 60.6 o
Power Dissipation (Pdiss) 0.29754mW
Table 3: Simulated Results
17. P a g e | 17
FINAL SCORE
Avd(dB) OVSR(V) SR(V/µs) CMRR(dB) GBW(MHz) PM(deg) Pdiss(mW)
Required ≥ 85 dB ≥ 1.4 V ≥ 15 V/µs ≥ 80 dB ≥ 15 MHz ≥ 60o ≤ 0.3mW
Actual 80.13 dB 1.42348V 15.729 V/µs 85.53 dB 19.26MHz 60.6 o 0.29754mW
Score 14.14 10 20 10 20 10 15
Table 4: Final Score for individual parameters
Score Formula = min[15,15(
𝐴𝑣𝑑
85𝑑𝐵
)] + min[10,10(
𝑂𝑉𝑆𝑅
1.4𝑉
)] + min[20,20(
𝑆𝑅
15𝑉/𝑢𝑠
)] +
min[10,10(
𝐶𝑀𝑅𝑅
80𝑑𝐵
)] + min[20,20(
𝐺𝐵𝑊
15𝑀𝐻𝑧
)] + min[10,10(
𝑃𝑀
60
)] + min[15,15(
0.3𝑚𝑊
𝑃𝑑𝑖𝑠𝑠
)]
Final Score = 99.14
CONCLUSION
The developed Operational Amplifier using “Two-Stage Compensated Amplifier” design
met all the specifications except Gain. The gain has been sacrificed to avoid huge sizing of the
transistors.
REFERENCES
[1] B. Razavi, Design of Analog CMOS Integrated Circuits, New York: Tata-McGraw Hill, 2002.
[2] H. Lee, Class notes, EE6326 – Spring 2014, University of Texas, Dallas, 2014