This summary provides the key details about the design of a two-stage CMOS operational amplifier:
- The design uses a classical two-stage op amp configuration with PMOS input transistors and Miller compensation with a nulling resistor. An analytical approach is used to determine the design parameters to meet specifications for gain, bandwidth, phase margin, and other factors.
- The current mirrors are first designed to provide the appropriate drain currents for each gain stage. Then the parameters for the differential input stage, second gain stage, active load stage, and compensation are determined analytically.
- Minor modifications based on SPICE simulations are made to achieve all specifications, which are verified in simulation results. The analytical design meets all
This report details the design of a two-stage operational amplifier (op-amp) in Cadence. It begins with hand calculations of component parameters. A schematic is plotted and simulated for DC and AC analysis. The initial design does not meet specifications, so component parameters are modified through several iterations until specifications are met. Finally, geometry optimization using Mosek in MATLAB is presented, though long calculation times prevented results. The report demonstrates the op-amp design process from initial calculations through simulation and optimization to meet specifications.
Of the many ways of implementing opamp in mixed mode VLSI design, two stage design is often preferred. This presentation illustrates the design process. Download for better view as it has animations
Differntial Input to Single Ended Output, Two stage Op-ampKarthik Rathinavel
This document summarizes a project to design a differential input, single ended output two-stage operational amplifier. The design approach was to bring all transistors into saturation at a common mode voltage of 0V and meet gain, phase margin, and unity gain frequency specifications. A compensation capacitor was increased to move the dominant pole in while a nulling resistor eliminated the effect of a zero, improving phase margin and unity gain frequency. Simulation results met all specifications, with an open loop gain of 67.97dB, phase margin of 75.3 degrees, and unity gain frequency of 15.29MHz. The input common mode range was -0.852V to 0.181V and output swing was -0.771V to 0
This document presents a new CMOS voltage divider based current mirror and compares it to basic and cascode current mirrors. The basic current mirror has limitations like finite output resistance and channel length modulation effects. The cascode current mirror improves output resistance but wastes threshold voltage. The new CMOS voltage divider current mirror uses an NMOS and PMOS transistor voltage divider to bias an NMOS transistor and control the output current. It consumes less power than the basic current mirror and is well-suited for low current biasing applications.
A NAND gate is a digital logic gate that implements logical negation on two input operands. If both inputs to a NAND gate are high, the output will be low. However, if one or both inputs are low, the output will be high. NAND gates are commonly used in digital circuits because any boolean function can be implemented using only NAND gates.
The document discusses operational amplifiers (op-amps) and differential amplifiers. It provides details on the basic requirements and characteristics of op-amps such as high gain, differential inputs, and high input/low output impedance. It describes the typical internal structure of an op-amp including differential, gain, and output stages. Ideal op-amp assumptions and linear op-amp operation in inverting and non-inverting configurations are also covered. The document then discusses differential amplifiers, including their advantages and applications in analog circuits. It provides details on a proposed CMOS differential amplifier design and its high common-mode rejection ratio.
This report details the design of a two-stage operational amplifier (op-amp) in Cadence. It begins with hand calculations of component parameters. A schematic is plotted and simulated for DC and AC analysis. The initial design does not meet specifications, so component parameters are modified through several iterations until specifications are met. Finally, geometry optimization using Mosek in MATLAB is presented, though long calculation times prevented results. The report demonstrates the op-amp design process from initial calculations through simulation and optimization to meet specifications.
Of the many ways of implementing opamp in mixed mode VLSI design, two stage design is often preferred. This presentation illustrates the design process. Download for better view as it has animations
Differntial Input to Single Ended Output, Two stage Op-ampKarthik Rathinavel
This document summarizes a project to design a differential input, single ended output two-stage operational amplifier. The design approach was to bring all transistors into saturation at a common mode voltage of 0V and meet gain, phase margin, and unity gain frequency specifications. A compensation capacitor was increased to move the dominant pole in while a nulling resistor eliminated the effect of a zero, improving phase margin and unity gain frequency. Simulation results met all specifications, with an open loop gain of 67.97dB, phase margin of 75.3 degrees, and unity gain frequency of 15.29MHz. The input common mode range was -0.852V to 0.181V and output swing was -0.771V to 0
This document presents a new CMOS voltage divider based current mirror and compares it to basic and cascode current mirrors. The basic current mirror has limitations like finite output resistance and channel length modulation effects. The cascode current mirror improves output resistance but wastes threshold voltage. The new CMOS voltage divider current mirror uses an NMOS and PMOS transistor voltage divider to bias an NMOS transistor and control the output current. It consumes less power than the basic current mirror and is well-suited for low current biasing applications.
A NAND gate is a digital logic gate that implements logical negation on two input operands. If both inputs to a NAND gate are high, the output will be low. However, if one or both inputs are low, the output will be high. NAND gates are commonly used in digital circuits because any boolean function can be implemented using only NAND gates.
The document discusses operational amplifiers (op-amps) and differential amplifiers. It provides details on the basic requirements and characteristics of op-amps such as high gain, differential inputs, and high input/low output impedance. It describes the typical internal structure of an op-amp including differential, gain, and output stages. Ideal op-amp assumptions and linear op-amp operation in inverting and non-inverting configurations are also covered. The document then discusses differential amplifiers, including their advantages and applications in analog circuits. It provides details on a proposed CMOS differential amplifier design and its high common-mode rejection ratio.
This document discusses the design of MEMS resonator systems with integrated readout circuitry. It first describes methods for extracting the threshold voltage of MOSFETs. It then covers the design of a differential amplifier, including determining its transconductance, voltage transfer characteristics, input common mode range, slew rate and frequency response. Next, it examines modeling an electromechanical nanocantilever sensor for mass detection. It provides equations for calculating small mass changes and the snap-in voltage of the cantilever-driver system. Finally, it presents the design process and SPICE simulation of a two-stage operational amplifier.
This document discusses transmission line propagation coefficients including reflection coefficient and transmission coefficient. It defines the reflection coefficient as the ratio of reflected to incident voltage or current. Reflection and transmission coefficients are derived for a transmission line terminated by a load impedance. Standing wave patterns on transmission lines are also analyzed. Key properties of standing waves include maximum and minimum voltages occurring at intervals of half wavelength and voltages/currents being 90 degrees out of phase.
Current sources, current mirrors, and current steering circuits are important components in integrated circuit design for providing stable bias currents. A constant current is first generated and then replicated across the circuit using current mirrors. Current mirrors use identical MOS transistors such that if the gate-source potentials are equal, the drain currents will be equal, allowing the reference current to be copied. There are various types of current mirror circuits that have different advantages and applications. Current can also be steered between paths using multiple current mirrors, with some mirrors acting as current sources and others as current sinks.
The document discusses the MOS transistor and its operation. It begins by describing the components and structure of the MOS transistor, including the polysilicon gate, aluminum contacts, and silicon dioxide layer. It then discusses the energy band diagrams and how applying different gate voltages results in accumulation, depletion, or inversion at the surface. The document also covers the threshold voltage, its dependence on factors like doping and oxide thickness, and its impact on MOSFET operation. It concludes by deriving the MOSFET drain current equation using the gradual channel approximation approach.
IC Design of Power Management Circuits (II)Claudia Sin
The document discusses various aspects of integrated circuit design for power management circuits. It covers control loop design including biasing circuits, oscillators, comparators and operational amplifiers. It also discusses power stage design such as power transistors, synchronous rectification and active diodes. Finally it discusses peripheral circuits including undervoltage lockout, overcurrent protection and soft start circuits. The document provides guidelines and examples for analog integrated circuit design of switching converters and related circuits.
Delay Calculation in CMOS Chips Using Logical Effort by Prof. Akhil MasurkarAkhil Masurkar
1) The document discusses using logical effort to estimate delay in CMOS chips. Logical effort allows estimating delay without simulating specific transistor sizes.
2) Delay has two components - effort delay proportional to load and parasitic delay independent of load. Effort delay depends on logical effort and electrical effort.
3) Logical effort measures a gate's ability to source current relative to an inverter. Electrical effort is the ratio of output to input capacitance.
This document describes the implementation of a bandgap reference circuit. It begins by acknowledging those who supported the project. It then provides an abstract stating that bandgap reference circuits are used to generate stable reference voltages and currents on integrated circuits. The main goal of the project was to understand bandgap reference design and limitations, and implement a bandgap reference circuit in a 90nm CMOS technology using CADENCE.
I have prepared it to create an understanding of delay modeling in VLSI.
Regards,
Vishal Sharma
Doctoral Research Scholar,
IIT Indore
vishalfzd@gmail.com
This document provides an overview of operational amplifier (op amp) circuit topologies and their analysis. It discusses various op amp configurations including single-stage, two-stage, telescopic cascode, folded cascode, and gain-boosting topologies. It analyzes each configuration's characteristics such as gain, bandwidth, output swing, and noise performance. Example circuits are provided and design considerations like biasing, common-mode range, and dominant pole locations are examined.
The document summarizes the operation of a CMOS transmission gate (TG). A TG consists of a parallel nMOS and pMOS transistor that act as a bidirectional switch controlled by complementary signals on the gates. When the control input is high, both transistors are off and the TG acts as a high impedance state. When the control input is low, one transistor is on providing a conduction path from input to output. The document further analyzes the DC characteristics of a TG under different bias conditions.
This document provides an overview of sigma-delta analog to digital converters (ΣΔADCs). It begins with outlining the basic principles of oversampling and noise shaping. It then discusses the effects of noise shaping on total noise for first and second order modulators. Additional topics covered include issues in modulator design, continuous and discrete time realizations, the inherent anti-aliasing property of continuous time modulators, and the effect of quantizer bits. Loop filter architectures and multi-stage cascaded modulators are also summarized. The document concludes with a design example specifying the parameters for a second order modulator.
This document describes the design of a low dropout voltage regulator (LDO) circuit. It includes the goals of providing a 3.3V output voltage from a 5V input. The key components of an LDO - pass transistor, error amplifier, and voltage reference - are discussed. Calculations are shown for efficiency, transistor sizes, setting the bias voltage, and sizing additional transistors. A block diagram and final schematic are presented. Post-layout simulations demonstrate the line regulation as the input voltage is changed.
The document describes the design of a folded cascode operational amplifier. Key points:
- The goal is to design an op-amp with over 80dB gain, 10MHz bandwidth, 5V/us slew rate, and other specs using a folded cascode topology.
- Hand calculations are shown for determining device sizes to meet the gain, bandwidth, and slew rate specs.
- Simulation results show a gain of 17.5k, 604.7Hz bandwidth, and 3.5V/us slew rate, meeting most but not all specs.
- Analysis discusses the pros and cons of this topology, noting the difficulty of achieving high slew rate and the narrow input/
The document discusses MOSFETs (metal-oxide-semiconductor field-effect transistors). It provides information on:
1) The structure of MOSFETs including typical dimensions of the gate length and width. It operates by using a voltage applied to the gate to control the conductivity between the drain and source.
2) The operation of n-channel and p-channel MOSFETs. In an n-channel MOSFET, applying a positive voltage to the gate creates an n-type inversion channel between the source and drain allowing current to flow.
3) Biasing techniques for MOSFET amplifiers including fixing the gate voltage, connecting a resistor in the source,
The document discusses feedback amplifiers and the concepts of positive and negative feedback. It states that negative feedback reduces amplifier gain but provides benefits like lower distortion, increased stability and improved input/output impedances. Feedback can be connected in either voltage or current series/shunt configurations, each affecting the input and output impedances differently. Negative feedback also increases an amplifier's bandwidth and makes its gain less sensitive to component variations. The Barkhausen criterion for oscillation is that the open-loop gain must be unity with a phase shift of 0° or 360° around the feedback loop.
Designed a differential input and single ended output high gain (>= 85 dB) operational amplifier using CMOS 0.35um technology using a single independent current source. The amplifier was also designed to achieve a CMRR (>= 80dB), Average Slew Rate (>= 15 V/us), UGF (>= 15 MHz) & Output Voltage Swing ( >= 1.4V). The maximum power dissipation through the complete circuit including the current source branch was limited to 0.3 mW.
The document discusses the structure and operation of MOS transistors. It describes the basic MOS structure which consists of a metal gate separated from a semiconductor substrate by an oxide layer. Applying a voltage to the gate can induce an inversion layer in the semiconductor to form a channel between the source and drain, allowing current to flow. The threshold voltage is the minimum gate voltage required to form an inversion layer. The document discusses n-channel MOSFETs and their characteristics in different regions of operation defined by the gate-source voltage.
This document introduces high speed operational amplifiers, including voltage feedback (VFB) and current feedback (CFB) types. It discusses key differences in bandwidth, distortion, and input impedance between VFB and CFB op amps. The document recommends some high speed op amp models from Analog Devices and provides application examples, stability analysis, and noise considerations for high speed op amp circuit design.
This document discusses the design of MEMS resonator systems with integrated readout circuitry. It first describes methods for extracting the threshold voltage of MOSFETs. It then covers the design of a differential amplifier, including determining its transconductance, voltage transfer characteristics, input common mode range, slew rate and frequency response. Next, it examines modeling an electromechanical nanocantilever sensor for mass detection. It provides equations for calculating small mass changes and the snap-in voltage of the cantilever-driver system. Finally, it presents the design process and SPICE simulation of a two-stage operational amplifier.
This document discusses transmission line propagation coefficients including reflection coefficient and transmission coefficient. It defines the reflection coefficient as the ratio of reflected to incident voltage or current. Reflection and transmission coefficients are derived for a transmission line terminated by a load impedance. Standing wave patterns on transmission lines are also analyzed. Key properties of standing waves include maximum and minimum voltages occurring at intervals of half wavelength and voltages/currents being 90 degrees out of phase.
Current sources, current mirrors, and current steering circuits are important components in integrated circuit design for providing stable bias currents. A constant current is first generated and then replicated across the circuit using current mirrors. Current mirrors use identical MOS transistors such that if the gate-source potentials are equal, the drain currents will be equal, allowing the reference current to be copied. There are various types of current mirror circuits that have different advantages and applications. Current can also be steered between paths using multiple current mirrors, with some mirrors acting as current sources and others as current sinks.
The document discusses the MOS transistor and its operation. It begins by describing the components and structure of the MOS transistor, including the polysilicon gate, aluminum contacts, and silicon dioxide layer. It then discusses the energy band diagrams and how applying different gate voltages results in accumulation, depletion, or inversion at the surface. The document also covers the threshold voltage, its dependence on factors like doping and oxide thickness, and its impact on MOSFET operation. It concludes by deriving the MOSFET drain current equation using the gradual channel approximation approach.
IC Design of Power Management Circuits (II)Claudia Sin
The document discusses various aspects of integrated circuit design for power management circuits. It covers control loop design including biasing circuits, oscillators, comparators and operational amplifiers. It also discusses power stage design such as power transistors, synchronous rectification and active diodes. Finally it discusses peripheral circuits including undervoltage lockout, overcurrent protection and soft start circuits. The document provides guidelines and examples for analog integrated circuit design of switching converters and related circuits.
Delay Calculation in CMOS Chips Using Logical Effort by Prof. Akhil MasurkarAkhil Masurkar
1) The document discusses using logical effort to estimate delay in CMOS chips. Logical effort allows estimating delay without simulating specific transistor sizes.
2) Delay has two components - effort delay proportional to load and parasitic delay independent of load. Effort delay depends on logical effort and electrical effort.
3) Logical effort measures a gate's ability to source current relative to an inverter. Electrical effort is the ratio of output to input capacitance.
This document describes the implementation of a bandgap reference circuit. It begins by acknowledging those who supported the project. It then provides an abstract stating that bandgap reference circuits are used to generate stable reference voltages and currents on integrated circuits. The main goal of the project was to understand bandgap reference design and limitations, and implement a bandgap reference circuit in a 90nm CMOS technology using CADENCE.
I have prepared it to create an understanding of delay modeling in VLSI.
Regards,
Vishal Sharma
Doctoral Research Scholar,
IIT Indore
vishalfzd@gmail.com
This document provides an overview of operational amplifier (op amp) circuit topologies and their analysis. It discusses various op amp configurations including single-stage, two-stage, telescopic cascode, folded cascode, and gain-boosting topologies. It analyzes each configuration's characteristics such as gain, bandwidth, output swing, and noise performance. Example circuits are provided and design considerations like biasing, common-mode range, and dominant pole locations are examined.
The document summarizes the operation of a CMOS transmission gate (TG). A TG consists of a parallel nMOS and pMOS transistor that act as a bidirectional switch controlled by complementary signals on the gates. When the control input is high, both transistors are off and the TG acts as a high impedance state. When the control input is low, one transistor is on providing a conduction path from input to output. The document further analyzes the DC characteristics of a TG under different bias conditions.
This document provides an overview of sigma-delta analog to digital converters (ΣΔADCs). It begins with outlining the basic principles of oversampling and noise shaping. It then discusses the effects of noise shaping on total noise for first and second order modulators. Additional topics covered include issues in modulator design, continuous and discrete time realizations, the inherent anti-aliasing property of continuous time modulators, and the effect of quantizer bits. Loop filter architectures and multi-stage cascaded modulators are also summarized. The document concludes with a design example specifying the parameters for a second order modulator.
This document describes the design of a low dropout voltage regulator (LDO) circuit. It includes the goals of providing a 3.3V output voltage from a 5V input. The key components of an LDO - pass transistor, error amplifier, and voltage reference - are discussed. Calculations are shown for efficiency, transistor sizes, setting the bias voltage, and sizing additional transistors. A block diagram and final schematic are presented. Post-layout simulations demonstrate the line regulation as the input voltage is changed.
The document describes the design of a folded cascode operational amplifier. Key points:
- The goal is to design an op-amp with over 80dB gain, 10MHz bandwidth, 5V/us slew rate, and other specs using a folded cascode topology.
- Hand calculations are shown for determining device sizes to meet the gain, bandwidth, and slew rate specs.
- Simulation results show a gain of 17.5k, 604.7Hz bandwidth, and 3.5V/us slew rate, meeting most but not all specs.
- Analysis discusses the pros and cons of this topology, noting the difficulty of achieving high slew rate and the narrow input/
The document discusses MOSFETs (metal-oxide-semiconductor field-effect transistors). It provides information on:
1) The structure of MOSFETs including typical dimensions of the gate length and width. It operates by using a voltage applied to the gate to control the conductivity between the drain and source.
2) The operation of n-channel and p-channel MOSFETs. In an n-channel MOSFET, applying a positive voltage to the gate creates an n-type inversion channel between the source and drain allowing current to flow.
3) Biasing techniques for MOSFET amplifiers including fixing the gate voltage, connecting a resistor in the source,
The document discusses feedback amplifiers and the concepts of positive and negative feedback. It states that negative feedback reduces amplifier gain but provides benefits like lower distortion, increased stability and improved input/output impedances. Feedback can be connected in either voltage or current series/shunt configurations, each affecting the input and output impedances differently. Negative feedback also increases an amplifier's bandwidth and makes its gain less sensitive to component variations. The Barkhausen criterion for oscillation is that the open-loop gain must be unity with a phase shift of 0° or 360° around the feedback loop.
Designed a differential input and single ended output high gain (>= 85 dB) operational amplifier using CMOS 0.35um technology using a single independent current source. The amplifier was also designed to achieve a CMRR (>= 80dB), Average Slew Rate (>= 15 V/us), UGF (>= 15 MHz) & Output Voltage Swing ( >= 1.4V). The maximum power dissipation through the complete circuit including the current source branch was limited to 0.3 mW.
The document discusses the structure and operation of MOS transistors. It describes the basic MOS structure which consists of a metal gate separated from a semiconductor substrate by an oxide layer. Applying a voltage to the gate can induce an inversion layer in the semiconductor to form a channel between the source and drain, allowing current to flow. The threshold voltage is the minimum gate voltage required to form an inversion layer. The document discusses n-channel MOSFETs and their characteristics in different regions of operation defined by the gate-source voltage.
This document introduces high speed operational amplifiers, including voltage feedback (VFB) and current feedback (CFB) types. It discusses key differences in bandwidth, distortion, and input impedance between VFB and CFB op amps. The document recommends some high speed op amp models from Analog Devices and provides application examples, stability analysis, and noise considerations for high speed op amp circuit design.
This document describes the design of a 1.8V operational amplifier in 180nm CMOS technology intended to compete with the μA741 model. A two-stage amplifier topology is proposed using a differential input stage followed by an inverting output stage. The input stage employs a PMOS differential pair with cascoded MOSFETs to increase gain, while a Miller compensation capacitor is used between stages for stability. The design aims to meet specifications for gain, bandwidth, output resistance, slew rate, voltage swing, supply voltage, and common mode rejection ratio similar to the μA741 model operational amplifier.
Ece 523 project – fully differential two stage telescopic op ampKarthik Rathinavel
• Designed a two stage op-amp with first stage as a telescopic amplifier and second stage being a common source, in Cadence.
• Simulated the loop characteristics of the amplifier to have atleast 100 MHz Unity Gain Bandwidth, 65 dB gain and 60º phase margin (both differential loop and Common Mode) for three temperature (27,-40,100) corners.
• Extracted the layout of the design in Virtuoso (after passing DRC an LVS) and simulated the differential loop performances of the extracted netlist.
• Designed a third order Butterworth filter with 100 KHz corner frequency using the op-amp.
Why the first 2 stages of Design thinking are important for a startup?Anuradha Sridharan
This document discusses the importance of the first two stages of design thinking - empathy and problem definition - for startups. It provides examples from two case studies of companies that utilized design thinking to better understand customer needs and problems. The document emphasizes spending time understanding the problem from the customer's perspective in order to identify opportunities to create value. It also stresses the importance of being open-minded during the empathy stage and allowing customer insights to shape the definition of problems to address.
Designed a Switched Capacitor Low Pass Filter with a sampling frequency of 60 Hz.
Simulated the filter to have a ripple within 0.2 dB under 3.6 MHz and a stopband attenuation of atleast -51 dB after 7.2 MHz.
Applied dynamic range optimization, Dynamic Range Scaling and Chip Area scaling to get maximum output swing while occupying minimum area on chip.
Tested the filter with non-idealities of the amplifier, such as finite gain, bandwidth, offset voltage, charge injection, etc.
Presentation includes design and testing of analog and mixed-signal integrated circuits such as an operational amplifier, 12-bit charge scaling architecture based digital-to-analog converter (DAC), 12-bit recycling architecture based analog-to-digital converter (ADC) and operational amplifier with floating gate inputs with on-chip BICS
The document discusses differential amplifiers, including their advantages, basic operation, and analysis of key parameters like differential gain, common-mode gain, and common-mode rejection ratio. It covers both MOS and BJT-based differential pairs, examining their linear and nonlinear operation. It also describes techniques to improve performance, such as using active loads and converting the differential output to a single-ended output.
Here are the steps to solve this:
1) VZ = VBE3 (zener voltage is equal to BJT base-emitter voltage)
2) Using KVL: -VZ + VBE3 + IE3RE = 0
3) Simplify: IE3RE = 0
4) IE3 is constant
Therefore, with a zener diode replacing R2, the current IE3 (and thus IT) remains constant regardless of load or temperature variations. The zener diode acts to stabilize the BJT base-emitter voltage, keeping the current constant.
The document discusses applications of operational amplifiers (op-amps). It describes how op-amps can be used to build integrator and differentiator circuits by using feedback networks incorporating resistors and capacitors. It also discusses how op-amps can be used to create active filters, including low-pass and high-pass filters, for filtering signals.
This document presents an overview of operational amplifiers (op-amps). It begins with an introduction to op-amps, followed by their circuit symbol, pin diagram, important terms and equations. It describes the ideal properties of an op-amp, as well as non-ideal behaviors. Applications discussed include analog to digital converters, current sources, and zero crossing detectors. Advantages are listed as versatility and uses in various circuits. Disadvantages include limitations in power and load resistance.
This document discusses power quality and defines it as the ability of a power system to supply voltage continuously within tolerances. It outlines various power quality events like sags, swells, interruptions, harmonics, and their causes and effects. It then describes various techniques to mitigate power quality issues, including dynamic voltage restorers, harmonic filters, static VAR compensators, and unified power quality conditioners. Maintaining high power quality improves system efficiency and equipment lifespan while eliminating problems like voltage fluctuations, harmonics, and reactive power issues.
Enhancing phase margin of ota using self biasingelelijjournal
In this paper, a new adaptive biased low voltage cascode current mirror with high input/output swing is presented. This advantage is achieved using a self-biasing transistor and compensation resistor. The new structure profits from better input dynamic range and lower supply voltage without frequency response limitation and increasing input impedance. Also, the proposed current mirror is incorporated in folded cascode amplifier in order to enhance its phase-margin. The simulation results in 0.18 μm CMOS technology confirm the theoretical analysis and exhibits 478μA linear input/output current swing and a
phase-margin enhancement of 12o for the proposed current mirror and amplifier compared to the conventional circuits, respectively
Design of Two CMOS Differential Amplifiersbastrikov
High performance, 0.6u process CMOS differential amplifiers were designed in Cadence. Design specifications included differential gain, 3-db bandwidth, output swing, input common mode range, phase margin, total static power consumption, slew rate, and common mode rejection ratio.
A new precision peak detector full wave rectifierVishal kakade
This document summarizes a research paper that proposes a new precision peak detector/full-wave rectifier circuit based on dual-output current conveyors. The key points are:
1) The proposed circuit uses MOS transistors, a phase shifter, and dual-output current conveyors to generate a DC output voltage equal to the peak amplitude of the input sinusoidal signal over a wide frequency range.
2) An all-pass filter is used to shift the phase of the input signal by 90 degrees. This allows the circuit to fully rectify both halves of the sinusoidal wave.
3) Simulation results show the circuit has very low ripple voltage and harmonic distortion compared to existing techniques, making it
A novel voltage reference without the operational amplifier and resistorsIJRES Journal
novel voltage reference has been proposed and simulated using a 0.18μm CMOS process in
this paper. A near-zero temperature coefficient voltage is achieved in virtue of the bias voltage subcirciut which
consists of two MOSFETs operating in the saturation region. The kind of bias voltage subcirciut is used to
adjust the output voltage and compensate the curvature. The output voltage is equal to the extrapolated
threshold voltage of a MOSFET at absolute zero temperature, which was about 591.5 mV for the MOSFETs we
used. The power supply rejection ratio (PSRR) is improved with three feedback loops. Although the output
voltage fluctuates with process variation, the circuit can monitor the process variation in MOSFET threshold
voltage. The simulation results show that the line regulation is 0.75 mV/V in a supply voltage range from 1.6 V
to 3.1 V and the temperature coefficient is around 10.8 ppm/℃ to 28.5 ppm/℃ at 9 different corners in a
temperature range from -20℃ to 120 ℃.
The PSRR is -70 dB at 100Hz with a supply voltage at 1.8 V, and the
layout size is 0.012mm2. The results of simulation and post layout simulation are almost the same.
Power System Simulation Laboratory Manual Santhosh Kumar
This document outlines experiments related to power system simulation laboratory. It includes 10 experiments covering topics like computation of transmission line parameters, modeling of transmission lines, formation of bus admittance and impedance matrices, load flow analysis using different methods, fault analysis, stability analysis of single machine and multimachine systems, electromagnetic transients, load-frequency dynamics, and economic dispatch. The document provides theoretical background and procedures for conducting each experiment using MATLAB software. Sample problems are also included for some experiments to demonstrate the modeling and simulation of different power system components and analysis.
Design of Low Voltage Low Power CMOS OP-AMPIJERA Editor
Operational amplifiers are an integral part of many analog and mixed signal systems. As the demand for mixed
mode integrated circuits increases, the design of analog circuits such as operational amplifiers in CMOS
technology becomes more critical. This paper presents a two stage CMOS operational amplifier, which operates
at ±1.8V power supply using TSMC 0.18um CMOS technology. The OP-AMP designed exhibit unity gain
frequency of 12.6 MHz, and gain of 55.5db with 300uw power dissipation. The gain margin and phase margin
of OP-AMP is 45˚ and 60˚ respectively. Design and simulation has been carried out in P Spice tool.
Application of SVM Technique for Three Phase Three Leg Ac/Ac Converter TopologyIOSR Journals
This paper presents a simulation of a three-phase three-leg AC/AC converter topology using nine IGBTs and space vector pulse width modulation (SVM) technique. The proposed topology reduces the number of switches compared to conventional back-to-back and matrix converters. Simulation results show the converter provides sinusoidal input and output voltages with unity power factor under constant frequency and variable frequency operation. Experimental results from a 5kVA prototype verify the validity of the proposed scheme.
Distortion Analysis of Differential AmplifierIOSR Journals
Abstract: The linearity of the CMOS is of major concern in the design of many analog circuits. In this paper the nonlinearity behavior of CMOS analog integrated circuits is investigated.The basic building block of analog integrated circuits such as differential amplifier with current mirror load have been chosen for harmonic distortion analysis.A mechanism to analyze the distortion of CMOS circuits in deep submicron technology that can be easily used to detect the distortion is built.The MOSFET model used for simulation is TSMC BSIM3 SPICE model from 0.13-μm CMOS process technology. HSPICE circuit simulator tool is used for distortion analysis of CMOS circuits. The MOS model used in this paper includes short-channel effects and gate-source capacitance, gate-drain capacitance, output resistance of MOS transistor. Analytical results are compared with simulation results and the influences of circuit parameters on circuit linearity are discussed.
Keywords: Analog Integrated Circuits, CMOSanalog integrated circuits, harmonic distortion, HSPICE, Short-channel effects, small signal analysis, transient analysis.
Design of a Sample and Hold Circuit using Rail to Rail Low Voltage Compact Op...IJERA Editor
This paper presents a low power high performance and higher sampling speed sample and hold circuit. The
proposed circuit is designed at 180 nm technology and has high linearity. The circuit can be used for the ADC
frontend applications and supports double sampling architecture. The proposed sample and hold circuit has
common mode range beyond rail to rail and uses two differential pairs transistor stages connected in parallel as
its input stage.
Mitigation of Lower Order Harmonics with Filtered Svpwm In Multiphase Voltage...IJERA Editor
Multi-phase machines and drives is a topic of growing relevance in recent years, and it presents many challenging issues that still need further research. This is the case of multi-phase space vector pulse width modulation (SVPWM), which shows not only more space vectors than the standard three-phase case, but also new subspaces where the space vectors are mapped. In the digital implementation, multiphase reference voltages are sampled and fed into the digital modulator to produce gating signals at a constant clock rate f. This means a finite pulse-width resolution because the gating state transition can only occur at some specific time instants depending on frequency. This results in a deviation of produced phase voltages from the desired phase voltages, i.e., increasing harmonic distortion especially for a small modulation index signal. In the present paper a filtered space-vector pulse-width modulation (SVPWM) considering finite pulse-width resolution is proposed to produce a switching sequence with reduced baseband harmonics for multiphase voltage source inverters (VSI). This is achieved by incorporating a pseudo feedback loop regarding weighted voltage difference between desired and produced phase voltages.
Analysis and Design of A Low-Voltage Low-Power Double-Tail Comparator. This is a final semester Mtech project on VLSI design implementation of dual tail comparator in a modifyied version. This design is implemented using VHDL Language with 100% Source code synthesizable available. Software for free to download and knowledge transfer for the same project is also being implemented..The design is implemented using FSM technology, low power is achieved in this project.area utilization is the major advantage in this project.Low power techniques such as Clock gating, power gating is implemented in this project.,ieee reference paper is used for the base.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
High Performance Temperature Insensitive Current Mode Rectifier without DiodeIOSR Journals
A new current mode precision rectifier is presented. This circuit provides precision rectification for
wide range of input signal with low temperature sensitivity. It can work as full wave rectifier as well as half
wave rectifier with controllability on action. It can amplify rectified current signal by a bias voltage. Direction
of the output current signal can also be controlled by changing the polarity of the bias voltage. It can operate up
to tens of Giga Hertz. The rectifier circuit with above features does not use any diode but only two CMOS
CCCDTA. Power consumption of the circuit is 601.05μW. The performance of the circuit is verified by PSPICE
simulations
High Performance Temperature Insensitive Current Mode Rectifier without DiodeIOSR Journals
Abstract : A new current mode precision rectifier is presented. This circuit provides precision rectification for wide range of input signal with low temperature sensitivity. It can work as full wave rectifier as well as half wave rectifier with controllability on action. It can amplify rectified current signal by a bias voltage. Direction of the output current signal can also be controlled by changing the polarity of the bias voltage. It can operate up to tens of Giga Hertz. The rectifier circuit with above features does not use any diode but only two CMOS CCCDTA. Power consumption of the circuit is 601.05μW. The performance of the circuit is verified by PSPICE simulations Keywords – CCCDTA, CMOS, current mode circuit, full wave rectifier, half wave rectifier, and PSPICE.
Single Stage Differential Folded Cascode AmplifierAalay Kapadia
The document presents the final report of a folded cascode amplifier design project. Key aspects of the design include:
1) The amplifier was designed to meet specifications including a gain of 85 dB, output swing of 1.4 V, and slew rate of 10 V/us.
2) A folded cascode topology was chosen to provide high output swing. Transistor sizes were calculated to meet the gain, slew rate, and output swing requirements.
3) Simulation results showed the design met all specifications, with an actual gain of 85.76 dB, phase margin of 60.1 degrees, and slew rate of 9.52 V/us.
A Review of Matrix Converter and Novel Control Method of DC-AC Matrix Converteridescitation
This paper presents a review of matrix converter and novel control methods for DC-AC matrix converters. It begins with a brief history of matrix converters and discusses different modulation and control strategies that have been developed, including Venturini scalar control, Roy scalar control, carrier-based PWM, and space vector modulation. The paper then proposes a new topology for a DC-AC matrix converter to generate a multilevel output voltage with fewer switches than a traditional multilevel inverter. The performance of the proposed DC-AC matrix converter module is evaluated through MATLAB simulation and by testing with a three-phase induction motor.
This document presents a new mathematical model for analyzing a three-phase controlled rectifier using switching functions. The model derives closed-form analytical equations to compute the rectifier's steady-state performance. It is based on deriving appropriate switching functions using General Switching Matrix Circuit techniques. Once the switching functions are obtained, the output current, input current, and output DC voltage can be easily derived. The model accurately accounts for overlap effects and can derive the input voltage and current distortions as well as output voltage distortion. The model provides designers with key performance metrics like voltage and current values without simulations.
Physical designing of low power operational amplifierDevendra Kushwaha
The document provides details about a master's thesis project to design a novel low power operational amplifier. It begins with an introduction to operational amplifiers, describing their basic structure and ideal characteristics. The literature review discusses previous work on designing low power and low noise operational amplifiers using techniques like current driven bulk, Miller compensation, and class AB amplifiers. Key inferences from the literature are that most work has been done on 120nm CMOS technology, noise can be reduced by adjusting transconductance, and cascoded structures provide better gain than cascaded structures. The document outlines the scope of work, methodology, expected outcomes, and software requirements for the thesis project.
A 80Ms/sec 10bit PIPELINED ADC Using 1.5Bit Stages And Built-in Digital Error...VLSICS Design
Use of pipelined ADCs is becoming increasingly popular both as stand alone parts and as embedded functional units in SOC design. They have acceptable resolution and high speed of operation and can be placed in relatively small area. The design is implemented in 0.18uM CMOS process. The design includes a folded cascode op-amp with a unity gain frequency of 200MHz at 88 deg. Phase margin and a dc gain of 75dB. The circuit employs a built in sample and hold circuit and a three phase non-overlapping clock.
A 80Ms/sec 10bit PIPELINED ADC Using 1.5Bit Stages And Built-in Digital Error...VLSICS Design
Use of pipelined ADCs is becoming increasingly popular both as stand alone parts and as embedded functional units in SOC design. They have acceptable resolution and high speed of operation and can be placed in relatively small area. The design is implemented in 0.18uM CMOS process. The design includes a folded cascode op-amp with a unity gain frequency of 200MHz at 88 deg. Phase margin and a dc gain of 75dB. The circuit employs a built in sample and hold circuit and a three phase non-overlapping clock.
Similar to Design of a Two-Stage Single Ended CMOS Op-Amp (20)
A 80Ms/sec 10bit PIPELINED ADC Using 1.5Bit Stages And Built-in Digital Error...
Design of a Two-Stage Single Ended CMOS Op-Amp
1. Abstract— Motivated by course requirements and personal
interest in CMOS design, the following papers describes the
process taken to design a classical two-stage op amp configuration
with PMOS input transistors and Miller compensation with a
nulling resistor. This design takes into consideration
specifications on the minimum channel length, supply voltage,
load capacitance, open loop gain, phase margin, and unity gain
frequency. An analytical approach to solving the design is the
initially prepared. Then minor modifications are made, via the
assistance of simulations tools, to ensure all specifications of the
two stage op-amp are met.
I. INTRODUCTION
HE design of a CMOS op-amp contains multiple stages.
Identifying the basic structure of the op-amp as well as the
compensation type is the first stage. Additionally,
identifying the dc currents and transistor sizes and verifying
the results via simulations (such as SPICE) follows. The
physical implementation of the design, fabrication,
specification verification via measurements, and final
medications are the additional stages which will not be
covered in the following two stage operational amplifier
design. Due to the specifications given for the design, the
classical two-stage op amp configuration (voltage to current
and current to voltage stages) with PMOS input transistors and
Miller compensation with a nulling resistor was chosen (shown
in Appendix A).
The analytical design approach taken for the two stage
operational amplifier begins by indentifying the parameters of
the current mirror. The differential input parameters, second
gain parameters, and active load parameters follow
respectively. The final analytical parameter incorporates the
resultant compensation. With the utilization of SPICE
simulation and the BSIM3 model, the analytical design
undergoes minor modifications to achieve the design
requirements.
II. PARAMETER EXTRACTION
While the supply voltage is given, the supply current,
operating temperature, and temperature range are ignored for
this design. The process specifications can be identified via
simulation of the BSIM3 model in SPICE. The process
specifications which are necessary for this design are Vtn, Vtp,
Kn’, Kp’, λn, and λp. In order to identify Vtn, Vtp, Kn’, and
Kp’, linearly sweep values of Vgs for an N-MOS and a P-
MOS transistor biased in the saturation region. Vtn and Vtp
are identified graphically by determining the value of Vgs
when the drain current through the N-MOS and P-MOS
transistor become zero. Kn’ and Kp’ are identified by the slope
of the √(Id) vs. Vgs curve (slope = √[K’ / 2 * (W/L)]). λn and
Submitted for review no later than December 6th
, 2007 by 13:00 PST
λp are obtained by varying the Vds and identifying the current
through an N-MOS and P-MOS transistor biased in the
saturation region. Once the currents are obtained, λn and λp
can be identified from equation one
(eq.1: 1 1
2 2
1
1
d ds
d ds
I V
I V
λ
λ
+ ×
=
+ ×
).
III. DESIGN OF THE OPERATIONAL AMPLIFIER
While there are multiple approaches in analytically
designing an operational amplifier, the subsequent method
utilized consists of selecting the preferred drain currents for
each gain stage, identifying the current mirror parameters to
achieve such values, and finally designing the gain stages to
achieve the op-amp’s specifications. The following describes
such process; In Appendix B is the detailed calculations listed
in respective order with the proceeding process.
A. Current Mirrors
The segments of the two stage op-amp which pertains to the
current mirror includes; Iref, M5, M7, and M8. The purpose of
the current mirrors is to supply a drain current to each of the
two gain stages. The reference current (Iref) as well as the
current for each of the two stages must be determined. In this
design, the reference current was arbitrarily chosen to be
20µA. While not in the requirements of the design, a larger
reference current has not been selected to minimize the effect
of reference current error. Based upon the requirements of the
op-amp, the gain-bandwidth (GB) as well as the open-loop
gain (Avo) can be utilized in order to identify the current
margin of the first stage. (If there were maximum power
dissipation, input common mode range, and/or slew rate
requirements, they would be taken into account in selecting the
current of the first stage.) The chosen current must be large
enough to adhere to the GB requirement (eq.2: 1m
C
G
GB
C
= )
while small enough to maintain the requirement for open loop
gain (eq.3:
( )
1 2
2
5 6,7
2 m m
vo
d d N P
G G
A
I I λ λ
× ×
=
× × +
). The current of
the first gain stage was chosen to be 300µA. From equation 3
and 4 (eq.4:
'
2 6,7
6
2m d N
W
G I K
L
= × × ×
), the current
for the second stage can be chosen as a balance between
increasing the trans-conductance without sacrificing the open-
loop gain. For simplicity of design, the current of the first and
second stage was chosen to be the same (300µA).
Transistor 8 is in a diode-connected configuration (drain is
directly connected to the gate); therefore the device will
Design of a Two-Stage Single Ended CMOS Op-Amp
(November 2007)
STEVEN G. ERNST
T
2. operate in either the saturation or cut-off region. Transistor 8
plays a direct role in determining the VdSAT for the other
biasing transistors. With this in mind, the (W/L) ratio for
transistor 8 was chosen to be 8. With equation 5, the (W/L)
ratio for M5 is calculated (eq. 5: 5
5 88
IW W
L I L
= ×
).
Additionally with equation 6, the (W/L) ratio for M7 is
calculated (eq. 6: 7
7 88
IW W
L I L
= ×
).
B. Differential Input Stage
As shown in equation 2, the trans-conductance of the first
gain stage can be calculated if the gain-bandwidth and the
compensation capacitor (CC) are known. To ensure the two
stage op-amp achieves the minimum gain-bandwidth
(determined by the unity gain frequency), a gain-bandwidth
buffer of 5 is included in equation 2. From Allen [1], when a
phase margin of 60o
is required, the compensation capacitor
must be chosen to be greater than 0.22 times the capacitance
seen as the output. With such condition, an arbitrarily chosen
value of 5pF for the compensation capacitor and a gain-
bandwidth buffer of 5, the gain of the first stage is identified
and utilized in equation 7 (eq. 7:
2
1
'
1,2 5
m
d P
GW
L I K
=
×
) to
calculate the (W/L) ratio of the differential input stage.
C. Second Gain Stage
The second pole of the two stage op-amp is determined
directly by the gain of the second stage and inversely by the
load capacitance (eq. 8: 2
2
m
L
G
P
C
= ). In order to obtain a
sufficient phase margin (PM), the second pole of the two stage
op-amp must be located past the unity gain frequency. From
Allen [1], the second pole should be extended by at least 1.73
times the gain-bandwidth. For a margin of safety, the value of
2.2 is recommended. With equation 2, equation 8, and the
buffer of 2.2, the trans-conductance of the second stage can be
calculated. Furthermore, the (W/L) ratio of the transistor in the
second gain stage (M6) can be calculated from equation 9 (eq.
9:
2
2
'
6 62
m
d N
GW
L I K
=
× ×
).
D. Active Load Stage
To ensure a reduced input offset voltage, the systematic
offset condition must apply; the drain voltages of M3 and M4
must remain the same. This allows the current for the first gain
stage to equally split between M1 and M2. With the systematic
offset condition applied, the (W/L) ratio for M3 and M4 can
be calculated from equation 10 (eq.
10: 5
3,4 66
1
2
d
d
IW W
L I L
= × ×
).
E. Compensation
Included in series with the Miller compensation (previously
estimated in the differential input stage) on the second gain
stage is a nulling resister. The purpose of the nulling resister is
to eliminate or move the right hand plane (RHP) zero to the
left plane. From Hershenson, Boyd, and Lee [2], the value of
the nulling resistor can be estimated by equation 11 (eq.
11:
2
1
M
R
G
= ).
F. Defining Widths and Lengths
Due to channel length modulation, the minimum channel
length should not be chosen for an op-amp design. From
Kartikeya Mayaram (November 2007) [3], the channel length
is best chosen if it is at least 3 to 4 times the minimum
allowable length. For the intended operation of the differential
input and active load stage, transistors M1, M2, M3, and M4
must have matching widths and matching lengths.
Additionally, the biasing transistors (M5, M7, and M8) must
have matching lengths. For the above reasons and due to
simplicity, all lengths are set equal (1um). All transistor widths
are calculated from equation 12 (eq. 12: i i
i
W
W L
L
= ×
)
where Li is the same for every transistor.
IV. SIMULATION
Once the design parameters were identified, the two stage
op-amp is ready for the last stage of modification. For this
design, PSPICE was chosen as the preferred simulation device.
The analytical result of the op-amp with the BSIM3 model will
not always meet all the specifications. For this reason, minor
modifications of the device parameters. With these
modifications, the design parameters are fully identified, and
the performance of the op-amp can be simulated. The net-list
for such simulation can be found in Appendix C.
A. Offset Voltage
The input common mode range is determined by grounding
the non-inverting input, connecting the inverting input to the
output, and measuring the dc operating point on the inverting
input/output node. This dc operating point is the offset voltage.
B. Open-Loop Gain
The open loop gain is achieved by plotting the magnitude of
the output vs. the input (in dB) of the op-amp while sweeping
the input with an AC source and visually identifying the
magnitude at low frequencies.
C. Unity-Gain Frequency
The unity-gain frequency is achieved similar to that of the
open-loop gain. Simply plot the magnitude of the output vs.
the input of the op-amp (in dB) while sweeping the input with
an AC source and visually identify the frequency at which the
gain is 0dB (1V/V).
3. D. Phase Margin
The phase margin is achieved by plotting the phase of the
output vs. input (in degrees) of the op-amp and identifying the
magnitude of the value of the phase that corresponds with the
unity-gain frequency. The phase margin is then calculated by
subtracting the corresponding value from 180 degrees.
E. Input Common Mode Range
The input common mode range is determined by applying
the offset voltage from the non-inverting input to the inverting
input, applying a voltage source from the non-inverting input
to ground, and sweeping dc values of the voltage source by the
range of the supply voltages. From a plot of the output
voltages, both edges of the linear region identify VICMAX and
VICMIN.
F. Input Referred Noise Voltage
Within the simulation software, PSPICE, there is a prebuilt
function specifically designed to evaluate the input referred
noise voltage (.NOISE output input). As the frequency
of the input to the op-amp is swept, this function will identify
the input referred noise voltage. Therefore, one can probe the
desired frequency to distinguish the noise voltage referred to
the input.
G. Power Supply Rejection Ratio
As there are positive and negative power supplied to the op-
amp, the power supply rejection ratio (PSRR) can be viewed
from two viewpoints. The positive PSRR can be determined by
equation 13 (eq. 13:
( 0)
( 0)
V dd dd
dd in out
A V V
PSRR
A V V
+ =
= =
=
). The
negative PSRR can be determined by equation 14 (eq.
14:
( 0)
( 0)
V dd ss
ss in out
A V V
PSRR
A V V
− =
= =
=
). In order to simulate the
PSRR, ground the non-inverting input and tie the inverting
input to the output.
V. RESULTS
Table I includes a comprehensive list of the design
specifications and the performance of the two stage op-amp. It
can be seen that the performance of the two stage op-amp
exceeds each of the specifications.
TABLE I
SPECIFICATIONS AND PERFORMANCE
Constraints / Variables Specifications Performance
Open-loop gain > 70 dB 74.46dB
Unity-gain frequency > 10 MHz 79.28MHz
Phase margin 60o
64.3o
ICMR 0.75V
VICMAX 0V
VICMIN -0.75V
IR Noise Voltage @ 1 kHz 1.8mV
IR Noise Voltage @ 4 MHz 11µV
PSRR (Vdd) @ 1kHz 78.5dB
PSRR (Vdd) @ 10MHz 44.9dB
PSRR (Vss) @ 1kHz 77.9dB
PSRR (Vss) @ 10MHz 15.4dB
Table II includes the design parameters of the two stage op-
amp.
TABLE II
DESIGN PARAMETERS
Constraints / Variables Specifications Design Parameters
W1 = W2 260µm
W3 = W4 45µm
W5 120µm
W6 90µm
W7 120µm
W8 8µm
L1-8 ≥ 0.18µm 1µm
Iref 20µA
CL 4pF 4pF
CC 5pF
R 800
VI. CONCLUSION
When the open-loop gain, phase margin, unity gain
frequency, power supply, and load capacitance are the only
constraints in designing a two stage operational amplifier, the
design parameters listed in table II can be determined via the
approach taken in this paper. Identifying the current mirror
through educated analytical methods, then categorizing the
remaining parameters to adhere to the specifications is one
approach which, in this case, yields desired results.
ACKNOWLEDGMENTS
In addition to the listed references, information used
throughout the paper was taken from general knowledge
obtained by the author thorough out his educational career,
industrial career, and hobbyist projects.
REFERENCES
[1] P.E. Allen. “Chapter 6 – CMOS Operational Amplifiers.” CMOS
Analog Circuit Design. 2005.
http://aicdesign.org/scnotes/2004notes/Chap06_2UP_5_2_04_.pdf
[2] Maria del Mar Hershenson, Stephen P. Boyd, and Thomas H. Lee.
“Optimal Design of a CMOS Op-Amp via Geometric Programming.”
IEEE. January 2001.
http://www.stanford.edu/~boyd/papers/pdf/opamp_tcad.pdf
[3] Kartikeya Mayaram. Professor. School of Electrical Engineering and
Computer Science. Oregon State University.
[4] Kartikeya Mayaram. “Lecture notes for ECE 522.” Fall 2007. Oregon
State University
Steven G. Ernst Born in Salem, Oregon in
1984. He became a member of IEEE in 2007.
Currently pursuing a master’s of science degree
in Electrical Engineering at Oregon State
University in Corvallis, Oregon. The
anticipated date of graduation is June 2009. He
received his bachelor’s of science degree in
Electrical Engineering at Oregon State
University in Corvallis, Oregon in March of
2007. His interests include Power Electronics
and Power Systems. His research focuses on
Energy Systems.
He has worked for Intel Corporation as a
JUNIOR DESIGN ENGINEER in 2006 –
2007. He has worked for Siltronic Corporation as a FACILITIES ENGINEER
in 2005. He currently is working for the Army Corps of Engineers as a
STUDENT ENGINEER in Portland, Oregon since 2007.
4. APPENDIX
A. Two Stage CMOS Operational Amplifier Configuration
B. Calculations
( ) ( )
2 2
'
2
2 2 8.4575 3
143.059
1
1
N
slope E A
K
W V
L
× × − µ
= = =
( ) ( )
2 2
'
2
2 2 4 3
32
1
1
P
slope E A
K
W V
L
× × − µ
= = =
1 1
2 2
1
1
d P ds
d P ds
I V
I V
λ
λ
+ ×
=
+ ×
1 52.93 4
0.010791
2.9 4 1 4
P
P
P
E
E
λ
λ
λ
+ ×−
→ = ∴ =
− + ×
1 1
2 2
1
1
d N ds
d N ds
I V
I V
λ
λ
+ ×
=
+ ×
1 44.3 4
0.010922
4.39 4 1 6
N
N
N
E
E
λ
λ
λ
+ ×−
→ = ∴ =
− + ×
Set Iref = 20µA
Set I5 = 300µA
Set I6 = 300µA
Set (W/L)8 = 8
5
5 88
300 8
120
20 1
IW W
L I L
µ
µ
= × = × =
7
7 88
300 8
120
20 1
IW W
L I L
µ
µ
= × = × =
Set buffer = 5
Set CC = 5pF
1 2
5 2 10 5 15.7m C
mA
G C GB buffer p M
V
= × × = × ×Π× × =
( )
22
1
'
1,2 5
15.7
256.76
300 32
m
d P
mGW
L I K µ µ
= = =
× ×
1
2
2.2
2.2 m
m L L
C
G
G C GB C
C
×
= × × = ×
2
2.2 15.7
4 2.765
5
m mA
p
p V
×
= × =
( )
22
2
'
6 6
2.765
89.0659
2 2 300 143.059
m
d N
mGW
L I K µ µ
= = =
× × × ×
5
3,4 66
1
2
d
d
IW W
L I L
= × ×
( )
1 300
89.0659 44.5329
2 300
µ
µ
= × × =
2
1 1
361.669
2.765M
R
G m
= = = Ω
( )1,2 256.76 1 256.76W m mµ µ= × =
( )3,4 44.5329 1 44.5329W m mµ µ= × =
( )5,7 60 1 60W m mµ µ= × =
( )6 89.0659 1 89.0659W m mµ µ= × =
( )8 8 1 8W m mµ µ= × =
C. PSPICE Code
*Two Stage Op-Amp Design
M1 5 0 4 4 CMOSP W = 260u L = 1u AD = 154.2p AS = 154.2p
PD = 515.2u PS = 515.2u
M2 6 8 4 4 CMOSP W = 260u L = 1u AD = 154.2p AS = 154.2p
PD = 515.2u PS = 515.2u
M3 5 5 3 3 CMOSN W = 45u L = 1u AD = 27p AS = 27p
PD = 91.2u PS = 91.2u
M4 6 5 3 3 CMOSN W = 45u L = 1u AD = 27p AS = 27p
PD = 91.2u PS = 91.2u
M5 4 2 1 1 CMOSP W = 120u L = 1u AD = 72p AS = 72p
PD = 241.2u PS = 241.2u
M6 7 6 3 3 CMOSN W = 90u L = 1u AD = 53.4p AS = 53.4p
PD = 179.2u PS = 179.2u
M7 7 2 1 1 CMOSP W = 120u L = 1u AD = 72p AS = 72p
PD = 241.2u PS = 241.2u
M8 2 2 1 1 CMOSP W = 8u L = 1u AD = 4.8p AS = 4.8p
PD = 17.2u PS = 17.2u
R1 6 10 800
Cc 10 7 5pF
CL 7 0 4pF
Iref 2 3 20uA
Vdd 1 0 0.9v
Vss 3 0 -0.9v
Vi 8 0 DC 0 AC 1V
* BSIM3 model inserted here i.e. .MODEL CMOSN NMOS LEVEL=7
* BSIM3 model inserted here i.e. .MODEL CMOSP PMOS LEVEL=7
.PROBE
.AC DEC 10 1 200MEG
.OP
.END
****************************DC*OPERATING*POINTS********************************
NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
( 1) .9000 ( 2) .1713 ( 3) -.9000 ( 4) .5619
( 5) -.3006 ( 6) -.3006 ( 7) .0620 ( 8) 0.0000
( 10) -.3006
5. D. KN’ and VTN Parameters Extraction
E. KP’ and VTP Parameters Extraction
F. Magnitude and Phase of the Two Stage Op-Amp
Vgs 2 0 1
Vds 1 0 0.1V
M1 1 2 0 0 CMOSN W=1u L=1u
*BSIM3 MODEL
.DC Vgs 0 1.5 0.01
.PROBE
.OP
.END
*RESULTS:
*VTN = 0.4V
*KPN = 143.059uA/V^2
Vg 2 0 1
VdS 1 0 -0.1V
M1 0 2 1 1 CMOSP W=1u L=1u
*BSIM3 MODEL
.DC Vg -1 1 0.1
.PROBE
.OP
.END
*RESULTS:
*VTP = -0.29V
*KPN = 32uA/V^2
6. G. Open-Loop Gain
H. Unity-Gain Frequency & Phase Margin
I. ICMR
M1 5 9 4 4 CMOSP W = 260u L =1u AD = 154.2pAS = 154.2pPD = 515.2uPS = 515.2u
M2 6 8 4 4 CMOSP W = 260u L =1u AD = 154.2pAS = 154.2pPD = 515.2uPS = 515.2u
M3 5 5 3 3 CMOSN W = 45u L =1u AD = 27p AS = 27p PD = 91.2u PS = 91.2u
M4 6 5 3 3 CMOSN W = 45u L =1u AD = 27p AS = 27p PD = 91.2u PS = 91.2u
M5 4 2 1 1 CMOSP W = 120u L =1u AD = 72p AS = 72p PD = 241.2uPS = 241.2u
M6 7 6 3 3 CMOSN W = 90u L =1u AD = 53.4p AS = 53.4p PD = 179.2uPS = 179.2u
M7 7 2 1 1 CMOSP W = 120u L =1u AD = 72p AS = 72p PD = 241.2uPS = 241.2u
M8 2 2 1 1 CMOSP W = 8u L =1u AD = 4.8p AS = 4.8p PD = 17.2u PS = 17.2u
R1 6 10 800
Cc 10 7 5pF
CL 7 0 4pF
Iref 2 3 20uA
Vdd 1 0 0.9v
Vss 3 0 -0.9v
Vic 8 0 DC 0
Vos 8 9 11.69E-06
*BSIM3 MODELS
.PROBE
.DC Vic -1.1 1.1 .01
.OP
.END
*RESULTS:
*Vicmax = 0V
*Vicmin = -0.75V
*ICMR = 0.75V
7. J. Input Referred Noise Voltage
K. Power Supply Rejection Ratio (Vdd)
L. Power Supply Rejection Ratio (Vss)
M1 5 8 4 4 CMOSP W = 260u L =1u AD = 154.2pAS = 154.2pPD = 515.2uPS = 515.2u
M2 6 8 4 4 CMOSP W = 260u L =1u AD = 154.2pAS = 154.2pPD = 515.2uPS = 515.2u
M3 5 5 3 3 CMOSN W = 45u L =1u AD = 27p AS = 27p PD = 91.2u PS = 91.2u
M4 6 5 3 3 CMOSN W = 45u L =1u AD = 27p AS = 27p PD = 91.2u PS = 91.2u
M5 4 2 1 1 CMOSP W = 120u L =1u AD = 72p AS = 72p PD = 241.2uPS = 241.2u
M6 7 6 3 3 CMOSN W = 90u L =1u AD = 53.4p AS = 53.4p PD = 179.2uPS = 179.2u
M7 7 2 1 1 CMOSP W = 120u L =1u AD = 72p AS = 72p PD = 241.2uPS = 241.2u
M8 2 2 1 1 CMOSP W = 8u L =1u AD = 4.8p AS = 4.8p PD = 17.2u PS = 17.2u
R1 6 10 800
Cc 10 7 5pF
CL 7 0 4pF
Iref 2 3 20uA
Vdd 1 0 0.9v
Vss 3 0 -0.9v
Vi 8 0 DC 11.69E-06 AC 1
*BSIM3 MODELS
.PROBE
.AC DEC 10 0.1 200MEG
.OP
.NOISE V(7) Vi
.END
*RESULTS: 1.8mV, 11uV
M1 5 7 4 4 CMOSP W = 260u L =1u AD = 154.2pAS = 154.2pPD = 515.2uPS = 515.2u
M2 6 0 4 4 CMOSP W = 260u L =1u AD = 154.2pAS = 154.2pPD = 515.2uPS = 515.2u
M3 5 5 3 3 CMOSN W = 45u L =1u AD = 27p AS = 27p PD = 91.2u PS = 91.2u
M4 6 5 3 3 CMOSN W = 45u L =1u AD = 27p AS = 27p PD = 91.2u PS = 91.2u
M5 4 2 1 1 CMOSP W = 120u L =1u AD = 72p AS = 72p PD = 241.2uPS = 241.2u
M6 7 6 3 3 CMOSN W = 90u L =1u AD = 53.4p AS = 53.4p PD = 179.2uPS = 179.2u
M7 7 2 1 1 CMOSP W = 120u L =1u AD = 72p AS = 72p PD = 241.2uPS = 241.2u
M8 2 2 1 1 CMOSP W = 8u L =1u AD = 4.8p AS = 4.8p PD = 17.2u PS = 17.2u
R1 6 10 800
Cc 10 7 5pF
CL 7 0 4pF
Iref 2 3 20uA
Vdd 1 0 0.9v AC 1V
Vss 3 0 -0.9v
*Vi 8 0 DC 0
*BSIM3 MODELS
.PROBE
.AC DEC 10 1 200MEG
.OP
.END
*RESULTS: 78.5dB, 44.9dB
M1 5 7 4 4 CMOSP W = 260u L =1u AD = 154.2pAS = 154.2pPD = 515.2uPS = 515.2u
M2 6 0 4 4 CMOSP W = 260u L =1u AD = 154.2pAS = 154.2pPD = 515.2uPS = 515.2u
M3 5 5 3 3 CMOSN W = 45u L =1u AD = 27p AS = 27p PD = 91.2u PS = 91.2u
M4 6 5 3 3 CMOSN W = 45u L =1u AD = 27p AS = 27p PD = 91.2u PS = 91.2u
M5 4 2 1 1 CMOSP W = 120u L =1u AD = 72p AS = 72p PD = 241.2uPS = 241.2u
M6 7 6 3 3 CMOSN W = 90u L =1u AD = 53.4p AS = 53.4p PD = 179.2uPS = 179.2u
M7 7 2 1 1 CMOSP W = 120u L =1u AD = 72p AS = 72p PD = 241.2uPS = 241.2u
M8 2 2 1 1 CMOSP W = 8u L =1u AD = 4.8p AS = 4.8p PD = 17.2u PS = 17.2u
R1 6 10 800
Cc 10 7 5pF
CL 7 0 4pF
Iref 2 3 20uA
Vdd 1 0 0.9v
Vss 3 0 -0.9v AC 1V
*BSIM3 MODELS
.PROBE
.AC DEC 10 0.5 200MEG
.OP
.END
*RESULTS: 77.9dB, 15.4dB