This document describes the design of an operational transconductance single-ended amplifier (OTA). Key aspects of the design include:
1. An input stage with rail-to-rail input common mode range using matched NMOS and PMOS transistors.
2. An output stage with high output resistance to achieve 80dB of gain. A diode connection from the output to the bias voltage improves common mode range.
3. Gain boosting stages using NMOS and PMOS op-amps to further increase gain beyond what the output stage provides.
4. A constant gm biasing circuit to provide supply-independent biasing for the transistors in a way that is less sensitive to voltage supply changes.
This document analyzes the performance of short, medium, and long transmission lines. It discusses how different loads affect the efficiency, voltage regulation, and power factor of short and medium lines. It also examines how connecting transmission lines in series or parallel impacts performance. The document explores how shunt and series compensation can be used to improve transmission line characteristics. Finally, it discusses methods for improving power factor, such as using static capacitors, and how circuit parameters are determined for different transmission line types.
Signal and power integrity challenges in VLSI circuits and strategies for the...Pushpak Dagade
This document provides an overview of signal and power integrity challenges in VLSI circuits. It discusses interconnect modeling and the impacts of interconnect on delay, crosstalk, and power. Crosstalk effects and mitigation techniques are described. Supply bounce issues caused by di/dt noise are examined, including causes and effects. Mitigation approaches for supply bounce like intelligent engineering, guard rings, and on-chip decoupling capacitors are covered. The document concludes with a section on electromagnetic emission and interference in VLSI circuits and techniques to reduce emissions and noise.
Broadband Forum Marketing Report-MR-257: An Overview of G.993.5 VectoringPeerasak C.
An overview of VDSL2 vectoring
Broadband Forum | July 24, 2012
Vectored DSL as defined in ITU-T Recommendation G.993.5 supports line speeds of greater than 100 Mbps on loops up to 500 meters in length, enabling the most advanced application services to be carried over copper.
With appropriate placement of DSLAMs, use of management tools and techniques such as bonding of vectored lines and use of DQM techniques, vectored DSL becomes an important tool for network operator to provide broadband services such as IPTV to all their customers.
The emergence of vectored DSL provides the DSL based service provider with the tools that facilitate supporting the bandwidths required for higher valued premium services over their existing copper based networks and helps ensure that deployment of DSL increases as broadband services continue to evolve.
This white paper originally published on the Broadband Forum
Linearity enhancement of operational transconductance amplifier using sourceIAEME Publication
This paper proposes a source degeneration technique to improve the linearity of operational transconductance amplifiers (OTAs). OTAs are commonly used as building blocks in analog and mixed-signal integrated circuits, but their performance can be limited by inherent non-linearities in MOS transistors. The proposed source degenerated OTA (SDOTA) achieves improved third-order intermodulation distortion of -62dB compared to a conventional OTA, while maintaining a transconductance of 655.8 μA/V and gain of 14dB up to 4.7 GHz. The SDOTA is implemented in a 180nm CMOS process and shows enhanced linearity for applications requiring high frequency operation such as sigma-delta analog-to-digital
Design and analysis of operational transconductance amplifier using pspiceeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
The document describes the design of an operational transconductance amplifier (OTA) in 45nm CMOS technology. It presents the challenges in achieving a large input range of 100GHz bandwidth and 5000V/us slew rate. The general approach uses two amplifiers with a multiplexer and pole cancellation. Simulation results show the OTA meets most targets, achieving a bandwidth of 20MHz, slew rate of 13000V/s, and gain of 75dB. Suggestions to improve bandwidth and slew rate include increasing current and using pole cancellation.
This paper presents the design of folded cascode operational transconductance amplifier (OTA). This
design has been implemented in 0.18um CMOS Technology using Cadence. Spectre simulation shows
that the OTA has flat gain of 47dB from 1Hz to 100 KHz frequency, indicating stability of OTA, noise
ranges as 22.49769nV/ at 10Hz to 66.89128fV/ at 1MHz and average power as 0.770mW. In
this paper, we will be studying the design concepts, analysis of operational transconductance amplifier
which is used for recording the bio signals. This paper plays a key role in real time applications for
equipment designing of ECG, EEG, EMG, ENG devices. It is also used in recording and also for
treatment of Paralysis, Epilepsy, Neuro diseases etc.,
This document provides an overview of an "Analog VLSI Design" course. The goals of the course are to introduce principles of analog integrated circuit design and CMOS technology. Students will learn about CMOS layout design using CAD tools and complete a design project. The course covers topics including CMOS technology, resistors, capacitors, MOSFETs, current mirrors, amplifiers, and data converters. Assessment includes homework, a project, and a final exam.
This document analyzes the performance of short, medium, and long transmission lines. It discusses how different loads affect the efficiency, voltage regulation, and power factor of short and medium lines. It also examines how connecting transmission lines in series or parallel impacts performance. The document explores how shunt and series compensation can be used to improve transmission line characteristics. Finally, it discusses methods for improving power factor, such as using static capacitors, and how circuit parameters are determined for different transmission line types.
Signal and power integrity challenges in VLSI circuits and strategies for the...Pushpak Dagade
This document provides an overview of signal and power integrity challenges in VLSI circuits. It discusses interconnect modeling and the impacts of interconnect on delay, crosstalk, and power. Crosstalk effects and mitigation techniques are described. Supply bounce issues caused by di/dt noise are examined, including causes and effects. Mitigation approaches for supply bounce like intelligent engineering, guard rings, and on-chip decoupling capacitors are covered. The document concludes with a section on electromagnetic emission and interference in VLSI circuits and techniques to reduce emissions and noise.
Broadband Forum Marketing Report-MR-257: An Overview of G.993.5 VectoringPeerasak C.
An overview of VDSL2 vectoring
Broadband Forum | July 24, 2012
Vectored DSL as defined in ITU-T Recommendation G.993.5 supports line speeds of greater than 100 Mbps on loops up to 500 meters in length, enabling the most advanced application services to be carried over copper.
With appropriate placement of DSLAMs, use of management tools and techniques such as bonding of vectored lines and use of DQM techniques, vectored DSL becomes an important tool for network operator to provide broadband services such as IPTV to all their customers.
The emergence of vectored DSL provides the DSL based service provider with the tools that facilitate supporting the bandwidths required for higher valued premium services over their existing copper based networks and helps ensure that deployment of DSL increases as broadband services continue to evolve.
This white paper originally published on the Broadband Forum
Linearity enhancement of operational transconductance amplifier using sourceIAEME Publication
This paper proposes a source degeneration technique to improve the linearity of operational transconductance amplifiers (OTAs). OTAs are commonly used as building blocks in analog and mixed-signal integrated circuits, but their performance can be limited by inherent non-linearities in MOS transistors. The proposed source degenerated OTA (SDOTA) achieves improved third-order intermodulation distortion of -62dB compared to a conventional OTA, while maintaining a transconductance of 655.8 μA/V and gain of 14dB up to 4.7 GHz. The SDOTA is implemented in a 180nm CMOS process and shows enhanced linearity for applications requiring high frequency operation such as sigma-delta analog-to-digital
Design and analysis of operational transconductance amplifier using pspiceeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
The document describes the design of an operational transconductance amplifier (OTA) in 45nm CMOS technology. It presents the challenges in achieving a large input range of 100GHz bandwidth and 5000V/us slew rate. The general approach uses two amplifiers with a multiplexer and pole cancellation. Simulation results show the OTA meets most targets, achieving a bandwidth of 20MHz, slew rate of 13000V/s, and gain of 75dB. Suggestions to improve bandwidth and slew rate include increasing current and using pole cancellation.
This paper presents the design of folded cascode operational transconductance amplifier (OTA). This
design has been implemented in 0.18um CMOS Technology using Cadence. Spectre simulation shows
that the OTA has flat gain of 47dB from 1Hz to 100 KHz frequency, indicating stability of OTA, noise
ranges as 22.49769nV/ at 10Hz to 66.89128fV/ at 1MHz and average power as 0.770mW. In
this paper, we will be studying the design concepts, analysis of operational transconductance amplifier
which is used for recording the bio signals. This paper plays a key role in real time applications for
equipment designing of ECG, EEG, EMG, ENG devices. It is also used in recording and also for
treatment of Paralysis, Epilepsy, Neuro diseases etc.,
This document provides an overview of an "Analog VLSI Design" course. The goals of the course are to introduce principles of analog integrated circuit design and CMOS technology. Students will learn about CMOS layout design using CAD tools and complete a design project. The course covers topics including CMOS technology, resistors, capacitors, MOSFETs, current mirrors, amplifiers, and data converters. Assessment includes homework, a project, and a final exam.
This document provides recommendations for controlling radiated emissions from PCBs containing isoPower devices. It identifies two main sources of emissions: edge emissions from currents meeting the board edges, and input-output dipole emissions from driving currents across isolation gaps. It recommends several EMI mitigation techniques including input-output stitching capacitance, edge guarding, interplane capacitive bypassing, and power reduction. Test results show these techniques can help isoPower devices meet FCC/CISPR emissions standards. Proper PCB design is important for controlling radiated noise from high-speed switching isoPower components.
The document provides a product catalogue for frequency inverters from Schneider Electric Power Drives. It includes overviews of the >pDRIVE< MX eco and >pDRIVE< MX pro product ranges, which consist of frequency inverters for controlling three-phase motors across various power and voltage ranges. Technical specifications, applications, interfaces, and protection degrees are provided for the different product lines.
Designed a microwave amplifier circuit with a required bandwidth of 250MHz at a center frequency of 3.7GHz experiencing 6.5dB gain within Keysight ADS.
This document is a PhD thesis presented by Stepan Sutula to obtain the title of Doctor in Microelectronics and Electronic Systems. The thesis explores methods to increase the power efficiency and resolution of switched-capacitor Delta-Sigma analog-to-digital converters (ADCs) using novel low-power CMOS circuits.
It describes the development of low-current analog circuit techniques targeting power efficiency, including novel Class-AB operational amplifiers. A 96.6-dB-SNDR 50-kHz-BW 1.8-V 7.9-mW Delta-Sigma modulator for ADCs is implemented in a 0.18-μm CMOS process based on these techniques. Measurement results indicate
This document discusses selectivity, or discrimination, between circuit breakers. Selectivity is achieved when a fault is cleared only by the protective device closest to the fault, without tripping upstream devices. Total selectivity exists when devices discriminate up to their breaking capacity, while partial selectivity exists up to a specified current threshold. Selectivity can be achieved through current-based, time-based, energy-based, or logic-based coordination of circuit breaker settings. Current-based selectivity sets stepped tripping thresholds from downstream to upstream. Time-based selectivity uses time delays such that downstream breakers trip faster than upstream ones. The document provides tables to check selectivity between various circuit breaker combinations.
This thesis examines optimization approaches for the design of infield cable topology for offshore wind farms. The objective is to approximate the optimal inter-array cable connections in an affordable computation time to minimize cable costs. The thesis reviews state-of-the-art collection system designs and related research, which reveals the complexity of the problem and the need for heuristic methods. Planar Open Savings and Esau-Williams heuristics are implemented and evaluated on various test instances to optimize radial and branched topologies respectively for single and multiple cable types while respecting cable capacity constraints. The results are used to develop a hybrid approach and recommendations for the best algorithm depending on the problem parameters. Additional features are included to enhance practical applicability and a case study
Designed and manufactured an edge-coupled bandpass filter, with a required bandwidth of 900MHz at a center frequency of 3.8GHz experiencing 0.5dB pass-band ripple within Keysight ADS.
Designed and manufactured an edge-coupled bandpass filter, with a required bandwidth of 900MHz at a center frequency of 3.8GHz experiencing 0.5dB pass-band ripple within Keysight ADS.
This document describes the design and implementation of a high voltage, high resolution digital-to-analog converter (DAC) for driving deformable mirrors. The design uses a floating DAC architecture with a high voltage DAC providing the ground reference for a secondary low voltage, high resolution DAC. This allows the system to achieve the high voltage range of the primary DAC while maintaining the high resolution of the secondary DAC. The document details the component selection, circuit designs for single channel and multi-channel boards, and test results demonstrating a resolution of 1.6mV over a 60V range.
High performance low leakage power full subtractor circuit design using rate ...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
The document describes the GreenDroid mobile application processor architecture, which uses "conservation cores" (c-cores) to significantly improve energy efficiency over current designs. The c-cores are specialized processors automatically generated from profiling common smartphone applications like Android. They execute the most frequently used code regions with 18x less energy than general processors. By filling the "dark silicon" areas of chips with many c-cores, the GreenDroid architecture can execute general smartphone applications with 11 times less energy than today's most efficient designs, while maintaining or improving performance.
This document provides a mid-term report on the design and analysis of a voltage controlled oscillator (VCO) for a master's project. It discusses completing the circuit diagram, symbol creation, and test circuit simulation in Cadence using 180nm technology. Simulation results so far show the VCO design is one third complete, with layout and performance analysis remaining. The report includes background on VCO metrics like frequency, tuning range, phase noise, and power consumption. It also reviews applications of VCOs in frequency translation and discusses challenges in designing low phase noise CMOS VCOs.
This document appears to be a price list from Schneider Electric for its low voltage distribution products. It includes pricing and descriptions for various circuit breakers, switch disconnectors, and accessories. The products are organized by category and range, with sections devoted to Compact NSXm circuit breakers, EasyPact CVS and EZC circuit breakers, ground fault protection devices, Masterpact circuit breakers, and more. Technical specifications, stock statuses, and contact information for ordering are provided.
This document discusses the design of MEMS resonator systems with integrated readout circuitry. It first describes methods for extracting the threshold voltage of MOSFETs. It then covers the design of a differential amplifier, including determining its transconductance, voltage transfer characteristics, input common mode range, slew rate and frequency response. Next, it examines modeling an electromechanical nanocantilever sensor for mass detection. It provides equations for calculating small mass changes and the snap-in voltage of the cantilever-driver system. Finally, it presents the design process and SPICE simulation of a two-stage operational amplifier.
Cd00004444 understanding-and-minimising-adc-conversion-errors-stmicroelectronicsvu CAO
The document discusses understanding and minimizing errors in analog to digital conversion. It explains that the ADC converts analog signals to digital values but is subject to various errors from factors like noise, voltage sources, and PCB layout. It provides techniques to minimize errors, such as reducing noise, improving voltage regulation, and carefully designing PCB layout and analog signal paths.
Proline Promag 50L-Electromagnetic Flowmeter. Flow measurement of liquids in water or wastewater applications. Email: lam.nguyen@vietan-enviro.com HP: 0945 293292
This document summarizes some key challenges for digital circuits related to process, voltage, and temperature variations. It discusses techniques to prevent latchup and electrostatic discharge issues in integrated circuits. It also describes simultaneous switching noise that can occur when large numbers of circuits switch simultaneously. The document proposes using adaptive body biasing techniques to compensate for PVT variations and control output slope under different conditions. Simulation results show this approach can adjust rising and falling times of an output buffer for different substrate bias voltage conditions.
Implementation and analysis of power reduction in 2 to 4 decoder design using...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Proline Promag 10 D. Electromagnetic flow measuring system
The lightweight, compact wafer style flowmeter for basic water
applications. Email: lam.nguyen@vietan-enviro.com HP: 0945 293292
This document provides recommendations for controlling radiated emissions from PCBs containing isoPower devices. It identifies two main sources of emissions: edge emissions from currents meeting the board edges, and input-output dipole emissions from driving currents across isolation gaps. It recommends several EMI mitigation techniques including input-output stitching capacitance, edge guarding, interplane capacitive bypassing, and power reduction. Test results show these techniques can help isoPower devices meet FCC/CISPR emissions standards. Proper PCB design is important for controlling radiated noise from high-speed switching isoPower components.
The document provides a product catalogue for frequency inverters from Schneider Electric Power Drives. It includes overviews of the >pDRIVE< MX eco and >pDRIVE< MX pro product ranges, which consist of frequency inverters for controlling three-phase motors across various power and voltage ranges. Technical specifications, applications, interfaces, and protection degrees are provided for the different product lines.
Designed a microwave amplifier circuit with a required bandwidth of 250MHz at a center frequency of 3.7GHz experiencing 6.5dB gain within Keysight ADS.
This document is a PhD thesis presented by Stepan Sutula to obtain the title of Doctor in Microelectronics and Electronic Systems. The thesis explores methods to increase the power efficiency and resolution of switched-capacitor Delta-Sigma analog-to-digital converters (ADCs) using novel low-power CMOS circuits.
It describes the development of low-current analog circuit techniques targeting power efficiency, including novel Class-AB operational amplifiers. A 96.6-dB-SNDR 50-kHz-BW 1.8-V 7.9-mW Delta-Sigma modulator for ADCs is implemented in a 0.18-μm CMOS process based on these techniques. Measurement results indicate
This document discusses selectivity, or discrimination, between circuit breakers. Selectivity is achieved when a fault is cleared only by the protective device closest to the fault, without tripping upstream devices. Total selectivity exists when devices discriminate up to their breaking capacity, while partial selectivity exists up to a specified current threshold. Selectivity can be achieved through current-based, time-based, energy-based, or logic-based coordination of circuit breaker settings. Current-based selectivity sets stepped tripping thresholds from downstream to upstream. Time-based selectivity uses time delays such that downstream breakers trip faster than upstream ones. The document provides tables to check selectivity between various circuit breaker combinations.
This thesis examines optimization approaches for the design of infield cable topology for offshore wind farms. The objective is to approximate the optimal inter-array cable connections in an affordable computation time to minimize cable costs. The thesis reviews state-of-the-art collection system designs and related research, which reveals the complexity of the problem and the need for heuristic methods. Planar Open Savings and Esau-Williams heuristics are implemented and evaluated on various test instances to optimize radial and branched topologies respectively for single and multiple cable types while respecting cable capacity constraints. The results are used to develop a hybrid approach and recommendations for the best algorithm depending on the problem parameters. Additional features are included to enhance practical applicability and a case study
Designed and manufactured an edge-coupled bandpass filter, with a required bandwidth of 900MHz at a center frequency of 3.8GHz experiencing 0.5dB pass-band ripple within Keysight ADS.
Designed and manufactured an edge-coupled bandpass filter, with a required bandwidth of 900MHz at a center frequency of 3.8GHz experiencing 0.5dB pass-band ripple within Keysight ADS.
This document describes the design and implementation of a high voltage, high resolution digital-to-analog converter (DAC) for driving deformable mirrors. The design uses a floating DAC architecture with a high voltage DAC providing the ground reference for a secondary low voltage, high resolution DAC. This allows the system to achieve the high voltage range of the primary DAC while maintaining the high resolution of the secondary DAC. The document details the component selection, circuit designs for single channel and multi-channel boards, and test results demonstrating a resolution of 1.6mV over a 60V range.
High performance low leakage power full subtractor circuit design using rate ...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
The document describes the GreenDroid mobile application processor architecture, which uses "conservation cores" (c-cores) to significantly improve energy efficiency over current designs. The c-cores are specialized processors automatically generated from profiling common smartphone applications like Android. They execute the most frequently used code regions with 18x less energy than general processors. By filling the "dark silicon" areas of chips with many c-cores, the GreenDroid architecture can execute general smartphone applications with 11 times less energy than today's most efficient designs, while maintaining or improving performance.
This document provides a mid-term report on the design and analysis of a voltage controlled oscillator (VCO) for a master's project. It discusses completing the circuit diagram, symbol creation, and test circuit simulation in Cadence using 180nm technology. Simulation results so far show the VCO design is one third complete, with layout and performance analysis remaining. The report includes background on VCO metrics like frequency, tuning range, phase noise, and power consumption. It also reviews applications of VCOs in frequency translation and discusses challenges in designing low phase noise CMOS VCOs.
This document appears to be a price list from Schneider Electric for its low voltage distribution products. It includes pricing and descriptions for various circuit breakers, switch disconnectors, and accessories. The products are organized by category and range, with sections devoted to Compact NSXm circuit breakers, EasyPact CVS and EZC circuit breakers, ground fault protection devices, Masterpact circuit breakers, and more. Technical specifications, stock statuses, and contact information for ordering are provided.
This document discusses the design of MEMS resonator systems with integrated readout circuitry. It first describes methods for extracting the threshold voltage of MOSFETs. It then covers the design of a differential amplifier, including determining its transconductance, voltage transfer characteristics, input common mode range, slew rate and frequency response. Next, it examines modeling an electromechanical nanocantilever sensor for mass detection. It provides equations for calculating small mass changes and the snap-in voltage of the cantilever-driver system. Finally, it presents the design process and SPICE simulation of a two-stage operational amplifier.
Cd00004444 understanding-and-minimising-adc-conversion-errors-stmicroelectronicsvu CAO
The document discusses understanding and minimizing errors in analog to digital conversion. It explains that the ADC converts analog signals to digital values but is subject to various errors from factors like noise, voltage sources, and PCB layout. It provides techniques to minimize errors, such as reducing noise, improving voltage regulation, and carefully designing PCB layout and analog signal paths.
Proline Promag 50L-Electromagnetic Flowmeter. Flow measurement of liquids in water or wastewater applications. Email: lam.nguyen@vietan-enviro.com HP: 0945 293292
This document summarizes some key challenges for digital circuits related to process, voltage, and temperature variations. It discusses techniques to prevent latchup and electrostatic discharge issues in integrated circuits. It also describes simultaneous switching noise that can occur when large numbers of circuits switch simultaneously. The document proposes using adaptive body biasing techniques to compensate for PVT variations and control output slope under different conditions. Simulation results show this approach can adjust rising and falling times of an output buffer for different substrate bias voltage conditions.
Implementation and analysis of power reduction in 2 to 4 decoder design using...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Proline Promag 10 D. Electromagnetic flow measuring system
The lightweight, compact wafer style flowmeter for basic water
applications. Email: lam.nguyen@vietan-enviro.com HP: 0945 293292
2. 2 | P a g e
Academic Integrity Statement
Academic Integrity Pledge
Plagiarism is defined as copying the language, phrasing, structure, or specific ideas of others and
presenting any of these as one's own, original work; it includes buying papers, having someone
else write your papers, and improper citation and use of sources. When you present the words or
ideas of another (either published or unpublished) in your writing, you must fully acknowledge
your sources. Plagiarism is considered a violation of academic integrity whenever it occurs in
written work, including drafts and homework, as well as for formal and final papers.
The NCSU Policies, Regulations, and Rules on Student Discipline
(http://www.ncsu.edu/policies/student_services/student_discipline/POL11.35.1.php) sets the
standards for academic integrity at this university and in this course. Students are expected to
adhere to these standards. Plagiarism and other forms of academic dishonesty will be handled
through the university's judicial system and may result in failure for the project or for the course.
Pledge:
We have read and understood the above statement and agree to abide by the standards of academic
integrity in the NCSU Policies, Regulations, and Rules on Student Discipline.
Team members:
Helion Dhrimaj
Murat Yokus
3. 3 | P a g e
Table of Contents
Executive Summary........................................................................................................................ 5
OTA Design Discussion ................................................................................................................. 6
Input Stage Design...................................................................................................................... 6
Output Stage Design ................................................................................................................... 7
Gain Boosting Op-Amp (Baby Op-Amp) Design ...................................................................... 8
Supply Independent Biasing Circuit Design............................................................................... 9
Compensation ........................................................................................................................... 10
Circuit Schematics ........................................................................................................................ 14
Parameter Values ...................................................................................................................... 14
DC Operating Points................................................................................................................. 17
Results........................................................................................................................................... 20
Conclusion and Discussion........................................................................................................... 26
4. 4 | P a g e
Table of Figures
Figure 1. Input design of main stage on the left and right ............................................................. 6
Figure 2. Output design of main stage........................................................................................... 7
Figure 3. NMOS gain boosting op-amp design ............................................................................. 8
Figure 4. PMOS gain boosting op-amp design.............................................................................. 8
Figure 6. Constant gm-biasing design ........................................................................................... 9
Figure 7. AC gain of NMOS gain boosting before compensation............................................... 10
Figure 8. AC gain of NMOS gain boosting after compensation.................................................. 11
Figure 9. AC gain of PMOS gain boosting amplifier before compensation................................ 11
Figure 10. AC gain of PMOS gain boosting amplifier after compensation................................. 12
Figure 11. Main gain stage before compensation ........................................................................ 13
Figure 12. Main gain stage after compensation........................................................................... 13
Figure 13. NMOS gain boosting amplifier parameter values...................................................... 14
Figure 14. PMOS gain boosting operational amplifer parameter values..................................... 15
Figure 15. Biasing circuit parameter values ................................................................................ 16
Figure 16. Main gain stage parameter values .............................................................................. 16
Figure 17. DC operating points of NMOS gain boosting op-amp............................................... 17
Figure 18. DC operating points of PMOS gain boosting op-amp................................................ 18
Figure 19. DC operating point of biasing circuit......................................................................... 18
Figure 20. DC operating points of main gain stage ..................................................................... 19
Figure 21. Frequency response of the OTA................................................................................. 20
Figure 22. CMRR, differential gain, and common mode gain .................................................... 21
Figure 23. PSRR, differential gain as well as Vdd gain .............................................................. 22
Figure 24. Input common mode ranges between 0.34 and 1.65 V .............................................. 22
Figure 25. Single ended output swing range from .601-2.072 Volts........................................... 23
Figure 26. Noise voltage floor at 272.519 MHz .......................................................................... 23
Figure 27. Slew Rate and Settling Times Results........................................................................ 24
Figure 28. Slew Rate at VDC = 2.25 ........................................................................................... 24
Figure 29. GBW at VDC = 2.25 V .............................................................................................. 25
5. 5 | P a g e
Executive Summary
Our single ended operational OTA provides 80 dB gain with a unity gain bandwidth of 198
MHz and a 64.65 degree phase margin. Our circuit’s input common mode range is from 0.34-
1.65V and the output swing is 1.8 V peak to peak. The settling time of our circuit is well below
the 90nsec specification at 37.39nsec and the slew rate reaches 79.439 V/usec. The flicker noise
floor at 272.52 MHz has a value of 6.8181nV/√𝐻𝑧 . Finally the OTA dissipates only 1.029 mW.
Table 1. Project Specifications
Parameter Required Specification Achieved Specification
Low-Frequency Gain 80 dB 80 dB
Gain-bandwidth product >175 MHz 198 MHz
Phase Margin 75 degrees, w/ unity gain fb,
no external load
64.65 degrees
Settling time <90nsec with 4pF external
load
37.29 nsec
Output Swing 1.2 V-pk-pk single ended 1.4 V-pk-pk single ended
Input common-mode range Rail to rail operation (0-2.5V) 0.34 – 1.65
CMRR >100 dB 113.863 dB
PSRR+ >100 dB 73.4 dB
Supply Voltage 2.5V 2.5 V
Power dissipation Pdiss<12 mW 1.029 mW (409.97µsec)
Slew rate >18 V/usec 79.439 V/usec
Input referred noise voltage
floor
<10 nV/√𝐻𝑧 in white portion
Also, you must report the 1/f
frequency
6.8181 nV/√𝐻𝑧
at 272.52 MHz
Robustness You must simulate your
design over a +/- 10% supply
voltage and over the process
corners. The GBW product
and slew rate should be
maintained within 5%
Slew rate: 55.13466 V/usec at
2.25 V
GBW: 102.7981 MHz at 2.25
V
6. 6 | P a g e
OTA Design Discussion
Input Stage Design
Our initial plan was to implement rail to rail input common voltage to be able to obtain
wide input range, so we chose the rail to rail input design. The width and length ratios of transistors
were arbitrarily chosen to obtain similar gm in NMOS and PMOS transistor sides. Tail currents of
340µA on both the NMOS and PMOS sides were used which ultimately gave high slew rates. This
level of current allowed us to achieve the minimum of 80 dB gain.
Figure 1. Input design of main stage on the left and right
7. 7 | P a g e
Output Stage Design
In order to achieve the 80 dB of gain, we created a high output resistance output stage.
Since a single ended output was used, a diode connection was made from outn to Vbp2 as shown
below. Approximately ~170 uA flows through the top and bottom transistor. Furthermore the same
time the vdsats are maintained to a value lower than 0.2 V, which was designed to enable wide
input common mode range.
Figure 2. Output design of main stage
8. 8 | P a g e
Gain Boosting Op-Amp (Baby Op-Amp) Design
Since our output stage achieved around 58 dB of gain, our circuit required the
implementation of NMOS and PMOS gain boosting op amps. With addition of gain boosting
stages, we achieved total gain of 80 dB. The gain boosting stage utilizes a differential input, refer
to Fig. 3. The negative inputs of baby opamps are designed to have approximately Vdsat and Vdd-
Vdsat values for NMOS and PMOS transistors respectivey in output stage.
Figure 3. NMOS gain boosting op-amp design
Figure 4. PMOS gain boosting op-amp design
9. 9 | P a g e
Supply Independent Biasing Circuit Design
The biasing circuit was one of the most important designs. We decided to utilize the
constant gm biasing circuit that is less sensitive to changes coming from the Vdd supply.
Furthermore, upon biasing the transistors correctly, we were able to change the value of the current
developed by varying the resistor. Our circuit required the need for voltages ranging from ~0.2 to
2.3 V. We experienced difficulties with the obtaining voltages at these limits, especially the 2.3 V
bias.
Figure 5. Constant gm-biasing design
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Compensation
In order to ensure stability, we used capacitors for compensation in the main OTA stage as
well as the gain boosting amplifiers that we used in conjunction with our main stage. In the NMOS
gain boosting stage, we used a value of 250 fF for our compensation capacitor. The output results
of our baby op amps before and after compensation are presented below.
Figure 6. AC gain of NMOS gain boosting before compensation
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Figure 7. AC gain of NMOS gain boosting after compensation
The same plots are presented below for the PMOS gain boosting amplifier. In this case a
capacitor with a value of 500fF is used for compensation.
Figure 8. AC gain of PMOS gain boosting amplifier before compensation
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Figure 9. AC gain of PMOS gain boosting amplifier after compensation
In the main stage of our OTA, we used a capacitor value of 1.5pF in order to obtain the
appropriate phase margin. We did parameter sweep to determine the value of the compensation
capacitor. Higher capacitor values gave required phase margin, however, the gain bandwidth
product value decreased to approx. 100 MHz. Therefore, we kept the value of capacitor as 1.5 pF
to be able to meet the GBW requirement. With this capacitor value, we obtained the phase margin
value as around 64 degrees.
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Figure 10. Main gain stage before compensation
Figure 11. Main gain stage after compensation
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Circuit Schematics
In this section we will include parameter values and dc values of our circuit schematics.
These include the gain boosting NMOS and PMOS op-amps, the gain stage of the amplifier with
the gain boosting op-amps, as well as the biasing circuit.
Parameter Values
Figure 12. NMOS gain boosting amplifier parameter values
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Figure 13. PMOS gain boosting operational amplifer parameter values
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Figure 14. Biasing circuit parameter values
Figure 15. Main gain stage parameter values
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DC Operating Points
Figure 16. DC operating points of NMOS gain boosting op-amp
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Figure 17. DC operating points of PMOS gain boosting op-amp
Figure 18 DC operating point of biasing circuit
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Figure 19 DC operating points of main gain stage
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Results
In this section the test results performed according to provided testing tutorials.
a) Frequency response of the OTA
Figure 20. Frequency response of the OTA
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b) Common Mode Rejection Ration
Figure 21. CMRR, differential gain, and common mode gain
c) Power Supply Rejection Ratio
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Figure 22. PSRR, differential gain as well as Vdd gain
d) Input Common Mode Range
Figure 23. Input common mode ranges between 0.34 and 1.65 V
e) Output Swing Range
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Figure 24. Single ended output swing range from .601-2.072 Volts
f) Input-Referred Noise Voltage Floor
Figure 25. Noise voltage floor at 272.519 MHz
g) Slew Rate and Settling Time
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Figure 26. Slew Rate and Settling Times Results
h) Robustness
Figure 27. Slew Rate at VDC = 2.25
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Conclusion and Discussion
In this project we designed and built a single ended OTA with 0.25µm CMOS technology.
Our designed and simulated circuit achieved 80 dB low frequency gain, a unity gain bandwidth of
198 MHz, as well as a phase margin of 64.6 degrees. The input common-mode range is from 0.34
to 1.65 with an output swing range of 1.8V peak to peak.
Our initial goal was to build a fully differential amplifier. We first achieved the proper
gain, GBW, and phase margin with the single ended output. From here we constructed the common
mode feedback circuit that proved to lower gain significantly. The CMFB circuitry did not perform
well when upon differential voltage changes in output stage. Therefore, we did not include the
CMFB design in our project.
We also noticed that when we incorporated the biasing circuit (initially ideal current and
voltage sources were used), the current values on input stage and output stage varied slightly. To
be able to obtain close current values that we had with ideal current sources in input and output
stages, we increased the length of the diode connected and its complementary transistor to
eliminate the effect of channel length modulation.
We have not met the phase margin, PSRR, rail to rail input, and robustness specifications.
Including a Gm optimization stage that enables a constant Gm over a wide range of input voltages
(0-2.5V). Further optimization is necessary in sizes of the transistor to be able to meet the
requirements. Our circuit design had low power consumption (approx. 1mW). Since the required
power consumption value is less than 12mW, more focus can be obtained to use the power
efficiently to be able to meet most of the requirements.
References
[1] D.A. Johns and K. Martin, “Chapter 6 – Advanced Current Mirrors and OpAmps,” in Analog
Integrated Circuit Design, 1st
ed. New York, John Wiley & Sons, Inc., 1997, pp. 256-266.
[2] Analog Circuit Design Class Notes, Fall 2014.