This document discusses different control methods for offline power factor correction (PFC) converters, including average current mode control, peak current mode control, and analytical control law methods. It then focuses on describing a borderline current mode PFC design that uses constant on-time control to achieve power factor correction. The converter senses the inductor current and uses a multiplier and error amplifier to impose a sinusoidally varying peak current setpoint that is proportional to the rectified input voltage, causing the input current to follow a sinusoidal envelope and correcting the power factor. The on-time is kept constant over a line cycle in borderline mode, resulting in frequency variations as the off-time changes to maintain a constant switching period.

1. SIMULATIONS AND PRACTICAL DESIGNS OF OFF.LINE CONVERTERS-THE FRONT END 529
between the set point and the resr"rlting average current exists and guarantees a low dis-
tortion. Average control works without ramp compensation.
Average-mode control sufTers fi'om cusp distortion when the input voltage lies in the
vicinity of the 0 V area. In this region, the available slew rate is too weak, and the indr,rc-
tor cr"iruent will lag behind the set point for a short time, causing distortion.
. Peak current control: Similarly to the first structLlre we described, peak current control
imposes a sinusoidal waveform on the inductor current but keeps it continuous this time.
The technique lequires ploper adjustment of the ramp compensation; otherwise severe
instability occurs near the input zero transition. The addition of the ramp degrades the
resulting distortion, but solutions via the inclusion ofofTsets give adequate results. CCM
peak current-mode control is not very popular, and only a few controllers exist (ML48 I 2
from Failchild, fbr instance).
The CCM mode allows the implementation of PFCs beyond the kilowatt. However,
the boost diode recovery time heavily contributes to the power switch dissipation. and a
snubber on both devices has to be designed.
3. Analytical cotltrol /nw: Without sensing the rectified envelope as the above would do, the
controllel internally elaborates a control law which fbrces power factor conection. This is
the case fbr the NCPl60l (fixed-frequency DCM) or the NCPI653 (CCM) fron ON
Sen.riconductor. ICEIPCSOI/2 from Infineon or the IRI 150 from International-Rectifier
also works with a control law.
Rather than an in-depth description of each possible scheme, this chapter ofTels a quick guided
tour of the existing techniques and concentrates, at the end, on a BCM PFC design
.,t:_
6.2.12 Constant On-Time Borderline Operation - rr i --
When we stLrdied BCM in Chap.2,Eq. (2-222) tar"rght us that the average value of a BCM cur-
rent was equal to its peak divided by 2 (Fig.2-99):
(6-9s)
A BCM boost preconverter fbllows the architectule depicted by Fie.-6-25. here in u cullenr-
mode structut'e. Without the traditional bulk capacitor, the diode bridge delivers a full-wave
FIGURE 6-25 A borderline PFC architecture operated in current nrode: A multiplier sets the peak cul€ltt set
point via high-voltage sensing.
CoutCurrent sense
comparator
7

2. 530 CHAPTER SIX
rectifled sinusoidal signal. Mostly C,,, plays the role of an EMI filter but also avoids a real volt-
age decrease down to zero, saving some switching losses by restricting the duty cycle
excursion. A portion of the rectified signal brought by R,r,", and R,,,,.. feeds a multiplier Xo
whose other input receives the loop error signal from the transconductance amplifier G1 (a tra-
ditional op amp could also do the job). A capacitor C, rolls off the bandwidth to a low level
(around l0 Hz), avoiding the natural output ripple to be sensed by the loop. Therefore, at
steady state, the error amplifier outputs a flat dc signal. Why a low bandwidth? Remember, a
PFC must store and release energy. implying the presence of a low-frequency ripple on the out-
put (Fig. 6- l9b). If the loop detects it via the sensing network R,,,,,,..,./R,,,,,",., it will lock onto it and
a so-called tail chasing can occur. A strong bandwidth rolloff thus prevents this from happening.
Unfortunately, it tr.rrns the PFC into a slowly reacting preconverter: It yields an extremely poor
load transient response, the PFC Achille's heel.
Borderline operation requires inductor current sensing, and this is done here, via a t'ew turns
wound over the main inductor L. When the flux reaches zero (core reset), the voltage induced
on this auxiliary winding collapses and initiates a new switching cycle. The time needed by the
current to ramp down from the peak to zero depends on input and output conditions. Hence,
the frequency constantly changes, a typical characteristic of BCM converters.
Elaborated with the half-wave input voltage image via the multiplier, the error voltage V",.,
imposes a sinusoidally varying cycle-by-cycle set point to the inductor current. In other words,
the peak current set point changes as the rectified voltage moves up and down
where V,,,(t) represents the full-wave rectified input voltage.
The instantaneous input power P,,,(/) is obtained by muttiplying the instantaneous input
current and input voltage together. The instantaneous PFC input curent is actually a time-
continuous function ofthe individual inductor current averaged values over a switching cycle.
As the average current value obeys Eq. (6-95), Pi,,Q) fbllows Eq. (6-97):
v,,,Q)
/1./,.,,i(r) : it,,^
I L.,,",,k(t)
Pi,ft) :
, v,,,{t
2Pi,,(rl _ vi,,0),
Vi,,(il L "''
From this equation, the instantaneous on time easily comes out and is equal to
(6-e6)
(6-e7)
(6-98)
Extracting the peak current from the above and setting it equal to that of Eq. (6-96), we have
2Pi,,Q)L
(6-99)t.,(t) :
vi,,(t)2
Now, we know the instantaneous input power follows a squared sine law [Eq. (6-71), assum-
ing 1007o efficiencyl. Introdr"rcing the rms term V,,,. into the input voltage definition, we can
update Eq. (6-99):
4P,,,,,sin1(at)L
(6- r 00)
IV.,fi sin (at)]2
where V,,. : Vi,,,,,,,
In light of Eq. (6- 100), we can see that the on time is kept constant over a line cycle when
operating the boost in BCM. This is true not only for current mode, as we just saw, but also
fbr voltage mode as the on time naturally keeps constant via the error amplifier delivering a
2LP,,,,t
V,,,'

3. SIMULATIONS AND PRACTICAL DESIGNS OF OFF-LINE CONVERTERS-THE FRONT END 531
continuous voltage at steady state (no ripple passes through as the gain has been rolled off),
Finally, according to these steps, the input cument follows Eq. (6-101):
(6- 101)
Vt
where k : Lff remains constant. Equation (6- l0l ) confirms that the input curent follows a
sinusoidal envelope: We perform power factor corection! Figure 6-26 portrays the typical
waveforms obtained in a PFC convefter operated in borderline mode.
8.05m 8. 15m 8.25m
Time in seconds
8.35m
FIGURE 6-26 Typical wirvefbrms obrained on a BCM PFC.
6.2.13 Frequency Variations in BCM
During the on time, the switch closes and the curent ramps up to the peak imposed by the
envelope at which point the MOSFET opens. The inductor current ramps down until it
reaches 0: The inductor is told to be "reset." The contloller detects this fact and initiates a new
cycle. Looking atFig.6-26, you can observe a wide frequency variation thanks to the off'-time
modulation (/,,,, is constant). Again a f'ew analytical steps will let Lrs assess the fi-equency
changes across a complete line cycle.
The switching period equals the sum of the on and off times:
(r) = 4" (r)
Tn,:tu,,+t,41 (6-102)