This paper presents the design of the feedback loop for single controller power factor correction converters. The feedback loop design must account for the large second harmonic component of the rectified input voltage. The size of the bulk capacitor and the corresponding loop gain affect the converter's performance in terms of total harmonic distortion, discontinuous conduction mode operation, and output regulation. The paper provides design procedures and examples for a boost-forward power factor correction converter. Simulation and experimental results validate the design approach.

1. Design of the Feedback Loop for Single Controller
Power Factor Correction Converter
Kyu Chan Lee and Bo H. Cho
School of Electrical Engineering, Seoul National University
Shinlim-dong, Kwanak-ku, Seoul, 151-742, Korea
Phone: +82-2-880-1785 Fax: +82-2-878-1452
E-Mail: lkc@plaza.snu.ac.kr
Abstract - This paper presents the design of the feedback
loop for Single Controller (SC) Power Factor Correction
(PFC) converters which can regulate the output voltage
tightly. In the SC PFC converter, which needs a small
size bulk capacitor for the low cost, the loop gain design
requires input-to-output transfer function because
rectified input voltage has large harmonic components.
Two design examples are used to illustrate that the
capacitor size and corresponding loop gain affect the
converter performances such as THD, DCM conditions,
and output regulation. Proposed design procedures are
verified for Two Stage One Controller boost-Forward
PFC converter using computer simulations and
experimental results.
I. INTRODUCTION
Recently various types of Single Stage(SS) PFC
converters which integrate a PFC part and a dctdc
converter have been developed to minimize the cost for
low power applications. For above lOOW power
applications, the Two Stage One Controller (TSOC)
PFC converter is introduced as shown in Fig.1 in order
to overcome the excessive device stresses and poor
efficiency in SS PFC schemes. It consists of a PFC
boost converter operating in the discontinuous
conduction mode(DCM) followed by a dc/dc converter
as in a conventional two stage scheme, but a single
PWM controller is used as the SS PFC converter [l].
Generally, the TSOC PFC converter has the same
topological stage as in a SS PFC except the delay in the
gate pulse of the boost switch. This type of PFC
converter is called a Single Controller (SC) PFC
converter.
In the SC PFC converter, the feedback control loop
bandwidth must be much higher than twice the line
frequency to meet the output regulation and the
transient response specifications. In order to investigate
the feedback characteristics of the SC PFC converter, a
small signal model is needed. For this purpose, an
accurate small signal model based on harmonic analysis,
which is valid up to half of the switching frequency, is
developed [2]. It shows that in a SC PFC converter, the
high frequency small signal characteristics are similar
to those of a dcldc converter with absence of the PFC
boost dynamics. Thus, dynamics near the loop
0-7803-4489-8/98/$10.000 1998 IEEE
crossover frequency i.e. stability can be analyzed using
either the accurate model or the approximated model.
However, due to the rectified ac line voltage,
considerable second harmonic ripple of the input
voltage exists at the bulk capacitor. In designing the
feedback loop, the amount of the feedback gain at
second harmonic frequency influences the operating
condition such as the DCM condition and the input
current distortion due to the feedback action in the duty
ratio. This is especially true for a PFC converter using a
minimum sized bulk capacitor for low cost while
meeting the hold-up time requirement.
In this paper, influences of the second harmonic
ripple in the closed loop system are analyzed by the
simplified small signal model using the harmonic
analysis. Design of the feedback loop considering the
capacitor size, output regulation, and power factor (or
THD) while maintaining the DCM condition is
presented. The analysis and design are performed for
the SS dither Boost PFC and the TSOC Boost-Forward
PFC converters. The results are verified through
simulations and experiments.
899
1 . FEEDBACK DESIGN CONSIDERATIONS
1
LOOP
t
dB
I
T
Vrei
&
Fig. 1 The diagram of SC PFC convertex
Fig. 1 shows the diagram of the off-line SC PFC
converter. In case of the TSOC PFC converter
employing the delay control, the switch S2 is controlled
to regulate the dc output voltage, and the switch S1 is
controlled for reduction of the capacitor voltage and

2. 2.5 then this values can be regarded as constant, 0.8 and
1)
Also, at this frequency range, output voltage of the
second stage converter which operates in CCM can be
approximated Eq.'s (2) and (3).
DCM operation at the same time, without frequency
modulation. A simple delay scheme using only the gate
drive single for S2 and the output of the feedback
control voltage, controls the capacitor voltage within a
designed range depending on the operating condition.
Therefore the TSOC PFC converter has a delay gain,
K1 which is more than 1 and constant offset, K2
between the duty ratio of the PFC switch S1 and dc-dc
converter switch S2. In case of the SS PFC converter,
because the PFC switch SI and dc-dc converter switch
S2 are same, there exists no delay gain, i.e. KI=l and
K2=0.
In order to design the feedback loop, small signal
model is needed. Fig. 2 shows the simplified small
signal model for SC PFC converter. In Fig. 2, GdF the
is
duty ratio to output voltage transfer function, G," is the
input voltage to output voltage transfer function of the
second dcldc converter. G ) is the duty ratio to output
voltage transfer function and G," is the input voltage to
output voltage transfer function of the DCM boost PFC
converter.
h
vc
(3)
-
By Eq's. (1) (3), low frequency control to output
transfer function of the SC PFC converter can be
obtained by Eq. (4)
(4)
At the high frequency range above the second
harmonic frequency of the input voltage, the control to
output transfer function of DCM boost converter can be
derived by the conventional state space averaging
method as shown in Eq. (5). Because DC and low
frequency ripples can be regarded as steady state
variables.
GvF
-
-
Fig.2 small signal block diagram of SC PFC converter
At the low frequency range below the second
harmonic frequency of the input voltage, the cascaded
dcldc converter is considered as a constant power load
because output voltage can be regulated tightly.
Therefore a small signal model can be derived by the
well-known method for DCM boost PFC pre-regulator
using the power balance [ 3 ] .Control to output transfer
function is shown in Eq. (1).
2M-1
1
where, w p z = M - 1 RpC,
By the same method, the control to output transfer
function of the SC PFC converter can be obtained by
Eq. (6).
where, H(s) =
where d s = K l dF
l+s/q
l+s/Qq + s 2 / g
By Eq's. (5) and (6), high frequency control to
output transfer function of the SC PFC converter can be
obtained by Eq. (7) because Wp2 is much lower than
the resonant frequency of output filter, WO.Thus first
term of Eq.(6) can be neglected.
K P = 2 L , f l R p , RP = V c 2 1 P , , , , M = V < l V ,
fa,, ha,, : function of M ( If the M is larger than
900

3. In PFC converters with the rectified AC voltage,
there exists the bulk capacitor voltage ripples at
harmonic frequencies of the input voltage. The
amplitude of the ripple voltage can be calculated by a
linearized input-to-output transfer function. This
function can be derived by fourier transformation of the
rectified input voltage and linearizing the square
function [4]. This is shown in Eq. (8) and is valid only
at harmonic frequencies of the input voltage.
where,
where, w, is the line frequency and Sp is the
regulation specification.
As shown in Eq. (9), the higher the feedback gain is
selected the output ripple becomes lower, but the
magnitude of duty ratio variation at the second
harmonic frequency becomes larger at the steady state.
This affects the PFC coiiverter performances such as
the DCM condition and the input current distortion.
Using the harmonic analysis, the capacitor voltage and
the duty ratio can be approximated as shown in Eq.( 11)
taking the dominant component at second harmonic
frequency.
vc = Vc - Avcsin2 6 , d, = D, +- Ad,sin26
where,
(1 1)
6=o t
,
FMA(2@,)D,/n
AdF =--
Total control to output transfer function using the
low and high frequency control to output transfer
function is sketched as shown in Fig. 3.
The reset duty ratio d.zB the DCM Boost converter
of
is shown as
d,, =
IGl
Fig. 3 The sketch of control to output for SC PFC
converter
i. =In
I
+
G
:
G; bow
:
AVc ho'Spx 5,
low f f 4(2Cq.j
m
0
'
2Llfi
(DB + AdZB.sin28 ) V g (sin 8
1
V , - Avc:;in2 B
V , - Av,sin2 8- V g I sin
frequency is shown as
sw=
vc- Av'sin2 6 -
Harmonics of the input current of the SC PFC
converter with the feedback loop closed as shown in Eq.
(15).
As shown in Fig. 3, the SC PFC converter has the
same small signal model in a conventional dc/dc
converter except for a larger gain at a low frequency
range. But the SC PFC has large output voltage ripples
at second harmonic frequency of input voltage. In order
to regulate the output voltage within the specified limit,
the required feedback gain FMA at second harmonic
v
o
1 + F ' M A ( 2 q ) V o / D , Avc
t)l
sign(sin 0)
(15)
(9)
Total harmonic &stortion (THD) of the line current
can
(15)
where, Avc Iz0=l GVBf i V g / 3
I
901
be calculated by the fourier transformation of Eq.

4. THD =
~
controller drives the switches for the PFC part and the
dcldc converter part differently to make the capacitor
voltage within the optimal range. Because the gain of
the delay controller is more than 1, the TSOC PFC
converter has larger variations in the duty ration than in
the SS PFC converter.
&-?-x 1OO[%]
I,
111.
DESIGN EXAMPLE
Two design examples are used to illustrate the
previously described harmonic analysis taking the
following requirements into consideration of
.3OA
- Output regulation
- DCM condition
4.5A
- THD
- Stability
- Control bandwidth
A . SS Dither Boost PFC converter
Specifications of the 1OOW SS PFC converter are as
follows. Input voltage is 90-132V, output voltage and
current are 5V and 20A. Parameter values of the power
stage are L1=64.5uH, n=l1.5, L2=30uH, C2=3000uF,
f=70kHz.
Fig. 4 shows the relations of the feedback loop gain
at 120Hz and boundary condition of DCM and THDs
with respect to the bulk capacitor by Eq. (14) and (16).
Using these simulation results, the feedback loop gain
and the smallest capacitor size can be designed. While
the capacitor value increases beyond 15uF in this
example, the DCM condition can be maintained. The
magnitude of the feedback gain is determined by the
control loop bandwidth and THD requirement.
As shown in Fig. 4, if the capacitor of 15uF is
selected, the range of the feedback gain, FMA should
be between 2.4 and 3.5.
Vrel
I
Fig.5 TSOC PFC converter
Specifications are that input voltage is 90-264V
and output voltage and current are 5V, 30A, 12V,4.5A.
Parameter values are L=lO5uH, n=17.5, L1=18uH,
L2=2uH, L3=2uH, C1=1500uF, C2=15OOuF, C3=luF,
C4=1500uF, f=62kHz. The gain of delay controller K1
equals 6
Fig. 6 shows the similar trends as in Fig. 4. In this
example, for the low cost, bulk capacitor of IOOUF is
selected and the possible FMA is between 0.55 and
1.15.
18
55
17
50
16
A
45
THI5
p
l
DI
%] 14
%.I
35
13
30
12
11
25
10
0
20
1
15
2
25
3
FMA(Zw)
3.5
4
45
5
2
3
4
5
FMA(2w)
Fig. 6 DCM conditions and THDs
Fig. 4 DCM conditions and THDs
B.
1
TSOC Boost Forward PFC converter
Fig 5 shows the 200W TSOC PFC converter which
resembles the conventional two stage schemes.
However a single PWM controller with a simple delay
902
In Fig. 7, the values of FMA are selected outside of
the range to verifie the design curves for the capacitor
value of 100uF. In Fig. 7(a), FMA is 1.65 to show that
the TSOC PFC converter does not operate in DCM. In
Fig. 7(b), for FMA is 0.25, output voltage ripples
exceeds the regulation specification.

5. . 30dB
- ZOdB
. lOdB
.
OdB
5
. -1OdB
a
2
. -20dB
U
&
. -30dB
Frequency[ Hz]
Fig. 8 measured and simulated control to output
trans fer function
Using this control to output transfer function and
the constraints in the feedback gain, a three-pole twozero feedback controller is designed and the loop gain
characteristic is shown in Fig. 9.
(a) FMA=1.65 ( AVo = lOmV )
I
I
I(G5)*10
v
I
I
~
I
I
I
5
U(ui)
-
I
I
vo
.
I
0
I
U
I
~I
7
I
Fig. 9 loop gain T(FMA=0.55)
(b) FMA=0.25 ( AVo = 100mV )
Fig. 7 TSOC PFC converter simulation results
IV.
EXPERIMENTAL
RESULTS
The control to output transfer function for a TSOC
PFC converter is measured through a network
analyzer(HP8751A). Fig. 8 shows the measured and
simulated control to output transfer functions for TSOC
PFC converters. It can be observed that the predicted
result and measured one are quite well matched. The
measurement conditions are as follows;
input voltage=90V, output power =10OW, Cl=lOOuF.
Fig. 10 shows the rectified line current, line voltage,
capacitor voltage and output voltage ripples to
investigate the effect of .the feedback gain which is used
lOOuF capacitor in case of FMA=1.65 and FMA=0.25.
As shown in Fig. lO(a), output voltage can be
maintained within 50mV specifications, but this
converter operates in CCM and THD is very large. Fig.
10(b) can not regulate: the output voltage while it
maintain to operate in DCM. This experimental results
are well matched with simulation results as shown in
Fig. 7 and verify the design curves in Fig. 6.
Fig. 11 shows the rectified line current, voltage and
output voltage ripples which is used FMA of 0.55 in
case of C=220uF and 100uF. It is shown that if the
same feedback gain is used output voltage ripple is
lower as the increasing bulk capacitor size.
903

6. 26-Feb-98
25-Feb-98
19:55.39
F1mmv
5
0.1
v oc
2 5 "U RC I
3 . 1 V DC
4
10 "U
BWL
8s
1
28 XS/s
4 DC4.2nV
RC
0 STOPPED
0 STOPPED
(a) Case I (FMA=1.65)
(a) Case I (C=220uF)
25-Feb-98
25-Feb-98
5 1s
BWL
0 . 1 v DC
2 5 PIV AC i
3 . 1 V DC
4 I0 R V AC
T
28 I . S ~
TRIGGER SETUP
T
0.1
20 hS/s
J-
v
DC
1 5 PIv RC g
3 . 1 v DC
4 10 PIV RC
tine
0 STOPPLO
(b) Case I1 I (FMA=0.25)
20
1
1
hS/S
DC80"V
U STOPPED
(b) Case I1 (C=lOOuF)
Fig. 10 the rectified line current, voltage and output
voltage ripples(C=l OOuF)
Fig. 11 the rectified line current, voltage and output
voltage ripples (FMA=O.55)
REFERENCES
V. CONCLUSION
Design of the feedback loop for the Single
Controller Power Factor Correction converters
considering influences of the 120Hz harmonics to the
operating condition and the input current distortion are
presented. The design procedures taking into account of
various performances such as THD, DCM conditions,
output regulation, and loop speed with respect to the
size of the bulk capacitor using two types of SC PFC
converters: Single Stage Dither Boost PFC converter
and Two Stage One Controller Boost Forward PFC
converter. Time simulation results are presented to
verify the analysis and design curves, and hardware
experimental results are provided for the verification of
this analysis.
904
[I] K.C.Lee and B.H.Cho, " Low Cost Power Factor
Correction(PFC) Converter Using Delay Control," PCCNagaoka'97, pp .335 -340
[2] J.Y.Choi and B.H.Cho, " Small-Signal Modeling of Single-phase
Power-Factor Correcting AC-DC Converters : A Unified
Approach," Intemal Report 1997, Power Electronic Research
group, SNU
131 James Lazar and Slobovan Cuk, " Feedback Loop Analysis for
AC/DC Rectifiers Operating in Discontinuous Conduction
mode." APEC'96, pp.797-SO6
[4]Michihiko Nagao, etc, " Analysis of High Power Factor AC-DC
Boost Converter," T.IEE Japan, pp.1139-1148, vol.ll4-D, no. 11,
'94