In recent years Sigma-Delta ADCs became one of the most popular types of Analog-to-Digital converters. The key features of these are high-speed, high resolution and low operating voltages. These are commonly used in variety of applications like digital audio CDs, CODEC, biomedical sensor applications and wireless transmitters/receivers. The basic principles involved in this technique are oversampling and noise shaping. This report reviews different techniques proposed for high resolution, low power Sigma-Delta ADC. Conventional design of SDM was dominated by discrete time architecture but in modern designs continuous types are also becoming famous because of their low power attributes. Continuous efforts have been taken to reduce the supply voltages of SDM and recently, lowest reported is 250mv.
Salient Features:
The magnitude response is nearly constant(equal to 1) at lower frequencies
There are no ripples in passband and stop band
The maximum gain occurs at Ω=0 and it is H(Ω)=1
The magnitude response is monotonically decreasing
As the order of the filter ‘N’ increases, the response of the filter is more close to the ideal response
Salient Features:
The magnitude response is nearly constant(equal to 1) at lower frequencies
There are no ripples in passband and stop band
The maximum gain occurs at Ω=0 and it is H(Ω)=1
The magnitude response is monotonically decreasing
As the order of the filter ‘N’ increases, the response of the filter is more close to the ideal response
FPGA are a special form of Programmable logic devices(PLDs) with higher densities as compared to custom ICs and capable of implementing functionality in a short period of time using computer aided design (CAD) software....by mathewsubin3388@gmail.com
This presentation gives an overview of FPGA devices. An FPGA is a device that contains a matrix of re-configurable gate array logic circuitry. When a FPGA is configured, the internal circuitry is connected in a way that creates a hardware implementation of the software application.
FPGA devices can deliver the performance and reliability of dedicated hardware circuitry.
FPGA are a special form of Programmable logic devices(PLDs) with higher densities as compared to custom ICs and capable of implementing functionality in a short period of time using computer aided design (CAD) software....by mathewsubin3388@gmail.com
This presentation gives an overview of FPGA devices. An FPGA is a device that contains a matrix of re-configurable gate array logic circuitry. When a FPGA is configured, the internal circuitry is connected in a way that creates a hardware implementation of the software application.
FPGA devices can deliver the performance and reliability of dedicated hardware circuitry.
This presentation is about AUTOSAR CAN stack. it provides an overview about:
- Included modules
- How modules communicate with each other
- Transmission and reception of frames
- changing network states
please let me know in the comments if you have any enhancements or feedback.
ADC - Analog to Digital Conversion on AVR microcontroller Atmega16Robo India
Robo India in this PPT is explaining on the most crucial and important aspect of Embedded system, robotics, automation and physical computing.
Analog to digital conversion is required in almost every project of above mentioned domain. One advantage to use a AVR micro controller is that it has inbuilt ADC thus we donot need to use external system for ADC.
Here Robo India is teaching how to use ADC in AVR series microcontrollers.
We welcome your views and queries, we are found at-
website: http://roboindia.com
mail- info@roboindia.com
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Know more about the various device drivers and the layered architecture of the AUTOSAR MCAL. And get the details about how the Microcontroller Abstraction Layer (MCAL) works
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In this AUTOSAR layered architecture, Communication Stack or ComStack facilitates communication. Hence ComStack can be defined as a software stack that provides communication services to the Basic Software Modules and Application Layer or Application Software.
https://www.embitel.com/product-engineering-2/automotive/autosar/
Design of Continuous Time Multibit Sigma Delta ADC for Next Generation Wirele...IJERA Editor
This paper presents the design of CT ΣΔ modulator which can provide high DR and SNR over a 20 MHz signal bandwidth. So far all the CT SDM uses either feedback or feedforward loop filter architecture. The proposed topology is a 3rd order low-pass sigma-delta modulator, which employs a combination of feedforward and feedback schemes. Loop filter is designed as RC integrators due to its high linearity and easy interface. The design starts from system level using Matlab/Simulink. Then, the first integrator in the loop, which is the most critical block in the modulator, is implemented at transistor level using Cadence Virtuoso 180 nm CMOS technology.
CMOS Analog IC design by Dr GS Javed - Refresher Course - Batch 1Javed G S, PhD
Topics covered in the course
1. DC Biasing of the circuits
2. Circuits for reference voltage and current generation
-Voltage Regulator
-BGR
-LDO
-V-to-I
3. Precision Current References
4. Opamp design for Analog to digital converters
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- Buffer
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- Current and Voltage circuits
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-Near Nyquist performance of Opamp for ADC Circuits
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-Simulation time for performance
-Resistors – their variation and Calibration
-Switch design for S/H
-CDAC
8. On-Chip Inductors
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parameters were simulated using Cadence Spectre- RF simulator. The designed Low Noise Amplifier
achieves a power gain of 22 dB and a minimum Noise Figure of 3 dB is achieved. It dissipates 12.5 mW of
power out of 1.8 V supply.
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Runway Orientation Based on the Wind Rose Diagram.pptx
Sigma-Delta Analog to Digital Converters
1. Sigma-Delta Analog to Digital Converters
(ADCs)
Satish Patil
Dept. of Electrical Engineering
Indian Institute of Techology, Bombay
(IIT Bombay) Sigma-Delta ADC 1 / 29
2. Outline
Basic principle
Eect of oversampling and noise shaping
1st and 2nd -order modulator (MOD1 and MOD2)
Eect of Noise shaping on total noise
Issues in modulator design
Discrete and Continuous time realization
Inherent anti-aliasing property of CT modulators
Eect of Quantizer bits
Maximum stable amplitude
Loop
4. Block diagram of ADC
General bolck diagram
2 major parts- Modulator and Decimator
(IIT Bombay) Sigma-Delta ADC 3 / 29
5. Basic principle of Sigma-Delta () modulator
Oversampling + Noise shaping
Oversampling: sampling input signal with frequency multiples of
Nyquist rate - Over Sampling Ratio (OSR)
Noise shaping: selecting proper loop transfer function such that
spectral density of inband noise can be reduced
Key features: coarse quantization,
6. ltering,feedback
Quantization is often quite coarse (1 bit!), but the eective resolution
can still be as high as 10-22 bits.
(IIT Bombay) Sigma-Delta ADC 4 / 29
7. Eect of oversampling and noise shaping
0
Reference: Industrial Sigma Delta Convertors Overview, Analog Devices Webcast Technical Seminar Series
(IIT Bombay) Sigma-Delta ADC 5 / 29
8. 1st-order modulator (MOD1)
Vo(z) = Ui (z):z1 + En(z):(1 z1)
STF = z1; NTF = (1 z1)
out of band gain (gain at z = 1) or jjHjj1 = 2
jNTF(ej!)j j!
= j1 ej!j = je
2 ej!
2 j = 2sin(!2
) at low
frequencies(approx.) jNTF(ej!)j !
(IIT Bombay) Sigma-Delta ADC 6 / 29
10. Noise performance
Inband Quantization noise power = 2
12
R
OSR
0 jNTF(j!)j2d!
For 1st order SDM,
Inband Quantization noise power = 2
12
R
OSR
0 !2d! = 2
12
13
3
OSR3
For every doubling in OSR, noise power decreases by factor of 8 hence
increase in eective no. of bits (ENOB) 1.5bits
For 2nd order SDM,
Inband Quantization noise power = 2
12
R
OSR
0 !4d! = 2
12
15
5
OSR5
Increase in ENOB for every doubling in OSR 2.5bits1
1
Reference: online video lectures of VLSI Data conversion circuits(EE658), IIT Madras
(IIT Bombay) Sigma-Delta ADC 8 / 29
11. Noise shaping
Figure: Noise shaping vs order Figure: zoomed portion
Out of Band gain increases with very rapidly with increase in
modulator order
Better inband, Worst out of band noise performance!
(IIT Bombay) Sigma-Delta ADC 9 / 29
12. Eect of Noise shaping on total noise
Total Q. noise power is calculated by 2
12
R
0 jNTF(j!)j2d!
MOD1: with only oversampling, STF = 1, NTF = 1, total noise
power is 2
12
with oversampling noise shaping, STF = 1,
NTF = (1 z1), total noise power is 2
12 2 = 22
12
MOD2: with only oversampling, STF = 1, NTF = 1, total noise
power is 2
12
with oversampling noise shaping, STF = 1,
NTF = (1 z1)2, total noise power is 62
12
Noise shaping results in increase in total Q.noise!
this phenomenon even gets worse for higher order modulators
Total P
noise can also be derived using Parseval's theorem:
2
12
k
h2(k) = 2
12
R
0 jNTF(j!)j2d!
(IIT Bombay) Sigma-Delta ADC 10 / 29
13. Issues in modulator design
SNR for oversampled noise shaping converter is
SNRdB = 6:02B + 1:76 + 10log ( 2L+1
2L ) + (2L + 1)log10(OSR) where,
B=quantizer bits
L=order of modulator
OSR=oversampling ratio
Ways to improve SNR
i. increasing loop order
ii. increasing OSR
iii. increasing quantizer resolution
Higher order modulators are highly unstable. This issue can be
addressed by using multi stage noise shaping (MASH) architecture.
quantizer overloading issue can be checked by MSA simulation
(IIT Bombay) Sigma-Delta ADC 11 / 29
14. Block diagram of CT and DT ADC
Contineous-time SDM provides inherent anti-aliasing
performance of CT is highly volatile to shape of pulse used for DAC2
2
source: Jose M de la Rosa. Sigma-delta modulators: Tutorial overview, design guide, and state-of-the-art
survey. Circuits and Systems I: Regular Papers, IEEE Transactions on, 58(1):121, 2011
(IIT Bombay) Sigma-Delta ADC 12 / 29
15. SNR vs OSR
Figure: SNR vs oversampling ratio for dierent modulator orders3
3
All MATLAB simulations are carried using R.Schreier, Toolbox, online available :
http://www.mathworks.com/matlabcentral/
18. lter
Figure: 1st order continuous time modulator
(IIT Bombay) Sigma-Delta ADC 14 / 29
19. Inherent anti-aliasing property of CT modulators...
Figure: CT MOD1 after block adjustment
(IIT Bombay) Sigma-Delta ADC 15 / 29
20. Inherent Anti-Aliasing property of CT modulators...
Figure: Frequency response of MOD1 CT modulators
unlike DT modulator, response to and 1 + is not same.
For higher orders, alias rejection response of CT modulators gets
better and better!
(IIT Bombay) Sigma-Delta ADC 16 / 29
21. Eect of Quantizer bits
nLev SNR(in dB) MSA=VRef
2 135 0.703
4 141.8 0.834
8 149.3 0.874
16 157.4 0.889
32 163.4 0.894
64 166.4 0.898
Results shown above are for order=3, OSR=256, N=8192
Risbo's method is used for calculation of MSA.
(IIT Bombay) Sigma-Delta ADC 17 / 29
23. Maximum Stable Amplitude(MSA)
Idea: apply slowly increasing ramp input over suciently large points
(1 Mega points) and
24. nd when y crosses threshold point.
Figure: input ramp and observed output of modulator
(IIT Bombay) Sigma-Delta ADC 19 / 29
25. MSA cont'd
Figure: time domain output of waveform used to calculate MSA
MSA: 90% of input where y blows away (in this case, y blows away
for input=0.97 of fullscale)
(IIT Bombay) Sigma-Delta ADC 20 / 29
27. lter architectures
Feedback topologies
I Cascade of Integrators Feedback form (CIFB)
I Cascade of Resonators Feed-forward form (CRFB)
lower power consumption at expense of higher distortion and
complexity of multiple feedback DACs
Feed-forward topologies
I Cascade of Integrators Feedback form (CIFF)
I Cascade of Resonators Feed-forward form (CRFF)
Low signal distortion.
only one DAC is required in feedback loop but extra ampli
28. er is needed
to accurately sum up input and integrator output4
4
J. Silva, U. Moon, J. Steensgaard, and G. Temes. Wideband lowdistortion delta-sigma ADC topology,
Electron. Lett., vol. 37, no. 12, pp. 737-738, Jun. 2001.
(IIT Bombay) Sigma-Delta ADC 21 / 29
33. rst modulator converts the
analog input signal
Each subsequent modulator
converts the quantization error
from the previous modulator
The quantization noises are
digitally cancelled
This gives a higher order of
noise shaping, without causing
instability
(IIT Bombay) Sigma-Delta ADC 23 / 29
34. Multi-stage (Cascaded) modulators...
y1(z) = x1(z)z1 + e1(z)(1 z1) and
y2(z) = e1(z)z1 + e2(z)(1 z1)
so output y(z) = y1(z)z1 + y2(z)(1 z1)
) y(z) = x(z)z2 + e2(z)(1 z1)2
Advantage: 2nd order noise shaping is achieved though 1st order loop
is implemented
However, cancellation of e1 is not perfect since the analog transfer
functions are not ideal
(IIT Bombay) Sigma-Delta ADC 24 / 29
36. cations:
I input frequency=500Hz
I SNR 100dB (16 bit resolution)
I use 1-bit quantizer
we design modulator for 17 bit resolution. 1st and 2ndorder loop
37. lters improves SNR by 9dB (1.5bits) and 15dB (2.5bits) per octave.
increment needed in resolution=16 bits, hence
I If L=1, then OSR 2
16
1:5 ) OSR = 2048
I If L=2, then OSR 2
16
2:5 ) OSR = 256
since case of 2048 OSR is dicult to implement we go for OSR=256,
order=2. NTF obtained using these specs:
TF = z22z+1
z21:225z+0:441
for 2nd order modulator H(1) = 2, we select jjHjj1 = 1:5 which
ensures stability and avoid quantizer overload
(IIT Bombay) Sigma-Delta ADC 25 / 29
39. Design Example...
SNR achieved from simulations: 100.9dB
MSA obtained by Risbo's method: 90% of Vref
for CRFB topology coecients obtained are as:
a : 0.2163 0.5585
g : 5.0199e-05
b : 0.2163 0.5585 1.0000
c : 1 1
(IIT Bombay) Sigma-Delta ADC 27 / 29
40. References I
Jose M de la Rosa.
Sigma-delta modulators: Tutorial overview, design guide, and state-of-the-art survey.
Circuits and Systems I: Regular Papers, IEEE Transactions on, 58(1):1{21, 2011.
Shanthi Pavan and Prabu Sankar.
Power reduction in continuous-time delta-sigma modulators using the assisted opamp technique.
Solid-State Circuits, IEEE Journal of, 45(7):1365{1379, 2010.
Youngcheol Chae and Gunhee Han.
Low voltage, low power, inverter-based switched-capacitor delta-sigma modulator.
Solid-State Circuits, IEEE Journal of, 44(2):458{472, 2009.
Chia-Ling Chang and Jieh-Tsorng Wu.
A 1-v 100-db dynamic range 24.4-khz bandwidth delta-sigma modulator.
In Circuits and Systems (ISCAS), 2013 IEEE International Symposium on, pages 813{816. IEEE, 2013.
Dushyant Juneja, Sougata Kar, Procheta Chatterjee, and Siddhartha Sen.
Design of delta sigma modulators for integrated sensor applications.
Control Theory and Informatics, 3(2):25{34, 2013.
J Silva, U Moon, J Steensgaard, and GC Temes.
Wideband low-distortion delta-sigma adc topology.
Electronics Letters, 37(12):737{738, 2001.
Fridolin Michel and Michiel SJ Steyaert.
A 250 mv 7.5 w 61 db sndr sc modulator using near-threshold-voltage-biased inverter ampli
41. ers in 130 nm cmos.
Solid-State Circuits, IEEE Journal of, 47(3):709{721, 2012.
(IIT Bombay) Sigma-Delta ADC 28 / 29
42. References II
Younghyun Yoon, Hyungdong Roh, Hyuntae Lee, and Jeongjin Roh.
A 0.6-v 540-nw delta-sigma modulator for biomedical sensors.
Analog Integrated Circuits and Signal Processing, pages 1{5, 2013.
Hao Luo, Yan Han, Ray CC Cheung, Xiaopeng Liu, and Tianlin Cao.
A 0.8-v 230-w 98-db dr inverter-based modulator for audio applications.
2013.
(IIT Bombay) Sigma-Delta ADC 29 / 29