This document discusses the design and simulation of low noise amplifier (LNA) circuits with different matching circuit combinations at the input and output sides. It compares the performance of LNA circuits using 'T' and 'L' type matching networks. The circuits are simulated using Advanced Design System (ADS) software. Simulation results show that the T-L matching configuration provides better gain and noise figure than L-L, L-T, and T-T matching under stability conditions. Specifically, the T-L matching achieved a forward gain of 14.14 dB and noise figure of 1.81 dB, outperforming the other matching configurations. Stabilization circuits are also applied and analyzed.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Optimization of Cmos 0.18 µM Low Noise Amplifier Using Nsga-Ii for UWB Applic...VLSICS Design
A design and optimization of 3-5 GHz single ended Radio Frequency (RF) Low Noise Amplifier (LNA) for
ultra-wide-band (UWB) applications using standard UMC 0.18 μm CMOS technology is reported.
Designing of RF circuit components is a challenging job, since even after performing lengthy calculations
and finding parameter values it is less guarantee that the design performs as expected. In view of this the
optimization tool; Elitist Non-Dominated Sorting Genetic Algorithm (NSGA-II); has been employed to get
the optimized starting values of components in the proposed LNA design. The obtained NSGA-II
parameters were simulated using Cadence Spectre- RF simulator. The designed Low Noise Amplifier
achieves a power gain of 22 dB and a minimum Noise Figure of 3 dB is achieved. It dissipates 12.5 mW of
power out of 1.8 V supply.
A 2.4 ghz cmos lna input matching design using resistive feedback topology in...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
A 2.4 ghz cmos lna input matching design using resistive feedback topology in...eSAT Journals
Abstract The attempt made in the paper shows an innovative designing for the enhancement and reliability in CMOS technology. A 2.4 GHz resistive feedback narrowband noise amplifier (LNA) using a series inductor input matching networks. It is easy reliable with an extra gm boosting as well as inductively degenerated topology. By using this resistive feedback topology increases the gain as well as noise figure of 2.2 dB,S21 parameter of 26dB,and IIP3 of -13dBm,while 2.8mW of power consuming from a 1.2V and its area 0.6mm2 in 0.13μm CMOS ,which gives the best figure of merit and performance. Keywords: LNA, CMOS, noise figure, resistive feedback, gm boosting, voltage gain boosting.
Design of 10 to 12 GHz Low Noise Amplifier for Ultrawideband (UWB) SystemIJECEIAES
Balanced amplifier is the structure proposed in this article, it provides better performance. In fact, the single amplifier meets the specification for noise figure and gain but fails to meet the return loss specification due to the large mis-matches on the input & outputs. To overcome this problem one solution is to use balanced amplifier topography. In this paper, a wide-band and highgain microwave balanced amplifier constituted with branch line coupler circuit is proposed. The amplifier is unconditionally stable in the band [9-13] GHz where the gain is about 20dB. The input reflection (S11) and output return loss (S22) at 11 GHz are -33.4dB and -33.5dB respectively.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Optimization of Cmos 0.18 µM Low Noise Amplifier Using Nsga-Ii for UWB Applic...VLSICS Design
A design and optimization of 3-5 GHz single ended Radio Frequency (RF) Low Noise Amplifier (LNA) for
ultra-wide-band (UWB) applications using standard UMC 0.18 μm CMOS technology is reported.
Designing of RF circuit components is a challenging job, since even after performing lengthy calculations
and finding parameter values it is less guarantee that the design performs as expected. In view of this the
optimization tool; Elitist Non-Dominated Sorting Genetic Algorithm (NSGA-II); has been employed to get
the optimized starting values of components in the proposed LNA design. The obtained NSGA-II
parameters were simulated using Cadence Spectre- RF simulator. The designed Low Noise Amplifier
achieves a power gain of 22 dB and a minimum Noise Figure of 3 dB is achieved. It dissipates 12.5 mW of
power out of 1.8 V supply.
A 2.4 ghz cmos lna input matching design using resistive feedback topology in...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
A 2.4 ghz cmos lna input matching design using resistive feedback topology in...eSAT Journals
Abstract The attempt made in the paper shows an innovative designing for the enhancement and reliability in CMOS technology. A 2.4 GHz resistive feedback narrowband noise amplifier (LNA) using a series inductor input matching networks. It is easy reliable with an extra gm boosting as well as inductively degenerated topology. By using this resistive feedback topology increases the gain as well as noise figure of 2.2 dB,S21 parameter of 26dB,and IIP3 of -13dBm,while 2.8mW of power consuming from a 1.2V and its area 0.6mm2 in 0.13μm CMOS ,which gives the best figure of merit and performance. Keywords: LNA, CMOS, noise figure, resistive feedback, gm boosting, voltage gain boosting.
Design of 10 to 12 GHz Low Noise Amplifier for Ultrawideband (UWB) SystemIJECEIAES
Balanced amplifier is the structure proposed in this article, it provides better performance. In fact, the single amplifier meets the specification for noise figure and gain but fails to meet the return loss specification due to the large mis-matches on the input & outputs. To overcome this problem one solution is to use balanced amplifier topography. In this paper, a wide-band and highgain microwave balanced amplifier constituted with branch line coupler circuit is proposed. The amplifier is unconditionally stable in the band [9-13] GHz where the gain is about 20dB. The input reflection (S11) and output return loss (S22) at 11 GHz are -33.4dB and -33.5dB respectively.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
A Novel Architecture for Different DSP Applications Using Field Programmable ...journal ijme
This paper presents a reconfigurable processor for different digital signal processing applications. The performance of the proposed architecture has been evaluated by taking different dsp applications like Low pass filter, high pass filter, finite impulse response (FIR) filter and FFT module. We designed the architecture of the processor and realizing the architecture using adder, multiplier, delay unit and validate it in the FPGA, which show that the hardware scheme is feasible for practical application. The experimental results clearly reveal the novelty of the architecture for dsp applications. This paper investigates the potential use of FPGAs for implementing efficient “Reconfigurable Processor” for different dsp applications. The proposed processor is based on parallel re-configurable which is implemented on FPGA. FPGAs have become an important component for implementing these functions with respect to cost, performance and flexibility. The general purpose SPARTAN 3AN FPGA kit has been employed for developing reconfigurable processor, with all the coding done using the hardware description language VERILOG.
This presentation illustrates the experience gained by me during a RF circuit design course. The course requirements included designing, fabricating and simulating various couplers, an amplifier, a low noise amplifier and an oscillator. Operating frequency was centered around 2.4 GHz.
Low Noise Amplifier at 2 GHz using the transistor NE85639 in ADSKarthik Rathinavel
• Systematically designed a LNA and its biasing using non-ideal components such as Microstrip TLs resistors, capacitors etc.
• Calculated the S parameters of the Transistor and simulated the gain and bandwidth to be 10 dB and 1 GHz respectively.
• Achieved a Noise Figure of 3.2 dB and s11 of -20 dB in the final design.
DESIGN AND NOISE OPTIMIZATION OF RF LOW NOISE AMPLIFIER FOR IEEE STANDARD 802...VLSICS Design
Low noise amplifier is the front end block of radio-frequency receiver system. Its design required various characteristics such as power gain, noise figure, insertion losses and power consumption. In this paper we have proposed a single stage low noise amplifier design with high gain and low noise using inductive source degeneration topology for frequency range of 3 GHz to 7 GHz and also use the active biasing devices. A range of devices like inductors and capacitors are used to achieve 50 Ω input impedance with a low noise factor. The design process is simulated process is using Advance Design System (ADS) and implemented in TSMC 0.18 µm CMOS technology. A single stage low noise amplifier has a measured forward gain 25.4 dB and noise figure 2.2 dB at frequency 5.0 GHz.
IOSR journal of VLSI and Signal Processing (IOSRJVSP) is an open access journal that publishes articles which contribute new results in all areas of VLSI Design & Signal Processing. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & Signal Processing concepts and establishing new collaborations in these areas.
International Journal of Engineering Research and Applications (IJERA) aims to cover the latest outstanding developments in the field of all Engineering Technologies & science.
International Journal of Engineering Research and Applications (IJERA) is a team of researchers not publication services or private publications running the journals for monetary benefits, we are association of scientists and academia who focus only on supporting authors who want to publish their work. The articles published in our journal can be accessed online, all the articles will be archived for real time access.
Our journal system primarily aims to bring out the research talent and the works done by sciaentists, academia, engineers, practitioners, scholars, post graduate students of engineering and science. This journal aims to cover the scientific research in a broader sense and not publishing a niche area of research facilitating researchers from various verticals to publish their papers. It is also aimed to provide a platform for the researchers to publish in a shorter of time, enabling them to continue further All articles published are freely available to scientific researchers in the Government agencies,educators and the general public. We are taking serious efforts to promote our journal across the globe in various ways, we are sure that our journal will act as a scientific platform for all researchers to publish their works online.
International Journal of Engineering Research and Development is an international premier peer reviewed open access engineering and technology journal promoting the discovery, innovation, advancement and dissemination of basic and transitional knowledge in engineering, technology and related disciplines.
We follow "Rigorous Publication" model - means that all articles appear on IJERD after full appraisal, effectiveness, legitimacy and reliability of research content. International Journal of Engineering Research and Development publishes papers online as well as provide hard copy of Journal to authors after publication of paper. It is intended to serve as a forum for researchers, practitioners and developers to exchange ideas and results for the advancement of Engineering & Technology.
Optimization of Packet Length for Two Way Relaying with Energy HarvestingIJCNCJournal
In this article, we suggest optimizing packet length for two way relaying with energy harvesting. In the first transmission phase, two source nodes N1 and N2 are transmitting data to each others through a selected relay R. In the second phase, the selected relay will amplify the sum of the signals received signals from N1 and N2. The selected relay amplifies the received signals using the harvested energy from Radio Frequency (RF) signals transmitted by nodes N1 and N2. Finally, N1 will remove, from the relay’s signal, its own signal to be able to decode the symbol of N2. Similarly, N2 will remove, from the relay’s signal, its own signal to be able to decode the symbol of N1. We derive the outage probability, packet error probability and throughput at N1 and N2. We also optimize packet length to maximize the throughput at N1 or N2.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
A Novel Architecture for Different DSP Applications Using Field Programmable ...journal ijme
This paper presents a reconfigurable processor for different digital signal processing applications. The performance of the proposed architecture has been evaluated by taking different dsp applications like Low pass filter, high pass filter, finite impulse response (FIR) filter and FFT module. We designed the architecture of the processor and realizing the architecture using adder, multiplier, delay unit and validate it in the FPGA, which show that the hardware scheme is feasible for practical application. The experimental results clearly reveal the novelty of the architecture for dsp applications. This paper investigates the potential use of FPGAs for implementing efficient “Reconfigurable Processor” for different dsp applications. The proposed processor is based on parallel re-configurable which is implemented on FPGA. FPGAs have become an important component for implementing these functions with respect to cost, performance and flexibility. The general purpose SPARTAN 3AN FPGA kit has been employed for developing reconfigurable processor, with all the coding done using the hardware description language VERILOG.
This presentation illustrates the experience gained by me during a RF circuit design course. The course requirements included designing, fabricating and simulating various couplers, an amplifier, a low noise amplifier and an oscillator. Operating frequency was centered around 2.4 GHz.
Low Noise Amplifier at 2 GHz using the transistor NE85639 in ADSKarthik Rathinavel
• Systematically designed a LNA and its biasing using non-ideal components such as Microstrip TLs resistors, capacitors etc.
• Calculated the S parameters of the Transistor and simulated the gain and bandwidth to be 10 dB and 1 GHz respectively.
• Achieved a Noise Figure of 3.2 dB and s11 of -20 dB in the final design.
DESIGN AND NOISE OPTIMIZATION OF RF LOW NOISE AMPLIFIER FOR IEEE STANDARD 802...VLSICS Design
Low noise amplifier is the front end block of radio-frequency receiver system. Its design required various characteristics such as power gain, noise figure, insertion losses and power consumption. In this paper we have proposed a single stage low noise amplifier design with high gain and low noise using inductive source degeneration topology for frequency range of 3 GHz to 7 GHz and also use the active biasing devices. A range of devices like inductors and capacitors are used to achieve 50 Ω input impedance with a low noise factor. The design process is simulated process is using Advance Design System (ADS) and implemented in TSMC 0.18 µm CMOS technology. A single stage low noise amplifier has a measured forward gain 25.4 dB and noise figure 2.2 dB at frequency 5.0 GHz.
IOSR journal of VLSI and Signal Processing (IOSRJVSP) is an open access journal that publishes articles which contribute new results in all areas of VLSI Design & Signal Processing. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & Signal Processing concepts and establishing new collaborations in these areas.
International Journal of Engineering Research and Applications (IJERA) aims to cover the latest outstanding developments in the field of all Engineering Technologies & science.
International Journal of Engineering Research and Applications (IJERA) is a team of researchers not publication services or private publications running the journals for monetary benefits, we are association of scientists and academia who focus only on supporting authors who want to publish their work. The articles published in our journal can be accessed online, all the articles will be archived for real time access.
Our journal system primarily aims to bring out the research talent and the works done by sciaentists, academia, engineers, practitioners, scholars, post graduate students of engineering and science. This journal aims to cover the scientific research in a broader sense and not publishing a niche area of research facilitating researchers from various verticals to publish their papers. It is also aimed to provide a platform for the researchers to publish in a shorter of time, enabling them to continue further All articles published are freely available to scientific researchers in the Government agencies,educators and the general public. We are taking serious efforts to promote our journal across the globe in various ways, we are sure that our journal will act as a scientific platform for all researchers to publish their works online.
International Journal of Engineering Research and Development is an international premier peer reviewed open access engineering and technology journal promoting the discovery, innovation, advancement and dissemination of basic and transitional knowledge in engineering, technology and related disciplines.
We follow "Rigorous Publication" model - means that all articles appear on IJERD after full appraisal, effectiveness, legitimacy and reliability of research content. International Journal of Engineering Research and Development publishes papers online as well as provide hard copy of Journal to authors after publication of paper. It is intended to serve as a forum for researchers, practitioners and developers to exchange ideas and results for the advancement of Engineering & Technology.
Optimization of Packet Length for Two Way Relaying with Energy HarvestingIJCNCJournal
In this article, we suggest optimizing packet length for two way relaying with energy harvesting. In the first transmission phase, two source nodes N1 and N2 are transmitting data to each others through a selected relay R. In the second phase, the selected relay will amplify the sum of the signals received signals from N1 and N2. The selected relay amplifies the received signals using the harvested energy from Radio Frequency (RF) signals transmitted by nodes N1 and N2. Finally, N1 will remove, from the relay’s signal, its own signal to be able to decode the symbol of N2. Similarly, N2 will remove, from the relay’s signal, its own signal to be able to decode the symbol of N1. We derive the outage probability, packet error probability and throughput at N1 and N2. We also optimize packet length to maximize the throughput at N1 or N2.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Study Utility Vehicle Makassar City Transport a High- ErgonomicsIJERA Editor
The development of technology during this was to meet the man, but it should be men must be spoilt, But if it
turns out that all that did not make people feel safe, comfortable, healthy and easy, but the planning process,
decision-making and developments have experienced a deviation orientation. Public transport Transportation in
the Makassar city should be made with implementing aspects promotes ergonomic comfort, but it does not apply
in means of transportation to the public. Issues for public vehicles on access up and down not in accordance
with The aim of the research vehicle users. is to phrases dimensions body which have an effect on to utility
vehicle, to examine the public vehicles that high-promotes ergonomic comfort. The method assessment is the
measurement dimensions body to the passengers as well as the use questionnaires and analyzed in a holistic
approach ergonomics. Results of research high security tools to public vehicles that high-security vehicle users
generally by body dimensions as a powerful than Knee-and-a-half was knee, long your feet, and your elbow
kelantai. While utilities yangbernilai ergonomics was the first and second around 24.76 cm and 49.53 cm, wide
around 24.25 cm and was hangar 104, 78 cm.
Effect of Combustion Air Pre-Heating In Carbon Monoxide Emission in Diesel Fi...IJERA Editor
This paper describes the effect of combustion air pre- heating in Diesel fired heat Treatment Furnace. The main
heat treatment processes are Normalizing, Tempering, Hardening, Annealing, Solution Annealing and Stress
Relieving. The emission of carbon monoxide is measured with combustion air pre-heating and without preheating.
The results are then compared and it is found that the emission of CO is reduced by 29.12%. With the
Combustion air pre-heating a considerable reduction in Specific Furnace Fuel Consumption (SFFC) is obtained.
The test was caaried out at Peekay Steels Casting (P) ltd, Nallalam, Calicut.
General Terms: Heat Treatment Furnace
A Combined Approach for Feature Subset Selection and Size Reduction for High ...IJERA Editor
selection of relevant feature from a given set of feature is one of the important issues in the field of
data mining as well as classification. In general the dataset may contain a number of features however it is not
necessary that the whole set features are important for particular analysis of decision making because the
features may share the common information‟s and can also be completely irrelevant to the undergoing
processing. This generally happen because of improper selection of features during the dataset formation or
because of improper information availability about the observed system. However in both cases the data will
contain the features that will just increase the processing burden which may ultimately cause the improper
outcome when used for analysis. Because of these reasons some kind of methods are required to detect and
remove these features hence in this paper we are presenting an efficient approach for not just removing the
unimportant features but also the size of complete dataset size. The proposed algorithm utilizes the information
theory to detect the information gain from each feature and minimum span tree to group the similar features
with that the fuzzy c-means clustering is used to remove the similar entries from the dataset. Finally the
algorithm is tested with SVM classifier using 35 publicly available real-world high-dimensional dataset and the
results shows that the presented algorithm not only reduces the feature set and data lengths but also improves the
performances of the classifier.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
OPTIMIZATION OF CMOS 0.18 M LOW NOISE AMPLIFIER USING NSGA-II FOR UWBVLSICS Design
A design and optimization of 3-5 GHz single ended Radio Frequency (RF) Low Noise Amplifier (LNA) for ultra-wide-band (UWB) applications using standard UMC 0.18 µm CMOS technology is reported. Designing of RF circuit components is a challenging job, since even after performing lengthy calculations and finding parameter values it is less guarantee that the design performs as expected. In view of this the optimization tool; Elitist Non-Dominated Sorting Genetic Algorithm (NSGA-II); has been employed to get the optimized starting values of components in the proposed LNA design. The obtained NSGA-II parameters were simulated using Cadence Spectre- RF simulator. The designed Low Noise Amplifier achieves a power gain of 22 dB and a minimum Noise Figure of 3 dB is achieved. It dissipates 12.5 mW of power out of 1.8 V supply
The Approach on Influence of Biasing Circuit in Wideband Low Noise Amplifier ...IJEACS
This proposed work investigates the effects of biasing
circuit in the ultra-wideband microwave low noise amplifier
which operates between 3GHz to 10GHz. The complete circuit is
visualized the importance of every component in the design with
respect to linear measurements like Gain, Noise Figure, Return
loss under unconditionally stable condition. The design and
realization are made by using Hybrid Microwave integrated
circuit in AWR microwave office. The thing that is absolutely
necessary and frequently the difficult step in the design of an
LNA is 'biasing circuit design'. The difficulty situation arises
because traditional methods LNA by using S-parameters data
files in EDA tools provides almost all linear measurements.
Hence a number of time consuming iterations of different biasing
circuits with optimization methods may be required to reach
targeted specifications with the fixed operating point at the
desired points in the load line. Considering this behavior, various
alternate biasing circuit schemes are prepared and founded the
results associated with it. Furthermore, this paper unmistakably
clarifies the impacts of the biasing circuit by utilizing
intermodulation and harmonics distortion technique for
portrayal characterization. Different cases and sorts of the
biasing circuits with various biasing focuses have been tested and given clear perspective of the biasing ideas.
DESIGN AND ANALYSIS OF 2 GHz 130nm CMOS CASCODE LOW NOISE AMPLIFIER WITH INTE...csijjournal
This work, illustrates the development of 2 GHz Low Noise Amplifier (LNA) interfaced with square truncated edge-fed right circularly polarized patch antenna. The LNA is simulated on Agilent ADS platform with TSMC 130nm RF CMOS process. The development of cascode amplifier and its optimization has been further exemplified. The developed LNA is tuned for 2 GHz and the performance is tuned for high stability factor of 4, Gain of 19 dB which is essential for any mobile device, Noise Figure (NF) of 1.15 dB with a P1dB point at -9 dBm. Further a truncated patch antenna with right circular polarization has been simulated on EMpro. The antenna has a gain of 6.1 dB in the azimuth plane. The simulated system can be further integrated to form the RF front end of TDD2000 LTE standard mobile device.
International Journal of Engineering Research and Development is an international premier peer reviewed open access engineering and technology journal promoting the discovery, innovation, advancement and dissemination of basic and transitional knowledge in engineering, technology and related disciplines.
We follow "Rigorous Publication" model - means that all articles appear on IJERD after full appraisal, effectiveness, legitimacy and reliability of research content. International Journal of Engineering Research and Development publishes papers online as well as provide hard copy of Journal to authors after publication of paper. It is intended to serve as a forum for researchers, practitioners and developers to exchange ideas and results for the advancement of Engineering & Technology.
PARASITIC-AWARE FULL PHYSICAL CHIP DESIGN OF LNA RFIC AT 2.45GHZ USING IBM 13...Ilango Jeyasubramanian
• Analyzed and designed a single stage cascoded LNA with Q-based calculation for desired input matching, output matching, power gain, IIP3 and Noise figure, including all the parasitics in the on-chip and off-chip components using SpectreRF simulations.
• Synthesized the LNA layout for on-chip components with spiral inductor, MOS capacitor, MIM capacitor and Bond-pads with ESD protections.
• Our LNA exhibited a noise figure of 1.23dB, linear gain of 18.54 dB, IIP3 of -4.60dbm, S11 of -31.11db, S22 of -24.91db with the operating range between 2.4-2.5GHZ along with 10% variation tolerance.
Design and Simulation of Low Noise Amplifiers at 180nm and 90nm TechnologiesIJERA Editor
With continued process scaling, CMOS has become a viable technology for the design of high-performance low noise amplifiers (LNAs) in the radio frequency (RF) regime. This thesis presents design and simulation of LNA at 180nm and 90nm technology. The LNA function is used to amplify signals without adding noise. The work is done on Cadence Virtuoso platform and the performance parameters like transient response and Noise figure are simulated and plotted. A supply voltage of just 5mV is used here. The noise figure at 180nm is found to be 259.722mdB at 1.04502GHz and The noise figure at 90nm is found to be 183.21mdB at 1.157GHz. 1.04502GHz and 1.157GHz are the peak frequency obtained from the frequency response of the Low noise amplifier. It is observed that the noise figure varies in each technology.
First order sigma delta modulator with low-power consumption implemented in a...eSAT Journals
Abstract
This paper presents a design of a switched-capacitor discrete time 1st order Delta-Sigma modulator used for a resolution of 8 bits
Sigma-Delta analog to digital converter. For lower power consumption, the use of operational transconductance amplifier is
necessary in order to provide wide output voltage swing and moderate DC gain. Simulation results showed that with 0.35um CMOS
technology, 80 KHz signal bandwidth and oversampling rate of 64, the modulator achieved 49.25 dB Signal to Noise Ratio (SNR) and
the power consumption was 5.5 mW under ±1.5V supply voltage .
Index terms: Analog-to-Digital conversion, Delta-Sigma modulation, CMOS technology, Transconductance operational
amplifier.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Negative image amplifier technique for performance enhancement of ultra wideb...IJECEIAES
The paper aims at designing of two stage cascaded ultra-wideband (UWB) low noise amplifier (LNA) by using negative image amplifier technique. The objective of this article is to show the performance improvement using negative image amplifier technique and realization of negative valued lumped elements into microstrip line geometry. The innovative technique to realize the negative lumped elements are carried out by using Richard’s Transformation and transmission line calculation. The AWR microwave office tool is used to obtain characteristics of UWB LNA design with hybrid microwave integrated circuit (HMIC) technology. The 2-stage cascaded LNA design using negative image amplifier technique achieves average gain of 23dB gain and low noise figure of less than 2dB with return loss less than -8dB for UWB 3-10GHz. The Proper bias circuit is extracted using DC characteristics of transistor at biasing point 2V, 20mA and discussed in detail with LNA layout. The negative image matching technique is applied for both input and output matching network. This work will be useful for all low power UWB wireless receiver applications.
IOSR Journal of Electronics and Communication Engineering(IOSR-JECE) is an open access international journal that provides rapid publication (within a month) of articles in all areas of electronics and communication engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in electronics and communication engineering. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
1. D. Senthilkumar, Dr.Uday Pandit khot, Prof. Santosh Jagtap / International Journal of
Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 1, January -February 2013, pp.403-408
Design and Comparison of Different Matching Techniques for
Low Noise Amplifier Circuit
D. Senthilkumar1, Dr.Uday Pandit khot2, Prof. Santosh Jagtap3
1. ME Student, Dept of EXTC, Vidyalankar College of Engineering & Technology, wadala (MS) INDIA
2. Asso.Prof of St. Francis Institute of Technology, Borivali (MS) INDIA.
3. Asst.prof of Vidyalankar College of Engineering & Technology, wadala (MS) INDIA
Abstract
This paper describes the design of Low intrinsic gate- drain capacitor is dealt in [2]. By
Noise Amplifier (LNA) circuits with different means of a fine tuning of the transistors output RC
types of matching circuits at the input side and loading impedance and source inductance, a
output side at 6 GHz. This paper compares the transistor‟s input reflection coefficient and noise
results of all possible combinations of ‘T’ and ‘L’ temperature can be greatly improved over broad
type matching circuits. The designed circuit is bandwidth.
simulated with Advanced Design System (ADS)
software. Each circuit is simulated for, with and In paper [3] presents an analysis and design
without stabilizing circuit and feedback circuit. of wide band Low Noise Amplifier (LNA) based on
RLC series circuit is applied as feedback circuit cascade configuration with resistive feedback.
and to improve the stability of the LNA circuit. Wideband input matching was achieved using a
Of all LNA matching circuits the T- L matching shunt –shunt feedback resistor in conjunction with a
gives better results in the stabile region than L-L proceeding π-match network.
matching, L-T matching and T-T matching.
Under stability condition forward gain and noise A symbolic approach and an optimization
figure of T-L match is 14.14 dB and 1.81 dB algorithm for the optimal design of Low Noise
which is better than L-L match as 10.39 dB and Amplifiers (LNAs) through S-parameters have been
2.15 dB , L-T match as 5.237 dB and 2.47 dB and discussed in [4]. This paper gives the idea of
T-T match as 6.468 dB and 3.9 dB. computing automatically the symbolic expression of
S-parameters using coates diagraph technique.
Keywords- Advance Design System (ADS), Low
Noise Amplifier (LNA), Noise Figure (NF), T- A novel method of designing low power
matching network, L-matching network. wide band Low Noise Amplifier (LNA) using a sub
threshold technique is discussed in paper [5]. The
I. INTRODUCTION Low Noise Amplifier (LNA) is built with common-
Designing amplifiers for a minimum noise gate (CG) input stage for wideband input matching
figure then becomes simply a matter of setting the and a common source (CS)- common gate (CG)
optimum condition for a particular transistor. Based cascade stage for gain boosting and the power
on S-parameters of the transistor and certain reduction is achieved by driving the front end
performance requirements, a systematic procedure is common gate(CG ) transistor in sub-threshold (low
developed for the design of the LNA. In LNA current) region and here the input matching is done
design, the most important factors are low noise, by LC circuit.
moderate gain, matching and stability. In the
designed LNA of this paper, different types of In [6] the effect of gate inductance on noise
matching sections have been designed and simulated figure of designed Low Noise Amplifier (LNA) is
using Advanced Design Software (ADS). dealt. In this paper [6] the effect of L g is
considerably less to noise figure of Low Noise
II. LITERATURE SURVEY Amplifier (LNA) designed based on the noise
Recently, Low Noise Amplifiers (LNAs) optimization technique.
were designed and simulated by many researchers
[1]-[8].In [1] a novel method is used for isolation of In [7] the noise figure in low noise radio
DC circuits from AC signals. Radial stubs are used frequency cascade amplifiers using narrow band
for this isolation. Since radial stubs have low input impedance matching is analyzed. The
impedance at low frequencies and it generates high matching network is as inherently belonging to the
impedance at higher frequency. low noise amplifier. A parallel-series matching
network has been proposed in [7] which allows
Design of wide band Low Noise Amplifier dominant noise contributions to be reduced and very
(LNA) with a novel feedback mechanism using low noise figure is to be achieved.
403 | P a g e
2. D. Senthilkumar, Dr.Uday Pandit khot, Prof. Santosh Jagtap / International Journal of
Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 1, January -February 2013, pp.403-408
In [8] a new technique has been employed for
improving the stability of the Low Noise Amplifier
(LNA). A RLC series circuit has been employed to
make the LNA stable. Also a RLC feedback circuit
is used between the gate terminal and drain terminal
operating the LNA in the stable region.
III.EQUIVALENT CIRCUIT OF
MICROWAVE MESFET
Most microwave amplifiers today use Fig. 2 Basic DC biasing network [12]
Gallium Arsenide (GaAs) Field-Effect Transistor
(FETs). They can presently be used at frequencies A. Single Stage Amplifier
up to 100 GHz in a wide variety of applications A single stage microwave transistor
requiring low noise figure, broad band width and amplifier can be modeled by the circuit in Fig. 3,
medium power capacity [9] [10]. Knowledge of the where a matching network is used both sides of the
equivalent circuit of a MESFET is very useful for transistor to transform the input and output
the device performance analysis (gain, noise, etc…) impedance Z0 to the source and load impedance Zs
in designing of microwave circuits. In this paper low and ZL. The most useful gain definition for
noise GaAs MESFET NE 76000 has been used for amplifier design is the transducer power gain, which
the design of LNA. The NE 76000 provides a low accounts both source and load mismatch. Thus from
noise figure and high associated gain though K- [13], can be define separate effective gain factors for
Band. Fig.1 show the equivalent circuit of this the input (Source) matching network, the transistor
transistor which has been recovered by NEC itself and the output (load) matching network as
Company for frequency range of 1 GHz to 26 GHz follow:
[11].
1 − Γ𝑠 2
𝐺𝑆 = (1)
1 − Γ 𝐼𝑁 Γ 𝑠 2
2
𝐺0 = 𝑆21 (2)
1− Γ𝐿 2
𝐺𝐿 = (3)
1 − S22 Γ 𝐿 2
Fig. 1 Linear Model of NE 76000 Transistors [15] Then the overall transducer gain is GT=GsG0GL. The
effective gains from GS and GL are due to the
IV. DC BIASING impedance matching of the transistor to the
In order to design a low noise device, the impedance Z0.
transistor must be DC biased at an appropriate
operating point. These depends of the application
(low noise, high gain, high power), and the type of
the transistor (FET, HEMT, etc) [12]. Accounts both
source and load mismatch. Thus from [13], can be
define separate effective gain factors for the input
(Source) matching network, the transistor itself and
the output (load) matching network as follow . Fig 2
shows model of a DC biasing circuit.
Vd (drain voltage) = 3V and Ids (drain-Source
current) = 10 mA. The biasing point is obtained by Fig.3 The General Transistor Amplifier Circuit [12]
using a Vg (Gate Voltage) range from -0.6 V to -0.3
V and it gives -0.4V as DC operating point by using B. Stability Consideration
the circuit shown in Fig 2. The stability of an amplifier, or its
resistance to oscillate, is a very important
consideration in a design and can be determined
from the S parameters, the matching networks, and
the terminations. In the circuit Fig. 3, oscillations are
possible when either the input or output port presents
404 | P a g e
3. D. Senthilkumar, Dr.Uday Pandit khot, Prof. Santosh Jagtap / International Journal of
Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 1, January -February 2013, pp.403-408
a negative resistance. This occurs when in In Fig.7 the „L‟ type matching is used at the input as
Γ 𝐼𝑁 > 1 or Γ 𝑂𝑈𝑇 > 1. These because of in and out well as on the output side. RLC series circuit is
depend on the source and load matching networks. designed and used to improve the stability of the
While, the stability of the amplifier depends on S circuit. For feed back again a RLC series resonance
and L as presented by the matching networks. type is used.
Alternatively, it can be shown that the amplifier will
be unconditionally stable if the following necessary
and sufficient conditions are met [14]:
1− 𝑆11 2 − 𝑆11 2 + ∆ 2
𝐾= >1
2 𝑆12 𝑆21 (4)
(5)
and ∆ >1
Fig. 6 „L‟ Type Input Matching and „L‟ Type Output
Matching LNA Circuit
m3
m4 freq=6.000GHz
freq=6.000GHz
StabFact1=1.140 dB(S(2,1))=10.392
20 m3
2.0
0
1.5
m4 -20
1.0
dB(S(2,1))
-40
0.5
StabFact1
0.0 -60
-0.5 -80
Fig. 4 A lossless network matching networks -1.0
-1.5
-100
arbitrary load impedance to a transmission line [12] -2.0
1 2 3 4 5 6 7 8 9 10
-120
1 2 3 4 5 6 7 8 9 10
freq, GHz
freq, GHz
In this paper an RLC series circuit is used
as stability circuit for LNA circuit in bringing it to m2
freq= 6.000GHz m5
dB(S(1,2))=-27.324 freq= 6.000GHz
the stable region.fig.5 shows a sample of RLC series 0
m2
80
NFmin=2.151
60
stability circuit. -50
dB(S(1,2))
NFmin
40
-100
-150 20
m5
-200 0
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10
freq, GHz freq, GHz
m1
m8 freq= 6.000GHz
freq= 6.000GHz
dB(S(2,2))=-16.067 dB(S(1,1))=-1.819
5
0
0
m1
Fig.5 Stabilizing Circuit for LNA.
dB(S(1,1))
-5
-5
-10
dB(S(2,2))
-10
-15 m8
-15
V. MATCHING NETWORK -20 1 2 3 4 5 6 7 8 9 10
freq, GHz
-25
1 2 3 4 5 6 7 8 9 10
The basic idea of the impedance matching freq, GHz
is illustrated in Fig. 4, which shows an impedance
matching network placed between load impedance Fig.7 S11, S22, S12, S21, NFmin Vs freq for L-L
and transmission line. The need for matching Matching
network arises because amplifiers, in order to deliver
maximum power to a load, or to perform in a certain After the simulation of the circuit shown in
desired way, must be properly terminated at both the Fig 6, the results are shown in Fig 7. The stability
input and output ports. The matching network is and forward gain are as 1.14 and 10.392 dB. The
ideally lossless to avoid unnecessary loss of power output reflection coefficient is -16.067 dB and
and is usually designed so that looking into the reverse transmission coefficient is -27.324 dB, input
matching network is Z0. Several types of matching reflection coefficient is -1.819 dB and the stability of
network are available, however factors likes the transistor amplifier is as 1.14 which satisfies the
complexity, bandwidth, implementation and equation (4).Thus the stability is maintained at more
adjustability need to be considered in the matching than one as per equation (4) with noise figure
network selection. In this paper different matching touches slightly more than two decibel point and the
circuits is discussed such as „L‟ forward gain reduced to 10.394 dB.
Matching, and „T‟ matching circuits and its all
possible combinations. Case: II ‘L’ Type Input Matching and ‘T’ Type
Output Matching LNA Circuit
Case: I ‘L’ Type Input Matching and ‘L’ Type In Fig 8 the „L‟ type matching is used at the input
Output Matching LNA Circuit and on the output side the „T‟ type matching is used.
405 | P a g e
4. D. Senthilkumar, Dr.Uday Pandit khot, Prof. Santosh Jagtap / International Journal of
Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 1, January -February 2013, pp.403-408
RLC series circuit is designed and used to improve
the stability of the circuit. For feed back again a
RLC series resonance type is used.
Fig. 10 „T‟ Type Input Matching and „L‟ Type
Output Matching LNA
Circuit
Fig. 8 „L‟ Type Input Matching and „T‟ Type Output
Matching LNA Circuit m1
f req=6.000GHz
m2 dB(S(1,1))=-17.214
f req=6.000GHz 0
dB(S(1,2))=-23.575
0
m2 -5
m4
m3 freq= 6.000GHz m2
freq= 6.000GHz freq= 6.000GHz
dB(S(1,1))
StabFact1=1.133 -50
dB(S(2,2))=-1.236 dB(S(2,1))=5.237
-10
dB(S(1,2))
0
2.0 -100
m3 20
-1
m2
-15
1.5
0
-150 m1
-2
dB(S(2,2))
m4 -20
StabFac t1
-20
dB(S(2,1))
-3
1.0 -40 -200 1 2 3 4 5 6 7 8 9 10
-4 -60 1 2 3 4 5 6 7 8 9 10
freq, GHz
-5
0.5 -80 freq, GHz m3
f req=6.000GHz
-6
-100
m8 dB(S(2,1))=14.140
0.0
1 2 3 4 5 6 7 8 9 10
1 2 3 4 5 6 7 8 9 10 -120 f req=6.000GHz
freq, GHz
freq, GHz
1 2 3 4 5 6 7 8 9 10 dB(S(2,2))=-6.291
freq, GHz
0 20 m3
0
-2
-20
-40
dB(S(2,1))
-4
dB(S(2,2))
-60
-80
-6 m8
-100
-8 -120
m7
freq= 6.000GHz
m5 dB(S(1,2))=-32.479 m1 -140
freq= 6.000GHz freq= 6.000GHz
dB(S(1,1))=-3.814 NFmin=2.478 -10 1 2 3 4 5 6 7 8 9 10
-20 m7 5.0
0
4.5
1 2 3 4 5 6 7 8 9 10 freq, GHz
-40
4.0
-1 -60 3.5
freq, GHz
-80 3.0 m1
NFmin
dB(S(1,2))
dB(S(1,1))
-2 2.5
-100
2.0
-120 1.5
-3
1.0
m5 -140
0.5
-4
-160 0.0
1 2 3 4 5 6 7 8 9 10
-180
-5
1 2 3 4 5 6 7 8 9 10 freq, GHz
1 2 3 4 5 6 7 8 9 10
freq, GHz
freq, GHz
m4
freq=6.000GHz
StabFact1=1.304
m4
Fig.9 S11, S22, S12, S21, NFmin Vs freq for L-T freq=6.000GHz
NFmin=1.816
2.5
Matching 80
2.0
60
StabFact1
1.5 m4
After the simulation of the circuit shown in
NFmin
40 1.0
Fig 8, the results are shown Fig 9. The stability, 20 0.5
output reflection coefficient and forward gain are m4 0.0
shown in Fig 4.50 as 1.133, -1.236 dB and 5.237 dB. 0
1 2 3 4 5 6 7 8 9 10
1 2 3 4 5
freq, GHz
6 7 8 9 10
freq, GHz
The input reflection coefficient is -3.814 dB, reverse
transmission coefficient is -32.479 dB and minimum Fig.11 S11, S22, S12, S21, NFmin Vs freq for T-L
noise figure is 2.478 dB. The stability of the matching
transistor amplifier is as 1.133 which satisfies the
equation (4).Thus the stability is maintained at more After the simulation of the circuit shown in
than one as per equation (4) with noise figure Fig 10, the results are shown in Fig 11.The forward
touches almost two and half decibel point while the gain is 14.14 dB, the output reflection coefficient is -
forward gain drastically reduced to 5.237 dB. 6.291 dB and reverse transmission coefficient is -
23.575 dB and also the input reflection coefficient is
Case: III ‘T’ Type Input Matching and ‘L’ Type -17.214 dB. The stability and minimum noise are as
Output Matching LNA Circuit 1.304 and 1.816 dB. Thus the stability is maintained
In Fig 8 the „T‟ type matching is used at the at more than one as per equation (4) with almost
input and on the output side the „L‟ type matching is double increasement in noise figure.
used. RLC series circuit is designed and used to
improve the stability of the circuit. For feed back Case: IV ‘T’ Type Input Matching and ‘T’ Type
again a RLC series resonance type is used. Output Matching LNA Circuit
In Fig 7 the „T‟ type matching is used at the
input as well as on the output side. RLC series Readout
Readout
Re
circuit is designed and used to improve the stability
Readout
Readout
406 | P a g e
5. D. Senthilkumar, Dr.Uday Pandit khot, Prof. Santosh Jagtap / International Journal of
Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 1, January -February 2013, pp.403-408
of the circuit. For feed back again a RLC series Table .I Comparative Results of LNA Circuit (with
resonance type is used. and without Stabilizing circuit) using different
matching techniques.
Fig 12 „T‟ Type Input Matching and „T‟ Type
Output Matching LNA Circuit
m1
freq= 6.000GHz
m5 NFmin=3.974
freq= 6.000GHz m7
dB(S(1,1))=-1.011 freq= 6.000GHz
dB(S(1,2))=-29.379
-20 m7 5.0
0.0
4.5 m1
-40
4.0
-0.5
-60 3.5
m5
-1.0 3.0
NFmin
dB(S(1,2))
-80
dB(S(1,1))
2.5
-1.5 2.0
-100
1.5
-2.0 -120 1.0
0.5
-2.5 -140
0.0
1 2 3 4 5 6 7 8 9 10
-160
-3.0 1 2 3 4 5 6 7 8 9 10 freq, GHz
1 2 3 4 5 6 7 8 9 10
freq, GHz
freq, GHz
m3
freq= 6.000GHz m4
dB(S(2,2))=-11.806 freq= 6.000GHz
StabFact1=1.254 m2
freq= 6.000GHz
2
dB(S(2,1))=6.468
2.0
VII. CONCLUSIONS
20 m2
0
0
-2
1.5
m4
dB(S(2,2))
-20
-4
StabFact1
dB(S(2,1))
-6
-8
1.0 -40
-60 The simulation results of all possible
combinations of „L‟ and „T‟ type matching circuits
0.5 -80
-10
m3
-100
-12
0.0
1 2 3 4 5 6 7 8 9 10 -120
1 2 3 4 5 6 7 8 9 10
freq, GHz 1 2 3 4 5 6 7 8 9 10
freq, GHz
freq, GHz
are shown in Table I for with(W) and without(WO)
stabilizing circuit(SC). From Table I the „T‟ type
Fig.13 S11, S22, S12, S21, NFmin Vs freq for L-L input matching with „L‟ type output matching gives
matching better results without much degradation in terms of
forward gain, noise figure, stability point of view. It
After the simulation of the circuit shown in Fig 12, gives gain as 16.3 dB, noise figure 1.8 dB while
the results are shown in Fig 13. The stability, output improving stability from 0.41 to 1.3. Other
reflection coefficient and forward gain are as 1.254, parameters like output reflection coefficient (S22) is -
-11.808 dB, and 6.468 dB. The input reflection 6.3 dB, input reflection coefficient (S11) is -17.2 dB
coefficient is -1.011 dB, reverse transmission and reverse transmission coefficient (S12) is -23.5 dB
coefficient is -29.379 dB and minimum noise figure also comparatively better than other matching
is 3.974 dB. The stability of the transistor amplifier sections. Whenever there is an improvement in
is as 1.254 which satisfies the equation (4).Thus the stability other matching circuits exhibits much
stability is maintained at more than one as per degradation in gain and more than double
equation (4) with noise figure touches almost four increments in noise figure from the results of LNA
decibel point while the forward gain drastically without stabilizing circuit.
reduced to 6.468 dB.
REFERENCES
VI. SIMULATION RESULTS [1] Mohd. Zinol Abidin Abd Aziz (2004),
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Readout
[2] Robert Hu, “Wideband Matched LNA
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407 | P a g e
6. D. Senthilkumar, Dr.Uday Pandit khot, Prof. Santosh Jagtap / International Journal of
Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 1, January -February 2013, pp.403-408
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[11] Exclusive North America Agent for NEC
RF, Microwave & optoelectronic semi
conductors CEL California Eastern
Laboratories- Headquarters-4590 patrick
henry drive, santa clora, CA 95054-1817-
www.CEL.com
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