The document discusses the design of low-power, high-resolution delta-sigma analog-to-digital converters (ADCs) using switched-capacitor circuits in CMOS technology. It aims to demonstrate that calibration-free ADCs with resolutions over 16 bits can be achieved in a standard 0.18-micron CMOS process using low-current design techniques. The document outlines delta-sigma modulator architectures, describes sources of non-idealities in switched-capacitor circuits, and presents the design of a demonstrator ADC to verify the hypotheses.

1. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 1/72
Low-Power High-Resolution CMOS
Switched-Capacitor Delta-Sigma
Analog-to-Digital Converters
for Sensor Applications
Stepan Sutula1
Directors: Dr. Michele Dei1, Dr. Carles Ferrer Ramis1,2, Dr. Francesc Serra Graells1,2
1Integrated Circuits and Systems (ICAS)
Institut de Microelectrònica de Barcelona, IMB-CNM(CSIC)
2Dept. of Microelectronics and Electronic Systems (DEMISE)
Universitat Autònoma de Barcelona (UAB)
November 5, 2015
Stepan Sutula

2. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 1/72
1 Introduction
2 ΔΣ-Modulator Architectures
3 Low-Power CMOS Switched-Capacitor Circuits
4 Practical ΔΣM Design in a 0.18-µm CMOS Technology
5 Experimental Results
6 Conclusions
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3. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 1/72
1 Introduction
2 ΔΣ-Modulator Architectures
3 Low-Power CMOS Switched-Capacitor Circuits
4 Practical ΔΣM Design in a 0.18-µm CMOS Technology
5 Experimental Results
6 Conclusions
Stepan Sutula

4. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 2/72
General ADC System
Interface between physical and digital worlds
Integration with the input sensor using low-cost CMOS technologies
Maximum precision required for target application
Low power consumption compatible with local energy storage, remote
power or energy harvesting
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5. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 3/72
Quantization
Number of bits:
N = log2(M)
Quantization step:
∆ =
Vmax − Vmin
2N − 1
Quantization noise PSD:
Sε(f ) =
1
fs

 1
∆
∆/2
−∆/2
2
q d q


=
∆2
12fs
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6. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 4/72
ADC State of the Art
20 30 40 50 60 70 80 90 100 110 120
100
101
102
103
104
105
106
107
FOMS = SNDR + 10 log BW
P
160 dB
170 dB
180 dB
SNDR = 10 log Ps
Pε
[dB]
P/fsnyq[pJ]
Flash
Folding
Pipeline
SAR
CT ΔΣ
SC ΔΣ
Schreier FOM
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7. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 4/72
ADC State of the Art
20 30 40 50 60 70 80 90 100 110 120
100
101
102
103
104
105
106
107
FOMS = SNDR + 10 log BW
P
160 dB
170 dB
180 dB
SNDR = 10 log Ps
Pε
[dB]
P/fsnyq[pJ]
Flash
Folding
Pipeline
SAR
CT ΔΣ
SC ΔΣ
Schreier FOM
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8. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 5/72
ADC State of the Art
Architecture Resolution Bandwidth Latency Area
Flash Low High Low High
Folding Medium Medium-high Low High
Pipeline Medium-high Medium-high High Medium
SAR Medium-high Low-medium Low Low
ΔΣ High Low High Medium
Lower bandwidth and higher latency allowed
ΔΣ-architecture simplicity and higher resolution preferred
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9. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 5/72
ADC State of the Art
Architecture Resolution Bandwidth Latency Area
Flash Low High Low High
Folding Medium Medium-high Low High
Pipeline Medium-high Medium-high High Medium
SAR Medium-high Low-medium Low Low
ΔΣ High Low High Medium
Lower bandwidth and higher latency allowed
ΔΣ-architecture simplicity and higher resolution preferred
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10. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 6/72
Objectives and Scope
Working hypotheses:
• Low-cost calibration-free high-resolution ADCs can be obtained in
standard CMOS technologies
• Low-current circuits are preferred over low-voltage design
techniques for higher power savings
• Competitive mixed-signal IC design frameworks can be conducted
using open-source tools
Low-power high-resolution ΔΣ-ADC demonstrator to verify the
hypotheses
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11. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 6/72
1 Introduction
2 ΔΣ-Modulator Architectures
3 Low-Power CMOS Switched-Capacitor Circuits
4 Practical ΔΣM Design in a 0.18-µm CMOS Technology
5 Experimental Results
6 Conclusions
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12. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 7/72
General ΔΣ-ADC Architecture
Oversampling ratio:
OSR =
fs
fN
=
fs
2 · BW
Quantization-noise in-band power:
Pε =
BW
−BW
Sε(f ) df =
∆2
12 · OSR
Antialiasing filtering relaxed
Overclocking needed
ΔΣ-modulator noise shaping
Reduced impact of the block
imperfections on the ADC
performance
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13. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 8/72
First-Order ΔΣ Modulator
One-sample-delay integrator:
H1(z) =
z−1
1 − z−1
Non-linear system due to the
quantization effects
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14. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 8/72
First-Order ΔΣ Modulator
Equivalent linear-model simplification
Signal and noise transfer functions:
STF(z) =
Vout(z)
Vin(z)
=
1
1 + (aqH1(z))−1
NTF(z) =
Vout(z)
Vqn(z)
=
1
1 + aqH1(z)
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15. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 9/72
Lth
-Order ΔΣ Modulator
Resolution-vs-OSR (L + 0.5)-bit/octave increase
Integrator overload prevention
Weakened loop stability
Careful robustness verification needed
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16. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 10/72
First-Order Feedforward ΔΣ-Modulator
Quantization-error processing
only
Integrator-output
signal-headroom relaxation
Signal and noise transfer functions:
STF(z) =
Vout(z)
Vin(z)
= 1
NTF(z) =
Vout(z)
Vqn(z)
=
1
1 + aqH1(z)
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17. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 11/72
Lth
-Order Feedforward ΔΣ Modulator
Single negative-feedback path
Power efficiency
Extra adder circuit
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18. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 12/72
Multi-Bit Quantization
Resolution increase
OSR reduction
Quantizer non-linearity
Calibration/DEM
needed
Feedforward-ΔΣM-
implementation issues
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19. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 13/72
Single-Bit Quantization
Inherent linearity
Quantizer-design
simplification
Benefits for the
feedforward-ΔΣM
implementation:
• Reduced
quantization time
• Passive adder
Oversampling
First-stage
instantaneous error
amplitude
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20. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 14/72
High-Level Modeling
CPU-simulation-time
reduction
Solution to the
mathematical-analysis
difficulties
Number of samples to
simulate:
nsamp = np · OSR
2 · BW
fin
Signal-to-quantization-
noise ratio:
SQNR = 10 log
Ps
Pε
103 104 105 106
−200
−150
−100
−50
0
40 dB/dec
Frequency [Hz]
Powerspectraldensity[dBFS/bin]
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21. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 14/72
High-Level Modeling
CPU-simulation-time
reduction
Solution to the
mathematical-analysis
difficulties
Number of samples to
simulate:
nsamp = np · OSR
2 · BW
fin
Signal-to-quantization-
noise ratio:
SQNR = 10 log
Ps
Pε
103 104 105 106
−200
−150
−100
−50
0
40 dB/dec
Frequency [Hz]
Powerspectraldensity[dBFS/bin]
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22. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 15/72
High-Level Modeling
Input-amplitude
sweep
Input-full-scale
adjustment
Model covering
signal-quantization
error and overloading
only
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23. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 16/72
Circuit Non-Idealities
Sampling thermal noise:
Pn =
2kBT
Cs1 · OSR
Component technology
mismatch
Integrator settling error
Jitter noise:
Pj =
V 2
s
8
(2π · BW · σj)2
OSR
Reference noise
103 104 105 106
−200
−150
−100
−50
0
40 dB/dec
Frequency [Hz]
Powerspectraldensity[dBFS/bin]
No thermal noise
With thermal noise
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24. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 17/72
Demonstrator Target Specifications
50-kHz bandwidth
16-bit resolution
Standard CMOS technology
No supply bootstrapping
No analog calibration
No digital compensation
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25. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 17/72
1 Introduction
2 ΔΣ-Modulator Architectures
3 Low-Power CMOS Switched-Capacitor Circuits
4 Practical ΔΣM Design in a 0.18-µm CMOS Technology
5 Experimental Results
6 Conclusions
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26. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 18/72
Low-Power Switched-Capacitor Design
Low-Voltage Approach
Bulk-driven OpAmps
Internal supply multipliers
Inverter-based OpAmps
Switched OpAmps
Nominal-voltage downscaling,
one-cell-battery compatibility
Moderate power savings
Low-Current Approach
Telescopic diff. pairs with
LCMFB
Dynamic biasing by RC bias
tees
Hybrid-Class-A/AB
Adaptive biasing
Higher power savings
Process and temperature
sensitivity
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27. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 18/72
Low-Power Switched-Capacitor Design
Low-Voltage Approach
Bulk-driven OpAmps
Internal supply multipliers
Inverter-based OpAmps
Switched OpAmps
Nominal-voltage downscaling,
one-cell-battery compatibility
Moderate power savings
Low-Current Approach
Telescopic diff. pairs with
LCMFB
Dynamic biasing by RC bias
tees
Hybrid-Class-A/AB
Adaptive biasing
Higher power savings
Process and temperature
sensitivity
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28. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 19/72
Variable-Mirror Amplifier Family
Two complementary diff. pairs
Dynamic current mirrors
Separate Class-AB control
Partial positive feedback
CMFB control through the
NMOS-pair tail
Gain improvement by the
output cascode transistors
No need for the Miller
compensation capacitors
High-peak Class-AB currents
only in the output transistors
[1] S. Sutula, M. Dei, L. Terés, and F. Serra-Graells, “Class-AB Single-Stage
OpAmp for Low-Power Switched-Capacitor Circuits,”ISCAS 2015 Awarded.
Stepan Sutula

29. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 20/72
Variable-Mirror Amplifier Family
In strong inversion:
Ionp =
B
A + B
Anβ
2
Vcp + Iinp
2
In weak inversion:
Ionp =
B
A + B
e
Vcp
UT Iinp
Desired Class-AB behavior:



Ioutp ≡ 0 Vcp ≡ Vxp Ionp ≡ Iinp
Ioutp ≡ 0 Vcp ≡ Vxp
Ionp Iinp
Ionp Iinp
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30. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 21/72
Type I
Positive-feedback cross-coupled B-B pair for the Class-AB operation
Negative-feedback crossing transistor C as a Class-AB limiter
D
.
=
A · B
A + B
E
.
=
A · B · C
A + B + C
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31. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 21/72
Type I
Positive-feedback cross-coupled B-B pair for the Class-AB operation
Negative-feedback crossing transistor C as a Class-AB limiter
D
.
=
A · B
A + B
E
.
=
A · B · C
A + B + C
Imax 1 +
D
C
Itail
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32. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 22/72
Type-I Analysis: Insensitivity to n and β
In strong inversion:



Iinp =B 2
Ionn
D
−
Ionp
D
+
Iinp
A
Ionp
D
−
Iinp
A
+ C 2
Itail
E
−
Ionp
D
−
Ionn
D
+
Iinp
A
+
Iinn
A
Ionp
D
−
Ionn
D
−
Iinp
A
+
Iinn
A
Iinn =B 2
Ionp
D
−
Ionn
D
+
Iinn
A
Ionn
D
−
Iinn
A
+ C 2
Itail
E
−
Ionn
D
−
Ionp
D
+
Iinn
A
+
Iinp
A
Ionn
D
−
Ionp
D
−
Iinn
A
+
Iinp
A
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33. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 23/72
Type-I Analysis: Insensitivity to UT
In weak inversion:



Iinp =
B
D
Ionn 1 −
D
A
Iinp
Ionp
+
C · D
A · E
Itail
Iinp
Ionp
−
Iinn
Ionn
Iinn =
B
D
Ionp 1 −
D
A
Iinn
Ionn
+
C · D
A · E
Itail
Iinn
Ionn
−
Iinp
Ionp
Independence from technology and temperature
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34. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 24/72
Type I with Class-AB Smoother
Low-level
common-mode
current injection
Instability prevention
under a high
Class-AB modulation
Need for extra current
sources
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35. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 25/72
Type II
Auto-biased Class-AB limiter
Self-latch prevention
Simple sizing procedure
F
.
=
A(B+C)
A+B+C
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36. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 25/72
Type II
Auto-biased Class-AB limiter
Self-latch prevention
Simple sizing procedure
F
.
=
A(B+C)
A+B+C
Imax
1+ A
C
1+ A
B+C
Itail > Itail
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37. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 26/72
Type-II Analysis: Insensitivity to n and β
In strong inversion:



Iinp = 2 B
Ionn
F
+ C
Ionp
F
− (B + C)
Ionp
F
−
Iinp
A
Ionp
F
−
Iinp
A
Iinn = 2 B
Ionp
F
+ C
Ionn
F
− (B + C)
Ionn
F
−
Iinn
A
Ionn
F
−
Iinn
A
Independence from technology and temperature
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38. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 27/72
Type-II Analysis: Insensitivity to UT
In weak inversion:



Iinp =
B
F
Ionn +
C
F
Ionp 1 −
F
A
Iinp
Ionp
Iinn =
B
F
Ionp +
C
F
Ionn 1 −
F
A
Iinn
Ionn
Independence from technology and temperature
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39. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 28/72
Type-II DC Transfer Curve
Parameterized
B/C for A=8
Matching between
analytical and
simulated results
Strong inversion
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40. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 28/72
Type-II DC Transfer Curve
Parameterized
B/C for A=8
Matching between
analytical and
simulated results
Weak inversion
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41. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 29/72
Cascode Biasing
Series/parallel
association
Saturation-edge
biasing
Valid for all MOSFET
inversion levels
Optimum output full
scale for a given
supply voltage
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42. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 30/72
SC-Integrators
Traditional OpAmp use
OpAmp in interleaving
Switched OpAmp
• critical switches
• 50-% duty cycle
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43. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 31/72
SOA-Integrator Operation
Sampling
phase
Integration
phase
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44. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 32/72
Charge-Injection Minimization
Delayed disconnection in the
signal-dependent paths
Signal-independent charge
injection
Rejected by CMFB
Extra switching phases
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45. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 33/72
SVMA Operation
Reduced set of
transistor matching
groups
Full CMOS
implementation
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46. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 33/72
SVMA Operation
Reduced set of
transistor matching
groups
Off-state network
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47. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 33/72
SVMA Operation
Reduced set of
transistor matching
groups
On-state network
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48. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 33/72
1 Introduction
2 ΔΣ-Modulator Architectures
3 Low-Power CMOS Switched-Capacitor Circuits
4 Practical ΔΣM Design in a 0.18-µm CMOS Technology
5 Experimental Results
6 Conclusions
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49. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 34/72
IC Design Environment
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50. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 35/72
High-Level Model
Coefficient a1 a2 a3 a4 c1 c2 c3 c4
Value 0.2 0.4 0.1 0.1 1 1 1 2
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51. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 36/72
High-Level Simulation
103 104 105 106
−200
−150
−100
−50
0
80 dB/dec
Frequency [Hz]
Powerspectraldensity[dBFS/bin]
−100 −50 0
0
20
40
60
80
100
120
Input Amplitude [dBFS]
SQNR[dB]
136 OSR, 13.6 MS/s
13.28-kHz input frequency
117-dB maximum SQNR
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52. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 37/72
Non-Idealities
0 5 10 15
0
20
40
60
80
100
120
mism [%]
SQNRmax,worst[dB]
0 0.05 0.1 0.15 0.2
80
90
100
110
120
sett [%]SQNRmax[dB]
8.25-% maximum coefficient
mismatch
0.035-% maximum settling error
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53. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 38/72
ΔΣM SC Scheme
Fully-differential No bootstrapping No output switches
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54. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 38/72
ΔΣM SC Scheme
Capacitance Value [pF] Capacitance Value [pF] Capacitance Value [pF]
Cfb 21.16 Cff0 0.92
Cs1 42.32 Ci1 211.6 Cff1 0.92
Cs2 3.68 Ci2 9.2 Cff2 0.92
Cs3 0.92 Ci3 9.2 Cff3 0.92
Cs4 0.92 Ci4 9.2 Cff4 1.84
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55. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 39/72
ΔΣM Clock Generation
Digital masking scheme to minimize the number of analog switches
Delayed-phase generation
14 outputs
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56. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 40/72
ΔΣM Operation
Integrator initialization
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57. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 40/72
ΔΣM Operation
Regular operation (phase A)
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58. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 40/72
ΔΣM Operation
Regular operation (phase B)
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59. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 41/72
SVMA Design
Equivalent-condition
extraction
Design-time minimization
Parameter SVMA1 SVMA2 SVMA3,4 Units
Cssi 63.48 3.68 0.92 pF
Cii 211.6 9.2 9.2 pF
Cli 4.6 1.84 1.84 pF
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60. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 42/72
SVMA Design
Basic-parameter analytical estimation
Parameter SVMA1 SVMA2 SVMA3,4 Units
βfb = Cii
Cssi +Cii
0.77 0.71 0.91
Cleffi = Cli + (1 − βfb)Cii 53.4 4.47 2.68 pF
Cleffi/Cli 11.6 2.43 1.46
Aopen = 1
βfb sett
71.4 72 69.9 dB
SR =
Vstep
tslew
46 61.3 15.3 V
µs
Imax = SR · Cleffi 2.46 0.274 0.041 mA
GBW =
ln −1
sett
2πβfbtsett
77.9 83.9 65.9 MHz
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61. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 43/72
Optimization Flow
Automated
variable sweep
Increased
productivity
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62. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 44/72
Sized SVMA1
Optimum values:
kb 4
kz 3
ICin 2
ICtail 4
ICmirr 6
Itail 950 µA
Minimum-channel-
length devices used
Bias for cascode
transistors optimized
for maximum output
full scale
1.8-V nominal voltage
supply of the CMOS
technology
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63. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 45/72
SVMA1 DC Transfer Curve
Minimal deviation under
different process and
temperature conditions
Class-AB achieves about
×4 bias current
−1 −0.5 0 0.5 1
0
0.5
1
1.5
2
Ionn
kb
Ionp
kb
(Iinp − Iinn) /Itail [Itail]
[Itail]
typical at 20 °C
fast at -40 °C
slow at 80 °C
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64. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 46/72
SVMA1-Parameter Extraction
Open-loop-gain and settling-time compliance with specifications
Parameter
typical
20 °C
fast
-40 °C
slow
80 °C
Units
Aopen 74.1 74.7 73.9 dB
SR 139 146 133 V
µs
Imax 7.41 7.8 7.1 mA
GBW 221 250 206 MHz
PM1 54 46.9 60.7 °
PMβ 55.8 48.9 62.8 °
tint 16.41 14.24 19.57 ns
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65. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 47/72
All-SVMA-Parameter Extraction
Open-loop-gain and settling-time compliance with specifications
Parameter SVMA1 SVMA2 SVMA3,4 Units
Aopen 74.1 72.1 70.5 dB
SR 139 36.2 26 V
µs
Imax 7.41 0.162 0.07 mA
GBW 221 95.4 70.9 MHz
PM1 54 77.8 83.1 °
PMβ 55.8 80.2 83.6 °
tint 16.41 25.75 19.82 ns
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66. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 48/72
SVMA Device Sizes
Parameter SVMA1 SVMA2 SVMA3,4 Units
Ccmfb 8050 437 218 fF
Ia1 250 50 50 µA
Ia2 237.5 50 50 µA
Ib 200 50 50 µA
(W/L)MA1 7.48/0.24 1.58/0.24 1.58/0.24 µm/µm
(W/L)MA2 2.7/0.24 0.57/0.24 0.57/0.24 µm/µm
(W/L)MB1,2 28.48/0.48 7.12/0.48 7.12/0.48 µm/µm
(W/L)MB3 154.24/0.48 38.56/0.48 38.56/0.48 µm/µm
(W/L)MC1,2 478.72/0.24 12.64/0.24 6.32/0.24 µm/µm
(W/L)MC3,4 172.8/0.24 4.56/0.24 2.28/0.24 µm/µm
(W/L)MD1,2 59.84/0.24 3.15/0.24 3.16/0.24 µm/µm
(W/L)MD3,4 21.6/0.24 1.14/0.24 1.14/0.24 µm/µm
(W/L)MG1,2 957.44/0.24 25.2/0.24 12.64/0.24 µm/µm
(W/L)MG3,4 345.6/0.24 9.12/0.24 4.56/0.24 µm/µm
(W/L)MI1,2 129.6/0.24 6.8/0.24 3.4/0.24 µm/µm
(W/L)MI3,4 359.04/0.24 18.96/0.24 9.44/0.24 µm/µm
(W/L)ML1,2 957.44/0.24 25.2/0.24 12.64/0.24 µm/µm
(W/L)ML3,4 345.6/0.24 9.12/0.24 4.56/0.24 µm/µm
(W/L)MSN
16/0.18 0.96/0.18 0.48/0.18 µm/µm
(W/L)MSP
144/0.18 8.64/0.18 4.32/0.18 µm/µm
(W/L)MT1 270.56/0.48 14.24/0.48 7.12/0.48 µm/µm
(W/L)MT2 732.64/0.48 38.56/0.48 19.28/0.48 µm/µm
(W/L)MU1,2 239.36/0.24 12.6/0.24 6.32/0.24 µm/µm
(W/L)MU3,4 86.4/0.24 4.56/0.24 2.28/0.24 µm/µm
(W/L)MZ1,2 179.52/0.24 9.45/0.24 3.16/0.24 µm/µm
(W/L)MZ3,4 64.8/0.24 3.42/0.24 1.14/0.24 µm/µm
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67. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 49/72
Feedforward-Switch Optimization
Equivalent switching scheme
Trade-off between the switch conductor capabilities and parasitics
Design-time reduction
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68. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 50/72
Feedforward-Switch Optimization
126-dB SDR
reached for the
worst-case corner
103 104 105 106
0
−50
−100
−150
−200
Frequency [Hz]
Powerspectraldensity[dBFS/bin]
typical at 20 °C
fast at -40 °C
slow at 80 °C
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69. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 51/72
Full-ΔΣM Simulation
105.7-dB SQNDR
reached in the
worst case
16.5-hour
simulation time
for 64 input-signal
sine periods
on Intel ®
CoreTM
CPU i7-2600 @
3.40 GHz
103 104 105 106
0
−20
−40
−60
−80
−100
−120
−140
−160
80 dB/dec
Frequency [Hz]
Powerspectraldensity[dBFS/bin]
typical at 20 °C
fast at -40 °C
slow at 80 °C
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70. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 52/72
CMOS Physical Design
Standard analog layout-design techniques
Gate noise:
V 2
n,g =
4kBT
3m2
W
L
R
Input-referred channel noise:
V 2
n,ch =
8kBT
3gm
Minimum finger number for wide-channel
devices (Vn,ch/Vg,ch = 5):
m = 3.5
W
L
R gm
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71. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 53/72
SVMA1 Post-Layout Simulation Results
Open-loop
frequency
response
200-pF load
capacitance
103 104 105 106 107 108 109
0
−60
−120
−180
Frequency [Hz]
Phase[°]
Phase
Gain
0
10
20
30
40
50
60
70
80
72 dB
50 °
DifferentialGain[dB]
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72. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 54/72
SVMA1 Post-Layout Simulation Results
Step response for several load conditions
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
−1
0
1
2
Time × Input Frequency [-]
DifferentialOutputVoltage[V]
650 µF at 1 Hz, 650 nF at 1 kHz 650 pF at 1 MHz
Hz, 650 nF at 1 kHz 6
Stability robustness
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73. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 55/72
ΔΣM Post-Layout Simulation
Spectre
transient-noise
mode
2-month
simulation time
for 64 input-signal
sine periods
on Intel®
Xeon®
CPU E5-2640 @
2.50 GHz
103-dB SNDR
108.7-dB DR
103 104 105 106
0
−20
−40
−60
−80
−100
−120
−140
−160
80 dB/dec
Frequency [Hz]
Powerspectraldensity[dBFS/bin]
Without transient noise
With transient noise
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74. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 56/72
Test-Vehicle Integration
Standard 0.18-µm 1P6M MIM CMOS technology
4.9-mm2
area
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75. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 57/72
SVMA1
0.07-mm2
area
Additional input
for the external
CMFB control
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76. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 58/72
Full-ΔΣM
1.8-mm2
area
No need for
global symmetry
Separate analog
and digital 1.8-V
supplies
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77. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 58/72
1 Introduction
2 ΔΣ-Modulator Architectures
3 Low-Power CMOS Switched-Capacitor Circuits
4 Practical ΔΣM Design in a 0.18-µm CMOS Technology
5 Experimental Results
6 Conclusions
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78. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 59/72
SVMA Measurement Setup
Unity-gain transient-response measurement
Continuous-time operation
External CMFB control
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79. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 60/72
SVMA Step Response
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80. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 61/72
SVMA Full-Scale Evaluation
0 20 40 60 80 100 120 140 160 180 200
−2
−1
0
1
2
Time [ms]
DifferentialOutputVoltage[V]
Ideal
Simulated
Measured
0
1
2
utputVoltage[V]
3.3-Vpp differential full scale at 1.8-V voltage supply
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81. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 62/72
SVMA Figure-of-Merit Comparison
Parameter [10] [11] [12] [13] [14]
This
work
Units
Technology 0.5 0.5 0.25 0.13 0.18 0.18 µm
Supply 2 2 1.2 1.2 0.8 1.8 V
DC gain 43 45 69 70 51 72 dB
Cload 80 25 4 5.5 8 200 pF
GBW 0.725 11 165 35 0.057 86.5 MHz
Phase margin 89.5 N/A 65 45 60 50 °
Slew rate, SR 89 20 329 19.5 0.14 74.1 V/µs
Static power, P 0.12 0.04 5.8 0.11 0.0012 11.9 mW
Area 0.024 0.012 N/A 0.012 0.057 0.07 mm2
Resistor-free No No Yes Yes Yes Yes mm2
FOM 59.33 12.50 0.28 0.98 0.93 1.25 V
µs
pF
µW
FOM =
SR·Cload
P
V
µs
pF
µW
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82. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 63/72
ΔΣM-DUT Packaging
Dual-in-line 16-pin
ceramic packaging
Top and bottom
shielding layers
In-package
noise-decoupling
capacitors
Interference and noise
reduction
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83. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 64/72
ΔΣM Measurement
Setup
Ultra-low-distortion
function generator as
a input-signal
generator
Low-jitter pulse
generator as a input
clock timebase
Low-noise
battery-based power
supplies and
references
Flexible FPGA-based
readout system
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84. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 65/72
ΔΣM Measurement Results
2.4-Vpp
differential full
scale
-2-dBFS input
amplitude
80-dB/decade
noise-shaping
slope observed
103 104 105 106
0
−20
−40
−60
−80
−100
−120
−140
−160
80 dB/dec
Frequency [Hz]
Powerspectraldensity[dBFS/bin]
Simulated
Measured
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85. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 66/72
ΔΣM Measurement Results
96.6-dB SNDR
105.3-dB SFDR
97-dB DR
SNDR
degradation at
high amplitudes is
avoided
−100 −80 −60 −40 −20 0
0
20
40
60
80
100
Input Amplitude [dBFS]
SNR,SFDR,SNDR[dB]
SNDR
SFDR
SNR
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86. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 67/72
ADC Performance Comparison
[15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27]
This
work
Architecture
ΔΣ
SC
ΔΣ
CT,SC
ΔΣ
SC
ΔΣ
CT,SC
ΔΣ
CT
ΔΣ
SRC
ΔΣ
SC
ΔΣ
SC
ΔΣ
SC
INC
ΔΣ
CT
Pipe+
SAR
ΔΣ
SC
ΔΣ
SC
Technology 0.35 0.35 0.25 0.18 0.18 0.13 0.18 0.18 0.35 0.16 0.18 0.18 0.18 0.18 µm
Supply voltage 5 3.3 1.8 0.9 1.8 0.7 1.5 1.8 5, 1.8 5 1.8 V
Diff. full scale 6.6 5.7 1.4 1.1 1.8 10 4.4 2.4 Vpp
Sampling rate 5.12 6.14 20 6.14 41.7 6.14 45.2 5 2.4 0.05 57.5 5 0.15 13.6 MS
s
Bandwidth 20 20 1000 20 200 24 500 25 20 0.0125 600 2500 0.1 50 kHz
Supply power 55 18 475 37 210 1.5 38 0.87 0.14 0.0063 21 30.5 0.505 7.9 mW
Area 5.6 0.82 20.2 0.65 6 1.44 3.5 2.16 0.21 0.38 0.99 5.74 0.8 1.8 mm2
DR 111 106 103 102 98 92 90.1 100 92.6 100.2 97 dB
SFDRmax 97 90 100.8 105.3 dB
SNDRmax 105 97 95 90 89 86.3 95 87.9 98.6 100.6 96.6 dB
FOMW 9458 7776 2057 20122 20311 1357 2251 378.5 173 314.8 678.2 87.7 28825 1429 fJ
conv
FOMS 160.6 157.5 166.2 152.3 149.8 161.0 157.5 169.6 169.5 182.8 164.6 177.7 153.6 164.6 dB
Bootstrap-free Yes Yes Yes Yes Yes Yes No No No Yes Yes Yes Yes Yes
Calibration-free Yes No Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes Yes
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87. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 68/72
Performance Comparison
20 30 40 50 60 70 80 90 100 110 120
100
101
102
103
104
105
106
107
SNDR [dB]
P/fsnyq[pJ]
Flash
Folding
Pipeline
SAR
CT ΔΣ
SC ΔΣ
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88. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 68/72
Performance Comparison
85 90 95 100 105 110 115 120
104
105
106
107
FOMS = SNDR + 10 log BW
P
[28]
[29]
[15]
[18]
[19]
[20]
[27]
[30]
[17] [24]
[25]
[31]
[32]
[33]
[16]
[21]
[22]
[23]
[26]
This
work
SNDR [dB]
P/fsnyq[pJ]
Feature-compliant
Others
FOMS of this work
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89. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 68/72
1 Introduction
2 ΔΣ-Modulator Architectures
3 Low-Power CMOS Switched-Capacitor Circuits
4 Practical ΔΣM Design in a 0.18-µm CMOS Technology
5 Experimental Results
6 Conclusions
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90. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 69/72
Contributions
Initial working hypotheses successively tested and confirmed:
• High-resolution and low-power state-of-the-art ADC
• Integrated in a low-cost standard CMOS technology
• Using novel analog design techniques at the system and circuit
levels
• No bootstrapping, analog calibration or digital
post-compensation
Selection guide of SC ΔΣM ADCs
Efficient framework based on open-source EDA tools
New family of single-stage Class-AB OpAmps: VMAs
SVMA- and ΔΣM-demonstrator implementation and measurements
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91. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 70/72
Research Funding
2007-2011: Chemical Warfare Agents Analyzer Based on
Low Cost Dual Band IR Microsystem (CANARIO)
EDA-B-DO61-IAP2-ERG:
32-channel read-out low-power IC
2009-2012: Perishable Monitoring through Short Tracking of
Lifetime and Quality by RFID (PASTEUR)
CATRENE CT204:
Low-power smart sensor with integrated
potentiostatic ΔΣ ADC
2011-2015: ESA Cosmic Vision MF ASIC
ESTEC 40000101556/10/NL/AF:
4 low-power ΔΣ ADCs with multiple BWs and SNDRs
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92. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 71/72
Publications
11 papers:
• 9 published (2 awarded)
• 2 being disseminated:
[+] S. Sutula, M. Dei, L. Terés, and F. Serra-Graells, “Variable-Mirror
Amplifier: A New Family of Process-Independent Class-AB
Single-Stage OpAmps for Low-Power SC Circuits,” submitted to the
IEEE Transactions on Circuits and Systems I.
[+] S. Sutula, M. Dei, L. Terés, and F. Serra-Graells, “A
Calibration-Free 96.6-dB-SNDR Non-Bootstrapped 1.8-V 7.9-mW
Delta-Sigma Modulator with Class-AB Single-Stage
Switched-OpAmps,” submitted to the IEEE International
Symposium on Circuits and Systems, Montreal, 2016.
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93. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 72/72
Future Work
Integration on the same die with the sensor array
LVDS-bus implementation
Decoupling-capacitor increase
Multi-bit-ΔΣM exploration
Reuse of low-current design techniques in the low-voltage realm
Thank you!
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94. Low-Power High-Resolution CMOS SC ΔΣ ADCs Intro ΔΣMs Circuits Design Results Conclusions 72/72
References
[1] S. Sutula, M. Dei, L. Terés, and F. Serra-Graells, “Class-AB Single-Stage
OpAmp for Low-Power Switched-Capacitor Circuits,” in Proceedings of the IEEE
International Symposium on Circuits and Systems, pp. 2081–2084, 2015,
Student Best Paper Award Honorable Mention.
[2] S. Sutula, F. Vila, J. Pallarès, K. Sabine, L. Terés, and F. Serra-Graells,
“Teaching Mixed-Mode Full-Custom VLSI Design with gaf, SpiceOpus and
Glade,” in Proceedings of the 10th European Workshop on Microelectronics
Education, pp. 43–48, 2014.
[3] J. Pallarès, F. Vila, S. Sutula, K. Sabine, L. Terés, and F. Serra-Graells, “A
Freeware EDA Framework for Teaching Mixed-Mode Full-Custom VLSI Design,”
in Proceedings of the XIX Conference on Design of Circuits and Integrated
Systems, 2014.
[4] S. Sutula, J. Pallarès Cuxart, J. Gonzalo-Ruiz, F. Xavier Munoz-Pascual,
L. Terés, and F. Serra-Graells, “A 25-uW All-MOS Potentiostatic Delta-Sigma
ADC for Smart Electrochemical Sensors,” IEEE Transactions on Circuits and
Systems I: Regular Papers, vol. 61, pp. 671–679, 2014.
[5] J. Pallarès, S. Sutula, J. Gonzalo-Ruiz, F. X. Muñoz-Pascual, L. Terés, and
F. Serra-Graells, “A Low-Power MOS-Only Potentiostatic Delta-Sigma ADC
Architecture for Electrochemical Sensors,” in Proceedings of the XIX Conference
on Design of Circuits and Integrated Systems, 2014, Best Paper Award.
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[6] S. Sutula, C. Ferrer, and F. Serra-Graells, “Design and Modeling of a Low-Power
Multi-Channel Integrated Circuit for Infrared Gas Recognition,” Elsevier
Microprocessors and Microsystems, vol. 36, pp. 355–364, 2012.
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Frontend Channel for Infrared Spectroscopic Gas Recognition,” IEEE
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[8] S. Sutula, C. Ferrer, and F. Serra-Graells, “A 100µA/Ch Fully-Integrable Lock-in
Multi-Channel Frontend for Infrared Spectroscopic Gas Recognition,” in
Proceedings of the IEEE International Symposium on Circuits and Systems,
pp. 2267–2270, 2010.
[9] S. Sutula, C. Ferrer, and F. Serra-Graells, “Design and Modeling of a 0.4mW/Ch
Multi-Channel Integrated Circuit for Infrared Gas Recognition,” in Proceedings of
the XXV Conference on Design of Circuits and Integrated Systems, pp. 226–271,
2010.
[10] A. J. López-Martín, S. Baswa, J. Ramirez-Angulo, and R. G. Carvajal,
“Low-Voltage Super Class AB CMOS OTA Cells With Very High Slew Rate and
Power Efficiency,” IEEE Journal of Solid-State Circuits, vol. 40, pp. 1068–1077,
2005.
[11] J. Ramirez-Angulo, R. G. Carvajal, J. A. Galan, and A. Lopez-Martin, “A Free
But Efficient Low-Voltage Class-AB Two-Stage Operational Amplifier,” IEEE
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2006.
[12] M. Yavary and O. Shoaei, “Very Low-Voltage, Low-Power and Fast-Settling OTA
for Switched-Capacitor Applications,” in Proceedings of the International
Conference on Microelectronics, pp. 10–13, 2002.
[13] M. Figueiredo, R. Santos-Tavares, E. Santin, J. Ferreira, G. Evans, and J. Goes,
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[15] Y. Yang, A. Chokhawala, M. Alexander, J. Melanson, and D. Hester, “A 114-dB
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[16] K. Nguyen, B. Adams, K. Sweetland, H. Chen, and K. McLaughlin, “A 106dB
SNR Hybrid Oversampling ADC for Digital Audio,” in Proceedings of the IEEE
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[17] R. Brewer, J. Gorbold, P. Hurrell, C. Lyden, R. Maurino, and M. Vickery, “A
100dB SNR 2.5MS/s Output Data Rate ΔΣ ADC,” in Proceedings of the IEEE
International Solid-State Circuits Conference, pp. 172–173, 2005.
[18] P. Morrow, M. Chamarro, C. Lyden, P. Ventura, A. Abo, A. Matamura,
M. Keane, R. O’Brien, P. Minogue, J. Mansson, N. McGuinness,
M. McGranaghan, and I. Ryan, “A 0.18µm 102dB-SNR Mixed CT SC
Audio-Band ΔΣ ADC,” in Proceedings of the IEEE International Solid-State
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[19] P. Silva, L. Breems, K. Makinwa, R. Roovers, and J. Huijsing, “An 118dB DR
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[20] M. Kim, G. Ahn, P. Hanumolu, S. Lee, S. Kim, S. You, J. Kim, G. Temes, and
U. Moon, “A 0.9V 92dB Double-Sampled Switched-RC ΔΣ Audio ADC,” in
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[21] A. Agah, K. Vleugels, P. Griffin, M. Ronaghi, J. Plummer, and B. Wooley, “A
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[22] H. Park, K. Nam, D. K. Su, K. Vleugels, and B. A. Wooley, “A 0.7-V 100-dB
870-µW Digital Audio ΔΣ Modulator,” in Symposium on VLSI Circuits Digest of
Technical Papers, pp. 178–179, 2008.
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[23] T. Christen, “A 15bit 140µW Scalable-Bandwidth Inverter-Based Audio ΔΣ
Modulator with >78dB PSRR,” in Proceedings of the European Solid-State
Circuits Conference, pp. 209–212, 2012.
[24] Y. Chae, K. Souri, and K. Makinwa, “A 6.3µW 20b Incremental Zoom-ADC with
6ppm INL and 1µV Offset,” in Proceedings of the IEEE International Solid-State
Circuits Conference, pp. 276–277, 2013.
[25] A. Bandyopadhyay, R. Adams, N. Khiem, P. Baginski, D. Lamb, and T. Tansley,
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Design Variables
Reduced set of input variables
Simplified SVMA-optimization process
Automated result back-annotation
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SVMA1 DC Transfer Curve versus kz
b03v02
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