Tarun Arora is seeking an internship in analog domain. He has a Master's degree in Electrical Engineering from Arizona State University and a Bachelor's degree from Kurukshetra University in India. His relevant coursework includes analog integrated circuits and VLSi design. He has experience with Cadence and other design tools. His projects include designing operational transconductance amplifiers and constant current references using Cadence. He also has experience with embedded systems and microcontrollers from projects in college. Previously he interned at a power plant and worked as a systems engineer at Tata Consultancy Services.

1. Tarun Arora
919 East Lemon St. Apt. #211, Tempe, AZ 85281 480.278.5145 tarunarora_02@yahoo.in, tarora1@asu.edu
Objective-Seeking an internship in the field of Analog Domain
EDUCATION
Ira A.Fulton School of Engineering at Master of Electrical Engineering, Analog and Mixed Signal (3.16/4.0) May-2013
Arizona State University, Tempe, AZ Design
Kurukshetra University, India Bachelor of Engineering, Instrumentation and control (3.8/4.0) June-2010
Engineering
RELEVANT COURSES (till 2nd sem at Arizona State University)
Fundamentals of Solid State Devices Analog Integrated Circuits Digital System Circuits
Advanced Quality Control V.L.S.I Design Advanced Analog Integrated Circuits
TECHNICAL SKILLS
Design Tools Cadence,Virtuoso IC Design Suite,Spectre,Xilinx ISE 12.1
Embedded tools Mplab,CVR-AVR microcontroller programming software,CVR studio.
Programming Languages C,C++,embedded C,Perl,Verilog.Matlab
Operating Systems Linux/Unix, MS-DOS, MAC OS, Windows (XP, 7, Vista)
PROJECTS
 Design Of Symmetric Operational Tran conductance Amplifier (OTA) (I) [Cadence ICFB, TSMC 0.3um CMOS]
 Designed three OTA’s Basic, High Impedance and OTA with common Source Buffer
 All the three circuits were optimized for Common Mode Range of .85 to 1.35V with gain greater then 43dB,UGF
–at 35MHZ,PSRR and CMRR 25dB at 10KHZ., and O/P Swing 1V peak to peak load cap 1pF.
 Plotted FFT to meet the distortion specs.0 dB and 6DB gain in unity gain configuration and HD3 of 20dB and 40
dB for Basic, High Impedance and OTA with common Source Buffer
 Layout using Common Centroid and Multi-Finger techniques matching is improved by using dummy transistors
 Rail to Rail Differential Amplifier(I) [Cadence ICFB, TSMC 0.3um CMOS]
 Biasing for the circuit is done by using Wide Swing Cascode Curent Source for both Pmos and Nmos Diff. Pair
 Met the gain spec of 40dB,UGF 80Mhz ,Power Less than 1mW and load capacitance 1pF.
 Common Mode range was maximized from 0.4V to 2.6V
 CMOS β-multiplier based constant-gm current reference current mirrors(I) [Cadence ICFB, TSMC 0.3um CMOS]
 Designed three CMOS β-multiplier, Simple ,Cascoded and with Feedback
 Optimized the circuit to achieve constant reference currents for wide range of VDD from 2V to 3V.
 Rectified the reference current and voltage generated for constant transconductance over temperature
variations from -20C to -85C.
 Mismatching between two references currents was less than 5%
 Two Stage Differential Amplifier with active Load (I) [Cadence ICFB, TSMC 0.3um CMOS]
 Circuit was optimized with the supply of 5uA ,Differential voltage Gain 50dB and O/P swing 1V peak to peak
 Performed the simulations for PSRR 45 dB ,CMRR 44.5dB , Common mode gain of -6.4 kdB, Rin=0.2749 GΩ,
Rout= 25.18 kΩ.
 The differential amplifier was simulated to cancel out Common mode (noise) pertaining to its high CMRR.

2.  Shunt-Shunt Feedback Circuit(I ) [Cadence ICFB, TSMC 0.3um CMOS]
 The design was implemented at transistor level with achieving following specifications
Rinf<150kΩ,Rof<6KΩ,I<1.5mA.
 The amplifier with feedback was verified to have a reduced gain of 129.3dB( gain without feedback obtained
was 161.2dB) and an extended bandwidth of 6.35MHZ(3dB Bandwidth without feedback was 34.67 KHz)
 Line follower (G) Embedded Project [Cvr Avr ,Microcontroller Atmega(32)]
 A bot which can trace the black line on white surface using microcontroller Atmega(32) and IR Leds.
 Responsible for designing circuit, gathering component and soldering on general PCB board.
 Project was ranked top among the 100 Participants in the International Technical Fest Held at Bits Pilani in 2009
 Game on Chip (G) Embedded Project [Cvr Avr ,Microcontroller Atmega(32)]
 A game similar to mobile applications. Snake tales gets bigger and bigger as it keeps on eating food and gets
overed when snake collapses with itself
 Responsible for designing circuit , gathering component and soldering on general PCB board.
 Project was ranked top among the 100 Participants in the International Technical Fest Held at Bits Pilani in 2009
PROFESSIONAL EXPERIENCE (G – group project )
Tata Consultancy Services Ltd. DEC 2010-JUNE2011
Assistant System Engineer, (Client: State bank of India.), Mumbai, India
 Project of airline reservation and hotel reservation system (dummy project during training).using core
java,c++,and my sql. (G)
 Done coding for two blocks - updation of room status and airline status and generation of bill.
National Thermal Power Plant (Intern for 3 months) JUNE 2008-SEPT2008
 Worked on embedded systems Atmega family.
 Studied various losses in the transformers .
AWARDS AND AFFILIATIONS
First Winner of international technical fest at Bits Pilani for Line follower, 2009
First Winner of international technical fest at Bits Pilani for Game on chip, 2009
Organized various programming and designing events during undergraduation 2008-2010