This document compares time domain measurements and simulations of S-parameters for a 1.83m RG58 coaxial cable. Measurements were taken using a TDR setup and compared to simulations using Spicy Swan, MC10, and Cable Studio circuit simulators. Good agreement was found between the measured and simulated waveforms for S11 and S21, though the simulations did not fully capture effects like distributed impedance discontinuities and dielectric losses in the real cable. Optimizing parameters like transmission line delay improved the match between simulated and measured results.
Nhận viết luận văn đại học, thạc sĩ trọn gói, chất lượng, LH ZALO=>0909232620
Tham khảo dịch vụ, bảng giá tại: https://vietbaitotnghiep.com/dich-vu-viet-thue-luan-van
Download luận văn đồ án tốt nghiệp ngành điện tử công nghiệp với đề tài: Thiết kế và thi công mô hình điều khiển, giám sát bãi giữ xe ô tô tự động, cho các bạn làm luận văn tham khảo
The document is a technical report in Vietnamese on microcontroller processing techniques. It includes 8 experiments using an ATmega16 microcontroller to control LEDs on Port A in different patterns by reading switches on Port B. It provides code and explanations for each experiment, which involve turning LEDs on and off individually or in sequences to demonstrate concepts like bit shifting, delays, and scanning I/O ports.
Nhận viết luận văn đại học, thạc sĩ trọn gói, chất lượng, LH ZALO=>0909232620
Tham khảo dịch vụ, bảng giá tại: https://vietbaitotnghiep.com/dich-vu-viet-thue-luan-van
Download luận văn đồ án tốt nghiệp ngành điện tử công nghiệp với đề tài: Thiết kế và thi công mô hình điều khiển, giám sát bãi giữ xe ô tô tự động, cho các bạn làm luận văn tham khảo
The document is a technical report in Vietnamese on microcontroller processing techniques. It includes 8 experiments using an ATmega16 microcontroller to control LEDs on Port A in different patterns by reading switches on Port B. It provides code and explanations for each experiment, which involve turning LEDs on and off individually or in sequences to demonstrate concepts like bit shifting, delays, and scanning I/O ports.
Nhận viết luận văn đại học, thạc sĩ trọn gói, chất lượng, LH ZALO=>0909232620
Tham khảo dịch vụ, bảng giá tại: https://vietbaitotnghiep.com/dich-vu-viet-thue-luan-van
Download luận văn đồ án tốt nghiệp ngành kĩ thuật điện tử với đề tài: Thiết kế và thi công hệ thống giám sát điện năng tiêu thụ kết hợp với điều khiển thiết bị điện từ xa thông qua internet và Lora, cho các bạn làm luận văn tham khảo
Nhận viết luận văn đại học, thạc sĩ trọn gói, chất lượng, LH ZALO=>0909232620
Tham khảo dịch vụ, bảng giá tại: https://vietbaitotnghiep.com/dich-vu-viet-thue-luan-van
Download luận văn thạc sĩ với đề tài: Thiết kế và mô phỏng điều khiển PLC hệ thống rửa xe tự động, cho các bạn làm luận văn tham khảo
Nhận viết luận văn đại học, thạc sĩ trọn gói, chất lượng, LH ZALO=>0909232620
Tham khảo dịch vụ, bảng giá tại: https://vietbaitotnghiep.com/dich-vu-viet-thue-luan-van
Download luận văn đồ án tốt nghiệp ngành điện tử công nghiệp với đề tài: Thiết kế và thi công hệ thống điểm danh nhân viên sử dụng vi điều khiển ARM, cho các bạn làm luận văn tham khảo
Nhận viết luận văn Đại học , thạc sĩ - Zalo: 0917.193.864
Tham khảo bảng giá dịch vụ viết bài tại: vietbaocaothuctap.net
Download luận văn đồ án tốt nghiệp ngành kĩ thuật điện với đề tài: Thiết kế và thi công mô hình xe robot dò tìm kim loại điều khiển bằng điện thoại, cho các bạn làm luận văn tham khảo
This document describes the components and functions of an automotive communication stack. It discusses:
- The Run-Time Environment (RTE) which provides an interface between application software and lower communication layers.
- Modules like COM, PduR, CanTp, and CanIf which package signals into PDUs and map PDUs to CAN IDs.
- The Can module which accesses microcontroller registers to send and receive actual CAN frames.
- Concepts like PDUs, signals, and hardware objects which are used to exchange data between ECUs.
- The configuration of parameters, variants, and containers which define the generic parts of a module's implementation.
Nhận viết luận văn đại học, thạc sĩ trọn gói, chất lượng, LH ZALO=>0909232620
Tham khảo dịch vụ, bảng giá tại: https://vietbaitotnghiep.com/dich-vu-viet-thue-luan-van
Download đề tài: Ứng dụng PLC S7 200 đo, điều khiển và cảnh báo nhiệt độ trong lò với giải đo [ 0 – 1200 ]°C, cho các bạn làm luận văn tham khảo
To gain an understanding of the way in which
PROFINET devices communicate with one
another over Ethernet.
• To learn how to capture the PROFINET
Frames using Wireshark®.
• To see how Wireshark® can be used to analyse
the captured frames to gain an understanding
of the various protocols.
• This is a topic covered in more detail in the
Certified PROFINET Engineers Course
Tdr measurement of rg58 coaxial cable s parameters 120413Piero Belforte
This document describes the setup and modeling of a 1.83m RG58 cable. Measurements were taken of the cable's S-parameters. Distributed Line (RL-TL) and PWL models were created in Spicy SWAN. The RL-TL model matched the measured S11 reasonably but was not asymmetric like the real cable. Both models matched the measured S21 risetime of 80ps. The eye diagram from measurement showed slightly more closure due to dielectric losses not in the models. Overall the DWS simulator was effective and faster than other methods for this cable characterization.
TDR-BASED DWS MODELING OF PASSIVE COMPONENTSPiero Belforte
1) Interconnection lengths of just a few centimeters can impact signal integrity for signals with rise times under 1 nanosecond due to reflections, dispersion, and skin effect. Distributed models are needed to account for these effects.
2) Measurements from a reflectometer can be used to create behavioral models in the time domain of passive components like cables and connectors. These measurement-based models capture effects that simpler lumped or distributed models cannot.
3) For a sample coaxial cable, reflectometer data was extracted and used to create S-parameter models of the cable in the DWS simulator. Simulations using these models matched the actual reflectometer measurements very closely, validating the behavioral modeling approach.
Nhận viết luận văn đại học, thạc sĩ trọn gói, chất lượng, LH ZALO=>0909232620
Tham khảo dịch vụ, bảng giá tại: https://vietbaitotnghiep.com/dich-vu-viet-thue-luan-van
Download luận văn đồ án tốt nghiệp ngành kĩ thuật điện tử với đề tài: Thiết kế và thi công hệ thống giám sát điện năng tiêu thụ kết hợp với điều khiển thiết bị điện từ xa thông qua internet và Lora, cho các bạn làm luận văn tham khảo
Nhận viết luận văn đại học, thạc sĩ trọn gói, chất lượng, LH ZALO=>0909232620
Tham khảo dịch vụ, bảng giá tại: https://vietbaitotnghiep.com/dich-vu-viet-thue-luan-van
Download luận văn thạc sĩ với đề tài: Thiết kế và mô phỏng điều khiển PLC hệ thống rửa xe tự động, cho các bạn làm luận văn tham khảo
Nhận viết luận văn đại học, thạc sĩ trọn gói, chất lượng, LH ZALO=>0909232620
Tham khảo dịch vụ, bảng giá tại: https://vietbaitotnghiep.com/dich-vu-viet-thue-luan-van
Download luận văn đồ án tốt nghiệp ngành điện tử công nghiệp với đề tài: Thiết kế và thi công hệ thống điểm danh nhân viên sử dụng vi điều khiển ARM, cho các bạn làm luận văn tham khảo
Nhận viết luận văn Đại học , thạc sĩ - Zalo: 0917.193.864
Tham khảo bảng giá dịch vụ viết bài tại: vietbaocaothuctap.net
Download luận văn đồ án tốt nghiệp ngành kĩ thuật điện với đề tài: Thiết kế và thi công mô hình xe robot dò tìm kim loại điều khiển bằng điện thoại, cho các bạn làm luận văn tham khảo
This document describes the components and functions of an automotive communication stack. It discusses:
- The Run-Time Environment (RTE) which provides an interface between application software and lower communication layers.
- Modules like COM, PduR, CanTp, and CanIf which package signals into PDUs and map PDUs to CAN IDs.
- The Can module which accesses microcontroller registers to send and receive actual CAN frames.
- Concepts like PDUs, signals, and hardware objects which are used to exchange data between ECUs.
- The configuration of parameters, variants, and containers which define the generic parts of a module's implementation.
Nhận viết luận văn đại học, thạc sĩ trọn gói, chất lượng, LH ZALO=>0909232620
Tham khảo dịch vụ, bảng giá tại: https://vietbaitotnghiep.com/dich-vu-viet-thue-luan-van
Download đề tài: Ứng dụng PLC S7 200 đo, điều khiển và cảnh báo nhiệt độ trong lò với giải đo [ 0 – 1200 ]°C, cho các bạn làm luận văn tham khảo
To gain an understanding of the way in which
PROFINET devices communicate with one
another over Ethernet.
• To learn how to capture the PROFINET
Frames using Wireshark®.
• To see how Wireshark® can be used to analyse
the captured frames to gain an understanding
of the various protocols.
• This is a topic covered in more detail in the
Certified PROFINET Engineers Course
Tdr measurement of rg58 coaxial cable s parameters 120413Piero Belforte
This document describes the setup and modeling of a 1.83m RG58 cable. Measurements were taken of the cable's S-parameters. Distributed Line (RL-TL) and PWL models were created in Spicy SWAN. The RL-TL model matched the measured S11 reasonably but was not asymmetric like the real cable. Both models matched the measured S21 risetime of 80ps. The eye diagram from measurement showed slightly more closure due to dielectric losses not in the models. Overall the DWS simulator was effective and faster than other methods for this cable characterization.
TDR-BASED DWS MODELING OF PASSIVE COMPONENTSPiero Belforte
1) Interconnection lengths of just a few centimeters can impact signal integrity for signals with rise times under 1 nanosecond due to reflections, dispersion, and skin effect. Distributed models are needed to account for these effects.
2) Measurements from a reflectometer can be used to create behavioral models in the time domain of passive components like cables and connectors. These measurement-based models capture effects that simpler lumped or distributed models cannot.
3) For a sample coaxial cable, reflectometer data was extracted and used to create S-parameter models of the cable in the DWS simulator. Simulations using these models matched the actual reflectometer measurements very closely, validating the behavioral modeling approach.
Comparison of time-domain S-parameters of RG58 cable computed by Theory, CST,...Piero Belforte
A comparison of time-domain S-parameters of a RG58 cable computed by different methods including Theory, CST simulator , SPICE (MC10) and DWS simulators. The good agreement among methods is shown as well as DWS advantages for fast modeling and simualtions of lossy lines using both circuital, BTM and hybrid methods.
The document compares time-domain S-parameters of an RG58 cable computed using different simulation methods: theory, CST Microwave Studio (MWS), SPICE, and Digital Wave Simulator (DWS). It simulates an 18.3 cm RG58 coaxial cable and calculates its S11 and S21 parameters using each method. The results are then compared between methods. MWS and Cable Studio provide similar results with slightly lower losses than DWS and SPICE with an RL-TL model. The document also analyzes adding dielectric losses and discusses the advantages and drawbacks of each simulation approach.
Design of Continuous Time Multibit Sigma Delta ADC for Next Generation Wirele...IJERA Editor
This paper presents the design of CT ΣΔ modulator which can provide high DR and SNR over a 20 MHz signal bandwidth. So far all the CT SDM uses either feedback or feedforward loop filter architecture. The proposed topology is a 3rd order low-pass sigma-delta modulator, which employs a combination of feedforward and feedback schemes. Loop filter is designed as RC integrators due to its high linearity and easy interface. The design starts from system level using Matlab/Simulink. Then, the first integrator in the loop, which is the most critical block in the modulator, is implemented at transistor level using Cadence Virtuoso 180 nm CMOS technology.
Behavioral Analysis of Second Order Sigma-Delta Modulator for Low frequency A...IOSR Journals
This document discusses behavioral analysis of a second order sigma-delta modulator for low frequency applications. It describes various non-idealities that can occur in switched capacitor sigma-delta modulators, including clock jitter, thermal noise, operational amplifier noise, finite DC gain, finite bandwidth, and slew rate. Mathematical models are presented for each non-ideality, and it is noted that accurate time domain simulation accounting for these effects is needed to optimize performance. The rest of the document will focus on simulating a second order sigma-delta modulator in MATLAB Simulink to analyze the individual and combined effects of the non-idealities on the modulator's performance for signal bandwidths up to 4 kHz.
IRJET- Design of Memristor based MultiplierIRJET Journal
This document describes the design of a 4-bit multiplier circuit using memristors. It begins with an introduction to memristors and their advantages over CMOS technology. It then discusses different window functions that can be used for memristor models and selects the Biolek window function. The document implements a 2-bit and 4-bit array multiplier circuit using memristor-CMOS hybrid logic gates. It analyzes the results in LTSpice and finds improvements in area and component count compared to traditional CMOS and other memristor-based designs. The document concludes memristors can help reduce area for multiplier circuits.
Simulations of a typical CMOS amplifier circuit using the Monte Carlo methodIJERA Editor
In the present paper of Microelectronics, some simulations of a typical circuit of amplification, using a CMOS transistor, through the computational tools were performed. At that time, PSPICE® was used, where it was possible to observe the results, which are detailed in this work. The imperfections of the component due to manufacturing processes were obtained from simulations using the Monte Carlo method. The circuit operating point, mean and standard deviation were obtained and the influence of the threshold voltage Vth was analyzed.
IRJET- Performance Analysis of Clock and Data Recovery Circuits using Multile...IRJET Journal
This document discusses several techniques for improving the performance of clock and data recovery circuits. It describes a multi-level half-rate phase detector that offers a trade-off between linear and bang-bang phase detection, providing multiple quantization levels to better control the voltage-controlled oscillator. It also presents an adaptive loop gain strategy for clock and data recovery circuits that enhances jitter performance. Additionally, it proposes a built-in jitter measurement circuit using calibration techniques to reduce timing resolution variations and improve measurement accuracy.
In this paper, a new topology of Adaptive Hysteresis Band controller for Boost & Buck converter has been proposed, modeled and analyzed. The difficulties caused in Hysteresis Band (HB) controlled dc-dc converter have been eliminated using Adaptive Hysteresis Band (AHB) controller. This novel control topology can be able to maintain the switching frequency constant unlike HB controller. Thus the filter design for the converters will become easier with this controller. Again this control methodology is a robust one as it depends upon the system parameters where there was no possibility with HB controller. The Mathematical modeling of the controller is shown in this paper, further this has been simulated using Matlab /SIMULINK to generate pulse. The steady state analysis to find the parameters and the stability condition of the converter using the dynamic behavior is also portrayed in this paper. The simulation for a Boost and a Buck converter is also shown separately using AHB controller.
The induction motors are indispensable motor types for industrial applications due to its wellknown advantages. Therefore, many kind of control scheme are proposed for induction motors over the past years and direct torque control has gained great importance inside of them due to fast dynamic torque response behavior and simple control structure. This paper suggests a new approach on the direct torque controlled induction motors, Fuzzy logic based space vector
modulation, to overcome disadvantages of conventional direct torque control like high torque ripple. In the proposed approach, optimum switching states are calculated by fuzzy logic
controller and applied by space vector pulse width modulator to voltage source inverter. In order to test and compare the proposed DTC scheme with conventional DTC scheme
simulations, in Matlab/Simulink, have been carried out in different speed and load conditions. The simulation results showed that a significant improvement in the dynamic torque and speed responses when compared to the conventional DTC scheme.
On the Impact of Timer Resolution in the Efficiency Optimization of Synchrono...IJPEDS-IAES
Excessive dead time in complementary switches causes significant energy losses in DC-DC
power conversion. The optimization of dead time prevents the degradation of overall efficiency
by minimizing the body diode conduction of power switches and, as a consequence,
also reduces reverse recovery losses. The present work aims at analyzing the influence of
one of the most important characteristics of a digital controller, the timer resolution, in the
context of dead-time optimization for synchronous buck converters. In specific, the analysis
quantifies the efficiency dependency on the timer resolution, in a parameter set that comprises
duty-cycle and dead-time, and also converter frequency and analog-to-digital converter
accuracy. Based on a sensorless optimization strategy, the relationship between all
these limiting factors is described, such as the number of bits of timer and analog-to-digital
converter. To validate our approach experimental results are provided using a 12-to-1.8V
DC-DC converter, controlled by low- and high-resolution pulse-width modulation signals
generated with an XMC4200 microcontroller from Infineon Technologies. The measured
results are consistent with our analysis, which predicts the power efficiency improvements
not only with a fixed dead time approach, but also with the increment of timer resolution.
PARASITIC-AWARE FULL PHYSICAL CHIP DESIGN OF LNA RFIC AT 2.45GHZ USING IBM 13...Ilango Jeyasubramanian
This document summarizes the design of a low noise amplifier (LNA) operating at 2.45GHz. The LNA uses a cascode topology with inductive source degeneration implemented in a 120nm CMOS process. Simulation results show the LNA meets specifications for gain, return loss, output match, noise figure, and linearity over 2.4-2.5GHz. Variability analysis demonstrates performance remains within specifications with +/-10% parameter variations. The compact layout achieves good matching through careful device placement and use of appropriate passive components to minimize parasitics.
The document presents a modified control method for a Doubly Fed Induction Generator (DFIG) wind turbine that improves stability of active and reactive power outputs during grid voltage unbalances. The modification uses hybrid PI-Fuzzy controllers for rotor side converter control along with a sequence component controller and notch filter to eliminate negative sequence grid voltage components. Simulation results show the modified control method with PI-Fuzzy controllers and sequence component control improves stability of the DFIG's active and reactive power outputs compared to the traditional stator flux oriented control during grid voltage unbalances.
This document presents the design of a high performance folded cascade OTA and sample and hold circuit. The OTA is designed to achieve 10-bit resolution while operating at a 28 MHz sampling frequency. Simulation results show the OTA achieves a high open loop gain of 72 dB and bandwidth of 112 MHz, with a phase margin of 73 degrees. A low resistance transmission gate switch is designed to reduce charge injection and clock feedthrough effects during sampling. The circuit is implemented in a 130 nm CMOS technology.
Reach and Operating Time Correction of Digital Distance Relay Yayah Zakaria
Current and voltage signals recieved from conventional iron core Current Transformer (CT) and Voltage Transformer plays very important role for correct operation of Distance Distance Relay (DDR). Increase in secondary burden connected to CT causes it to saturate at earlier stage. The saturated CT produces distorted secondary current, causing DDR to under reach and to operate by certain time delay. Rogowski Coils (RCs) are attaining increased acceptance and use in electrical power system due to their inherent linearity, greater accuracy and wide operating current range. This paper presents use of RC as an advanced measurement device suitable for DDR. Case study for validation of use of RC is carried out on low voltage system. The simulation results of Distance protection scheme used for protection of part of 220kV AC system shows excellent performance of RC over CT under abnormal conditions.
Reach and Operating Time Correction of Digital Distance Relay IJECEIAES
Current and voltage signals recieved from conventional iron core Current Transformer (CT) and Voltage Transformer plays very important role for correct operation of Distance Distance Relay (DDR). Increase in secondary burden connected to CT causes it to saturate at earlier stage. The saturated CT produces distorted secondary current, causing DDR to under reach and to operate by certain time delay. Rogowski Coils (RCs) are attaining increased acceptance and use in electrical power system due to their inherent linearity, greater accuracy and wide operating current range. This paper presents use of RC as an advanced measurement device suitable for DDR. Case study for validation of use of RC is carried out on low voltage system. The simulation results of Distance protection scheme used for protection of part of 220kV AC system shows excellent performance of RC over CT under abnormal conditions.
250 MHz Multiphase Delay Locked Loop for Low Power Applications IJECEIAES
This document summarizes a research paper that proposes a 250 MHz multiphase delay locked loop (DLL) for low power applications. The DLL is implemented using a 0.18um CMOS technology and operates at 1.8V with a power consumption of 1.39mW at 125MHz center frequency and locking range of 0.5MHz to 250MHz. Key components of the DLL include a modified true single phase clock phase frequency detector, a charge pump and second order loop filter, and a voltage controlled delay line consisting of single ended differential pair delay cells. Simulation results show the DLL provides proper clock synchronization with negligible phase error between the reference clock and DLL output clocks.
Fault modeling and parametric fault detection in analog VLSI circuits using d...IJECEIAES
In this article we describe new model for determination of fault in circuit and also we provide detailed analysis of tolerance of circuit, which is considered one of the important parameter while designing the circuit. We have done mathematical analysis to provide strong base for our model and also done simulation for the same. This article describes detailed analysis of parametric fault in analog VLSI circuit. The model is tested for different frequencies for compactness and its flexibility. The tolerance analysis is also done for this purpose. All the simulation are done in MATLAB software.
Similar to 2013 06 tdr measurement and simulation of rg58 coaxial cable s-parameters_final (20)
Spicy schematics facebook post collection 2012 13 (SWAN applications)Piero Belforte
This document contains a collection of 37 Facebook posts from the page "Spicy Schematics - ischematics.com" from 2012-2013 showcasing circuit simulations and models created using the Spicy Schematics SWAN simulation software. The posts include simulations of transmission lines, cables, amplifiers, oscillators, and digital circuits along with comparisons between different simulation methods. Many of the posts provide simulation results, diagrams, and discussion of modeling techniques.
This document should be very interesting to an engineer because it reports a not biased experimental validation of a predictive tool carried out by a customer for an actual multiboard avionics design. The general considerations are reported at the beginning of the document...the conclusion is that a tool like PRESTO can save up to a 30% in the development time of a system like this . I have other papers reporting validations but these refers to specific non production test vehicules. Then if you give a quick look to the rest of the doc you will have an idea of what is the level of compliance between measurements and predictions...some results are very close together and other shows differences up to 70% or so...but we as engineers we have always to consider the min-max spread of technical specs for digital components may be in order of 100% or more of typical value so it is a nonsense trying to achieve better compliance. Moreover the digital test patterns involved are not the actual ones , and this can make a significant difference, even if Presto was provided with a feature allowing the user to put in the model actual test patterns as input stimuli. Presto was a state-of-the art post -layout tool at this time and this thanks to both the simulation engine (SPRINT, the predecessor of DWS) and to the modeling techniques including PD planes. Extracted nets of up to hundreds of thousands of lines (circuital elements) were simulated in some tens of minutes on machines that were 1000 times slower than today PCs. A true CO-SIMULATION of SI , PI and EMC was performed...no other commercial tool was able to achieve this performance level.
This can give you an idea of the capabilties of both DWS and related modeling methods like BTM ...the PI/SI examples I'm building up for Spicy SWAN are only a very small subset of the complexity Presto was able to deal with.
The document provides a history of Digital Wave Simulator (DWS) from its origins in the 1970s to the present. It details how DWS evolved from early digital wave algorithms developed by the author at CSELT to commercial programs like Sprint and Presto. It describes applications of DWS at companies like Cisco and the development of the THRIS and HiSAFE testing environments. Most recently, DWS has been incorporated into the Spicy SWAN hybrid simulation platform to provide circuit simulation capabilities. Over 500 person-years have been spent developing DWS and its applications for electronic design.
This brochure describes SPRINT, a general purpose circuit simulator developed by Piero Belforte in the late 1980s that was remarkably fast for its time. Belforte notes that SPRINT's simulation speed on workstations from that era would be around 10,000 times slower on modern personal computers, consistent with Moore's Law. Belforte also created the applications presented in the brochure using SPRINT. He later developed Digital Wave Simulator (DWS) based on SPRINT's algorithms to achieve even greater speed performance.
The document details the history of Digital Wave Simulator (DWS), a digital wave analysis simulation software developed by Piero Belforte beginning in the 1970s. It describes how DWS originated from Belforte's work using digital wave algorithms for electrical simulation. Belforte later founded HDT to develop DWS into a general purpose simulator called SPRINT. HDT also created PRESTO for post-layout simulation and collaborated with CSELT to develop THRIS, a hardware qualification tool that became an Italian telecom standard. After HDT closed, Belforte continued independent DWS development through his company SWAN. The document provides links to additional information, applications, publications and the manhours estimated to have been spent
We were pioneers: early applications of dwn simulations_2Piero Belforte
The early applications (1970s) of a revolutionary electrical circuit simulation method (DWN) are presented including device modelling and signal integrity driven design of high speed digital modules. These modules were utilized to develop the prototypes of digital switching systems deployed in Italian Telecom network in the 1970s.
Lsi Switching Networks (World Telecom Forum Geneva 1983)Piero Belforte
A new generation of LSI-based digital switching networks is presented. Thei application can cover
all practical needs for telecom exhanges from PABX to toll applications.
This document appears to be a set of slides from June 1995 authored by Piero Belforte. The slides are unlabeled and consist of the repeated text "Piero Belforte June 1995" across 20 pages, suggesting it is an incomplete or placeholder set of slides.
The document discusses various fault insertion trials and electromagnetic compatibility tests that were conducted on electronic boards and systems. This includes fault insertion studies on digital exchanges, ATM switches, optical modules, and other complex boards. Tests such as TDR analysis, emission mapping, spectrum analysis, and near field analysis were performed in laboratories to evaluate signal integrity and predict effects of faults. People and equipment involved in the tests are also mentioned, along with applications of fault insertion and modeling techniques.
Characterization And Modeling Of 1 Gbs Mcm Ieee Transactions On Computers Jun...Piero Belforte
The document lists the authors P. Belforte, F. Maggioni, and J. Torres and notes they published in the IEEE Transactions on Computers journal in June 1993, but does not provide any other context or summarized content.
This flyer promotes THRIS (The Human Rights Information System), an online database created by Piero Belforte containing information on human rights treaties and reporting procedures. The database provides details on core international human rights instruments, reporting calendars and guidelines, concluding observations and comments on country reports. Users can search for country reports and individual communications considered by UN treaty bodies.
The SWAN project is aimed to superfast circuit simulation for multigigabit applications without the issues of conventional simulators (Spice and similar).
The logo of the SWAN PROJECT created by Piero Belforte (head of the Project) is shown.
Prediction of Pcb Radiated Emissions (Emc Symposium Zurich 1998)Piero Belforte
The paper shows the experimental validation of predictive results of radiated emissions of a multilayer pcb. The radiated field is calculated from simulated results of pcb signals obtained from DWN analysis of interconnects.
Simulation of Lossy Interconnections using Digital Wave Network (Iscas 1982,...Piero Belforte
This paper presents an early extension of the DWN method to the simulation of lossy interconnections between digital devices and systems. Several actual applications are reported with comparison to measures.
MIXED MODE SIMULATION OF HIGH SPEED BOARDS USING DWSPiero Belforte
An example of how DWS can deal with mixed mode (electrical,timing, logic) is shown in this paper. The clock frequency limits due to layout an timing issues can be determined by simulation and an optimization of max frequency of operation can be performed by simulation.
New Method For Electrical Simulation Using Digital Wave Filters(It, Alta Freq...Piero Belforte
A revolutionary method for very fast and accurate cicuit simulation is presented.
The method is based on building up an equivalent DSP representation of the circuit
using wave variables (DWN, Digital Wave Network).
Early Signal Integrity applications including TDR-based modeling of high-speed digital devices are presented.
Biased Reflectometry (International Zurich Congress On Emc September 2007)Piero Belforte
A method for building up signal/power integrity models of active devices is presented in this papaper. The method is based on TDR measures taken at varying operating points of the device.
Best Competitive Marble Pricing in Dubai - ☎ 9928909666Stone Art Hub
Stone Art Hub offers the best competitive Marble Pricing in Dubai, ensuring affordability without compromising quality. With a wide range of exquisite marble options to choose from, you can enhance your spaces with elegance and sophistication. For inquiries or orders, contact us at ☎ 9928909666. Experience luxury at unbeatable prices.
Profiles of Iconic Fashion Personalities.pdfTTop Threads
The fashion industry is dynamic and ever-changing, continuously sculpted by trailblazing visionaries who challenge norms and redefine beauty. This document delves into the profiles of some of the most iconic fashion personalities whose impact has left a lasting impression on the industry. From timeless designers to modern-day influencers, each individual has uniquely woven their thread into the rich fabric of fashion history, contributing to its ongoing evolution.
Satta matka fixx jodi panna all market dpboss matka guessing fixx panna jodi kalyan and all market game liss cover now 420 matka office mumbai maharashtra india fixx jodi panna
Call me 9040963354
WhatsApp 9040963354
❼❷⓿❺❻❷❽❷❼❽ Dpboss Matka Result Satta Matka Guessing Satta Fix jodi Kalyan Final ank Satta Matka Dpbos Final ank Satta Matta Matka 143 Kalyan Matka Guessing Final Matka Final ank Today Matka 420 Satta Batta Satta 143 Kalyan Chart Main Bazar Chart vip Matka Guessing Dpboss 143 Guessing Kalyan night
Tired of chasing down expiring contracts and drowning in paperwork? Mastering contract management can significantly enhance your business efficiency and productivity. This guide unveils expert secrets to streamline your contract management process. Learn how to save time, minimize risk, and achieve effortless contract management.
𝐔𝐧𝐯𝐞𝐢𝐥 𝐭𝐡𝐞 𝐅𝐮𝐭𝐮𝐫𝐞 𝐨𝐟 𝐄𝐧𝐞𝐫𝐠𝐲 𝐄𝐟𝐟𝐢𝐜𝐢𝐞𝐧𝐜𝐲 𝐰𝐢𝐭𝐡 𝐍𝐄𝐖𝐍𝐓𝐈𝐃𝐄’𝐬 𝐋𝐚𝐭𝐞𝐬𝐭 𝐎𝐟𝐟𝐞𝐫𝐢𝐧𝐠𝐬
Explore the details in our newly released product manual, which showcases NEWNTIDE's advanced heat pump technologies. Delve into our energy-efficient and eco-friendly solutions tailored for diverse global markets.
Ellen Burstyn: From Detroit Dreamer to Hollywood Legend | CIO Women MagazineCIOWomenMagazine
In this article, we will dive into the extraordinary life of Ellen Burstyn, where the curtains rise on a story that's far more attractive than any script.
Discover the Beauty and Functionality of The Expert Remodeling Serviceobriengroupinc04
Unlock your kitchen's true potential with expert remodeling services from O'Brien Group Inc. Transform your space into a functional, modern, and luxurious haven with their experienced professionals. From layout reconfiguration to high-end upgrades, they deliver stunning results tailored to your style and needs. Visit obriengroupinc.com to elevate your kitchen's beauty and functionality today.
SATTA MATKA DPBOSS KALYAN MATKA RESULTS KALYAN CHART KALYAN MATKA MATKA RESULT KALYAN MATKA TIPS SATTA MATKA MATKA COM MATKA PANA JODI TODAY BATTA SATKA MATKA PATTI JODI NUMBER MATKA RESULTS MATKA CHART MATKA JODI SATTA COM INDIA SATTA MATKA MATKA TIPS MATKA WAPKA ALL MATKA RESULT LIVE ONLINE MATKA RESULT KALYAN MATKA RESULT DPBOSS MATKA 143 MAIN MATKA KALYAN MATKA RESULTS KALYAN CHART INDIA MATKA KALYAN SATTA MATKA 420 INDIAN MATKA SATTA KING MATKA FIX JODI FIX FIX FIX SATTA NAMBAR MATKA INDIA SATTA BATTA
AI Transformation Playbook: Thinking AI-First for Your BusinessArijit Dutta
I dive into how businesses can stay competitive by integrating AI into their core processes. From identifying the right approach to building collaborative teams and recognizing common pitfalls, this guide has got you covered. AI transformation is a journey, and this playbook is here to help you navigate it successfully.
[To download this presentation, visit:
https://www.oeconsulting.com.sg/training-presentations]
This PowerPoint compilation offers a comprehensive overview of 20 leading innovation management frameworks and methodologies, selected for their broad applicability across various industries and organizational contexts. These frameworks are valuable resources for a wide range of users, including business professionals, educators, and consultants.
Each framework is presented with visually engaging diagrams and templates, ensuring the content is both informative and appealing. While this compilation is thorough, please note that the slides are intended as supplementary resources and may not be sufficient for standalone instructional purposes.
This compilation is ideal for anyone looking to enhance their understanding of innovation management and drive meaningful change within their organization. Whether you aim to improve product development processes, enhance customer experiences, or drive digital transformation, these frameworks offer valuable insights and tools to help you achieve your goals.
INCLUDED FRAMEWORKS/MODELS:
1. Stanford’s Design Thinking
2. IDEO’s Human-Centered Design
3. Strategyzer’s Business Model Innovation
4. Lean Startup Methodology
5. Agile Innovation Framework
6. Doblin’s Ten Types of Innovation
7. McKinsey’s Three Horizons of Growth
8. Customer Journey Map
9. Christensen’s Disruptive Innovation Theory
10. Blue Ocean Strategy
11. Strategyn’s Jobs-To-Be-Done (JTBD) Framework with Job Map
12. Design Sprint Framework
13. The Double Diamond
14. Lean Six Sigma DMAIC
15. TRIZ Problem-Solving Framework
16. Edward de Bono’s Six Thinking Hats
17. Stage-Gate Model
18. Toyota’s Six Steps of Kaizen
19. Microsoft’s Digital Transformation Framework
20. Design for Six Sigma (DFSS)
To download this presentation, visit:
https://www.oeconsulting.com.sg/training-presentations
SATTA MATKA DPBOSS KALYAN MATKA RESULTS KALYAN CHART KALYAN MATKA MATKA RESULT KALYAN MATKA TIPS SATTA MATKA MATKA COM MATKA PANA JODI TODAY BATTA SATKA MATKA PATTI JODI NUMBER MATKA RESULTS MATKA CHART MATKA JODI SATTA COM INDIA SATTA MATKA MATKA TIPS MATKA WAPKA ALL MATKA RESULT LIVE ONLINE MATKA RESULT KALYAN MATKA RESULT DPBOSS MATKA 143 MAIN MATKA KALYAN MATKA RESULTS KALYAN CHART
Virtual Leadership and the managing workIruniUshara1
Virtual leadership is a form of leadership in which teams are managed via a remote working environment.
Like traditional leadership roles, virtual leaders focus on motivating employees and helping teams accomplish their goals.
Virtual leadership focuses heavily on improving collaboration through communication, accountability, and transparency
Efficient PHP Development Solutions for Dynamic Web ApplicationsHarwinder Singh
Unlock the full potential of your web projects with our expert PHP development solutions. From robust backend systems to dynamic front-end interfaces, we deliver scalable, secure, and high-performance applications tailored to your needs. Trust our skilled team to transform your ideas into reality with custom PHP programming, ensuring seamless functionality and a superior user experience.
Prescriptive analytics BA4206 Anna University PPTFreelance
Business analysis - Prescriptive analytics Introduction to Prescriptive analytics
Prescriptive Modeling
Non Linear Optimization
Demonstrating Business Performance Improvement
3. Introduction
The purpose of this document is to compare
measurements and circuit simulations of input (S11) and
output (S21) waveforms in time domain of a lossy line.
The line under investigation is an 1.83-m RG58 coaxial
cable.
It is shown the validity and limit of the model RL-TL [1],
[2], [3] used for simulations by using two commercial
circuit simulators: Spicy Swan (DWS) [4] and MC10
(SPICE) [5]
Results computed by Cable Studio 2013 using 2D-TL
model of CST 2013 [6] are also reported.
6. Detail of SD24 head and cable connection fixture
Cable connection to SD24 ports is achieved by means of two 60mm long
SMA semirigid cables soldered to a reference ground plane (FR4 pcb).
Cables under test inner conductors are connected together by means of
short soldered splices.
6
7. S11/S22 (measure)
Heavy distributed impedance discontinuities (up to more than 50mrho pp) are
pointed out by the measurement.
The cable is not symmetrical (S11 not equal to S22) due to these discontinuities
7
10. OPTIMIZED SETUP MODEL(1) : Spicy SWAN schematic
This model utilizes an ERFC approximation of TDR waveform taking into
account SMA fixture effects.
Connection splices are modeled by two equal TL (TSOLD1,TSOLD2).
RG58 CU cable is modeled as a cascade of 366 X 5cm RL-TL cell.
10
11. SETUP DISCONTINUITIES (soldered splices between semirigid fixture )
can be used as TIME MARKERS.
Comparing the measured S11 (red) to the simulated one (blue) the exact
matching of marker position is achieved adjusting the value of TD of
elementary RL_TL cell of the model. A slight reduction from nominal 25.3ps
to 24.75ps was needed for perfect match
11
12. FIRST SPLICE MODEL OPTIMIZATION
Z0 and Td of TL model of the splice (TSOLD1) are optimized to match
the first peak of actual measure . The same parameters are assigned to
the second splice (TSOLD2)
12
13. Actual SD24 TDR HEAD (CSA 803) waveform
The following is the actual waveform generated by Ch1 and observed on Ch2. The
connection is made using a wideband 40cm SMA cable. In this way the step
dispersion due to the fixture of RG58 cable is taken into account.
The resulting risetime is 22.5ps between 20% and 80%, while the observed risetime
at Ch1 (generator) is 17ps.
13
14. Normalized TDR waveform (0-2rho)
This is 19-breakpoints PWL approximation of the previous SD24 waveform.
The step amplitude has been normalized between 0 and 2rho for utilization
in the simulative DWS model (model 2)
14
15. OPTIMIZED SETUP MODEL(2)
This is the Spicy SWAN schematic of the simulative model (2) using the pwl
approximation of TDR step generator (VTDR).
Splice models parameters are optimized ,and the RG58 elementary RL-TL
cell delay is optimized as well. The sim time step has been chosen to be 1/10
of elementary cell delay (Tstep=2.475ps) to minimize overall delay errors.
15
17. Spicy SWAN (DWS) results of model (2)
The following are the plots of simulated S11 and S22 of previous setup.
This sim requires about 30s with about 20K points and 28K model elements.
17
18. The following slides show the differences between
measured and simulated waveforms including setup
effects.
18
19. The RL-TL cell model is practically symmetrical, while the actual cable is
not.
Actual cable S11/S22 values are under-estimated with respect model values due
to distributed impedance discontinuities.
Overall behavior after first reflection shows good agreement between model and
meaure
19
23. S21 edge comparison (model1)
In this slide the absolute delays are taken into account (Splice markers matched)
Measured 20%-80% risetime : 80ps vs 70ps of model. The measured waveform has a
slower foot but a faster edge in the upper part. This is due probably to dielectric losses
(slower foot). The faster upper part can be due to stranded conductors of the actual cable,
23
S21:measure
S21:model
24. S21 edge comparison (model2)
24
In this slide the splice markers are NOT exactly matched to superimpose the
waveforms.
The measured risetime is identical to that of the model (80ps), but the shape
differences of model 1 are confirmed: slower measured waveform foot and
faster upper portion of measured edges
Measure
Model
25. 25
measure
RL-TL model
5 Gbit/sec
10 Gbit/sec
WCED: Worst Case Eye Diagrams (from DWV: Digital Wave Viewer) :
YELLOW : 5Gbit/sec, RED: 10Gbit/sec
EYE CLOSURE and ISI JITTER are slightly higher in the measure due to
dielectric losses not taken into account in the model
EYE shapes are more symmetrical in the measure: this can be also due to
dielectric losses not taken into account in the model
26. 26
Removing Splices from the simulative model, the simulated eye diagram
gets more open and less similar to the eye calculated from actual measure
(including splice effects). The dielectric loss effect (not considered in the
model) symmetrizes the eye diagram.
28. Comments on Measurements & DWS simulations
The used setup is effective for a 1.83m long cable characterization
The TDR incident pulse rise time (22ps) is fast enough to achieve good waveform
resolution (80ps rise time at cable’s output)
Actual cable shows sensible impedance discontinuities (S11)
Actual cable is asymmetrical
Theoretical cable delay is slightly overestimated
RL-TL model gives good S11 estimate (without discontinuities)
S21 edge risetime agreement is good (70-80ps)
Dielectric losses have to be added to achieve better S21 waveform match (edge
foot too fast in the sim model)
Skin effect losses are probably over-estimated (upper S21 edge too slow)
EYE CLOSURE and ISI JITTER (5-10Gbit/sec) slightly higher in the measure due to
dielectric losses not taken into account in the model
DWS is very effective in terms of accuracy and sim times (at least 50X faster than
MC10)
BTM S-parameters modeling, supported by DWS, can take into account effects like
distributed discontinuities and asymmetries of actual cable with a further speed-
up factor of 10X to 50X (more than 3 orders of magnitude faster than MC10)
MC10 shows accuracy problems in simulating RL-TL circuits [9]
28
29.
30. MC10 simulation features
MC10 uses the model RL-TL of [1, section 7.2.1]
The RL network is the result of vector fitting
technique applied to Eq. 7.59 of [1] that are the same
of Eq. V.18 of [7].
32. Z0coax=49.95
TDcoax=25.293ps (no
delay adaptation with
measurements)
This circuit was obtained from Eq. 7.57 of [1] by
vector fitting technique adopting 10 poles.
The model is valid up to 10 GHz, see Fig. 7.21 of [1]
35. Good agreement
with DWS results
Measured
MC10
Measured
MC10
MC10 delay is
modified for
comparison with
DWS waveform
(see slide 23)
ns
ns
Volt
Volt
36. Comments on Measure & MC10 simulations
In this situation MC10 simulations are in good
agreement with DWS simulations nevertheless the
delay of the unit cell were not optimized to
measurements and despite MC10 issues with RL-TL
circuits [9].
To achieve good accuracy, it is very important to use
at least a maximum step time of 1ps or a fixed time
step of 2.53ps=1/10 of unit cell delay.
37.
38. CS simulation features
Cable Studio 2013 takes into account both skin and proximity
effect at the same time while CS 2012 considers skin effect only.
The source is the PWL approximation of actual TDR waveform
(rise time tr=22.5ps, 20% and 80%) as used for DWS sims.
A cable model valid up to 10,000 MHz (instead of 40,000 MHz
as should be required by the input risetime) is used for saving
simulation time.
A fixed time step=2.5ps is used.
Dielectric losses has tanδ=0.8m (8e-4) at 100MHz, default value
in CST.
Setup impedance discontinuities are considered.
39. Permittivity εr=2.3
Tanδ = 0.8x10-3
at 100MHz
Fixed time step=2.5ps
1+S11
S21
Source
with
TDR
input file
40. ns
Measured CS with (dadot) and without
(dash) dielectric losses
Volt
•Loss effect is under estimated
•There is an offset of about 0.005
41. •Loss effect is under estimated
•There is an offset of about 0.005
Measured
CS with (dadot) and without
(dash) dielectric losses
ns
Volt
42. •Measure (solid)
•CS with (dadot) and
without (dash) dielectric
losses
MC10 delay
modified for
comparison with
DWS waveform
Losses are slightly
under estimated also
with tanδ=0.8m
Dielectric losses introduce a
delay of 0.4ns
ns
Volt
ns
Volt
43. •Measure (solid)
•CS with (dadot) and
without (dash) dielectric
losses
CS delay is modified for
comparison with DWS
waveform (see slide 23)
S21 is in good
agreement with the
measurement when
tanδ=0.8m is used
Dielectric losses introduce a
delay of 10ps (anticipation)
ns
Volt
ns
Volt
44. Comments on Measure & cs simulations
CS provides the expected wave shapes of the S parameters in time
domain.
It is very important to use the option: “allow modal models” in
“2D (TL) modeling settings” to avoid fast oscillations on the front
of S21.
For accurate results, the circuit should run with a fixed time step
(in this case 2.5ps)
For better results, the cable model should be valid up to 40,000
MHz instead of 10,000.
CS under estimates S11 also with ohmic and dielectric losses
(tanδ=0.8m) while S21 is in good agreement with measurements.
Better results are obtained with cs2013, that takes into account
proximity effect also, than cs2012
45.
46. MC10 models
This section is divided into two parts:
1. The model RL-TL as described previously for MC10
& DWS sims is compared with CS
2. The analytic model as described in [1, 7.2.1.1] with a
correction factor of ½ and using the exact
transmission line model for computing s parameters
as reported in[1, 11.2.3] is compared with CS and
MWS.
47. Part1: CST simulation features
The frequency range considered is: 0-10 GHz
MWS and Cable Studio (CS) S parameters are computed
by CST 2013 if not specified
Normal accuracy is used for 2D modeling of CS
Meshcells=71,944 computed by adaptive mesh refinement
are used for MWS
51. Part 1: Comments on S parameters
Making reference to [2], [3], we have:
DWS, MC10, CS models consider a solid shield while the actual RG58
cable has a braided shield.
S11 with ohmic losses only: CS 2010 & 2013 no modal show coincident
waveforms; CS modal provides lower valued waveform; MC10 and
MWS are lower also and are very similar with slight higher resonances
for MWS when the frequency increases.
S11 computed by CS with different types of losses are practically the
same.
S21 with ohmic losses only: MWS, CS (no modal), CS (modal) compute
the same attenuation; Higher attenuation is computed by CS 2010 (no
modal) and close to MC10 as previously verified.
S21 computed by CS with dielectric losses (tanδ=0.8m) provides an
attenuation of 0.023 dB close to the nominal 0.026 dB at 1 GHz
reported in the data sheet of the RG58.
S21 computed by CS (ohmic+diel) is slight lower than MC10 up to 7
GHz.
52. Part2: MC10,CST, MWS simulation features
The circuit for computing S parameters is the same of [1, 11.2.3,
pag. 421].
The cable is simulated by exact TL equations by using the per-
unit-line parameters Zpuls and Ypuls.
Eq. for the case of a round wire above a ground plane are used
for Zi(ω) of Zpuls=Zi(ω)+j ωLo instead Eq. of a coaxial wire.
The two types of Equations differs for a factor ½.
Eq.7.28 of [1, pag.174]) is used for Ypuls=ωCotanδ +jωCo
MWS considers both ohmic and dielectric losses
It is used a tanδ=0.8m for all frequencies
53. Zi(f) Exact eq. for a
round wire [1, Eq.7.8a]
rDC dc value fpr for a
round wire [1, Eq.7.6]
Zif(f) approximate eq.
for a round wire [1,
Eq.7.15], type 1
Ziwcoax(f) approximate
eq. for a round wire [7,
Eq.V.13], type 2
Ziwcoaxt(f)
approximate eq. for a
coaxial wire [7,
Eq.V.18] and [1, 7.59]
•Exact and approximate equations (Types 1&2)
for a round wire are in good agreement over
0.3MHz.
•Approximate equation for a coaxial wire used for
RL-TL model overestimates the losses over
0.03MHz.
Ω
MHz
54. •Cable studio: solid line with ohmic, dielectric (do), ohmic+dielectric (d)
•MC10: dashed line with ohmic, dielectric (do), ohmic+dielectric (d)
•MWS: dash-dot line
CS provides
higher S11
parameters
55. •Cable studio: solid line
•MC10: dashed line
•MWS: dash-dot line
Dielectric
Ohmic
Ohmic+dielectric
MHz
Very good agreement among the
different methods can be noted
56. Part 2: Comments on S parameters
When using expression for a coaxial wire cable that
differs from round wire by a factor ½, the ohmic
losses are overestimated.
S11: Cable Sudio computes parameters for every type
of losses about 20 dB higher than those given by MC10
using the analytic expressions for a round wire.
S21: Cable Sudio computes parameters for every type
of losses in good agreement with those given by MC10
using the analytic expressions for a round wire.
S11&S21: MWS computes parameters in good
agreement with MC10 using the analytic expressions
for a round wire.
57. Conclusions
For accurate circuit simulations of S-parameter cable in time domain,
the discontinuities introduced by the setup should be considered.
RL-TL model: it seems it overestimates ohmic losses and therefore in
part takes into account the dielectric loss effect. To be verified
considering the actual dielectric losses of the coaxial cable.
RL-TL model: it is valid up to 10 GHz in Spicy Swan (DWS) or MC10
and provides waveforms close to the measurements if a constant time
step equal at least 1/10 of the unit cell delay is used.
RL-TL model: S11 is under estimated in the time interval equal twice
the cable delay because the model does not take into account
discontinuity and dissymmetry along the cable.
RL-TL model: S21 front is slight faster than measurement up to 0.4 of
its maximum value because the model does not take into account the
dielectric losses.
Cable studio (frequency domain): S11 is overestimated (about 20dB)
while S21 is in good agreement with those computed by MC10 by using
exact analytic expressions for lossy round wire for all types of losses.
Cable studio (time domain): S11 is underestimated for all the time
interval while S21 is estimated well with ohmic and dielectric losses
(tanδ=0.8m), and fixed time step=2.5ps.
58. References
[1] S. Caniggia, Francesca Maradei, “Signal Integrity and
Radiated Emission”, John Wiley & Sons, 2008
[2] P. Belforte, S. Caniggia, “CST coaxial cable models for SI
simulations: a comparative study”, March 24th 2013
[3] P. Belforte, S. Caniggia,, “Measurements and Simulations
with 1.83-m RG58 cable”, April 5th 2013
[4] Spicy SWAN : www.ischematics.com
[5] MC10: www.spectrum-soft.com
[6] Cable and Micro Wave Studio: www.cst.com
[7] M. D’Amore, “Compatibiltà Elettromagnetica”, Siderea,
2003 (in Italian)
[8] P. Belforte DWS versus Microcap 10: 10 RL-TL cell cascade
comparative benchmark
[9]
http://www.slideshare.net/PieroBelforte1/2013-pb-dws-vs-micro