2015 course SPPU SEIT syllabus of subject Processor Architecture and Interfacing (PAI) This covers special function registers used for serial communication in 8051, Operating modes of serial communication, doubling baud rate in 8051
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2015 course SPPU SEIT syllabus of subject Processor Architecture and Interfacing (PAI) This covers the basics of serial communication, Data framing and Baud Rate in 8051 microcontroller.
International Journal of Engineering Research and Applications (IJERA) aims to cover the latest outstanding developments in the field of all Engineering Technologies & science.
International Journal of Engineering Research and Applications (IJERA) is a team of researchers not publication services or private publications running the journals for monetary benefits, we are association of scientists and academia who focus only on supporting authors who want to publish their work. The articles published in our journal can be accessed online, all the articles will be archived for real time access.
Our journal system primarily aims to bring out the research talent and the works done by sciaentists, academia, engineers, practitioners, scholars, post graduate students of engineering and science. This journal aims to cover the scientific research in a broader sense and not publishing a niche area of research facilitating researchers from various verticals to publish their papers. It is also aimed to provide a platform for the researchers to publish in a shorter of time, enabling them to continue further All articles published are freely available to scientific researchers in the Government agencies,educators and the general public. We are taking serious efforts to promote our journal across the globe in various ways, we are sure that our journal will act as a scientific platform for all researchers to publish their works online.
SE PAI Unit 5_Serial Port Programming in 8051 microcontroller_Part 1KanchanPatil34
2015 course SPPU SEIT syllabus of subject Processor Architecture and Interfacing (PAI) This covers the basics of serial communication, Data framing and Baud Rate in 8051 microcontroller.
International Journal of Engineering Research and Applications (IJERA) aims to cover the latest outstanding developments in the field of all Engineering Technologies & science.
International Journal of Engineering Research and Applications (IJERA) is a team of researchers not publication services or private publications running the journals for monetary benefits, we are association of scientists and academia who focus only on supporting authors who want to publish their work. The articles published in our journal can be accessed online, all the articles will be archived for real time access.
Our journal system primarily aims to bring out the research talent and the works done by sciaentists, academia, engineers, practitioners, scholars, post graduate students of engineering and science. This journal aims to cover the scientific research in a broader sense and not publishing a niche area of research facilitating researchers from various verticals to publish their papers. It is also aimed to provide a platform for the researchers to publish in a shorter of time, enabling them to continue further All articles published are freely available to scientific researchers in the Government agencies,educators and the general public. We are taking serious efforts to promote our journal across the globe in various ways, we are sure that our journal will act as a scientific platform for all researchers to publish their works online.
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Dynamic equalization training is a unique capability in modern day serial data communication. Through optimization of transmitter and receiver equalization parameters we can push the limits of serial data rates. Troubleshooting dynamic equalization problems at the Physical and Protocol layers requires testing for proper functionality and compliance.
Join Teledyne LeCroy's Stephen Mueller for this webinar to understand how to address this measurement challenge. The presentation will include real measurement examples and debugging techniques to pinpoint problems in the physical and protocol layers.
At multigigabit per second data rates and with channel flight times longer than a bit period, signal integrity is a major concern. Under these conditions, high-speed analog effects, previously only seen in high frequency RF and microwave engineering, can impair the signal quality and degrade the bit error rate of the link. This hands-on workshop will show you how use Advanced Design System (ADS) to dramatically reduced product design cycles by resolving these issues early in the design cycle. Using PCI Express serial link as an example, we’ll illustrate how you can: Analyze complete serial links by co-simulating individual components, each at its most appropriate level of abstraction: link-, circuit- or physical-level. Import S-parameter backplane and interconnect models accurately into transient (SPICE) simulations. Perform jitter diagnosis with the proven EZJIT Plus algorithm used in Agilent instruments.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
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FSK Demodulator, one of the applications of PLL has been implemented using both hardware and software. Results are found to be similar and based on these results it is believed that this will contribute for the improvement in performance and reliability for future communication systems. Hence this will also contribute to the development of higher reliability of the systems.
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WiMAX ("Worldwide Interoperability for Microwave Access") technology is developed to meet the
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modulation technique used in IEEE 802.16d (fixed WiMAX) communication standard. OFDM is used to
increase data rate of wireless medium with higher spectral efficiency. The proposed work is to evaluate
performance of IEEE Std 802.16d transceiver in MATLAB R2009b simulink environment. System performance
evaluated using BER vs SNR for different modulation technique such as 4 QAM, 16 QAM, 64 QAM under
different channel condition
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Implementation of Universal Asynchronous Receiver and TransmitterIJERA Editor
Universal Asynchronous Receiver Transmitter (UART) is the serial communication protocol that is used for data exchange between computer & peripherals. UART is a low velocity, short-distance, low-cost protocol. UART includes three modules which are received, the baud rate generator and transmitter. The UART design with Very High Description Language can be integrated into the Field Programmable Gate Array to achieve stable data transmission and to make system reliable and compact. In the result and simulation part, this project will focus on check the receive data with error free & baud rate generation at different frequencies. Before synthesizing of UART a baud rate generator is incorporated into the system. We use the frequency divider which sets itself to required frequency for the functionality at lower frequency. All modules are designed using VERILOG and implemented on Xilinx Suite development board.
October 8, 2014 Webcast Identifying PCI Express 3.0 Dynamic Equalization Problems
Dynamic equalization training is a unique capability in modern day serial data communication. Through optimization of transmitter and receiver equalization parameters we can push the limits of serial data rates. Troubleshooting dynamic equalization problems at the Physical and Protocol layers requires testing for proper functionality and compliance.
Join Teledyne LeCroy's Stephen Mueller for this webinar to understand how to address this measurement challenge. The presentation will include real measurement examples and debugging techniques to pinpoint problems in the physical and protocol layers.
At multigigabit per second data rates and with channel flight times longer than a bit period, signal integrity is a major concern. Under these conditions, high-speed analog effects, previously only seen in high frequency RF and microwave engineering, can impair the signal quality and degrade the bit error rate of the link. This hands-on workshop will show you how use Advanced Design System (ADS) to dramatically reduced product design cycles by resolving these issues early in the design cycle. Using PCI Express serial link as an example, we’ll illustrate how you can: Analyze complete serial links by co-simulating individual components, each at its most appropriate level of abstraction: link-, circuit- or physical-level. Import S-parameter backplane and interconnect models accurately into transient (SPICE) simulations. Perform jitter diagnosis with the proven EZJIT Plus algorithm used in Agilent instruments.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
4 ijaems nov-2015-4-fsk demodulator- case study of pll applicationINFOGAIN PUBLICATION
FSK Demodulator, one of the applications of PLL has been implemented using both hardware and software. Results are found to be similar and based on these results it is believed that this will contribute for the improvement in performance and reliability for future communication systems. Hence this will also contribute to the development of higher reliability of the systems.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Complex digital and analog circuits and multiple clock signals used for design and development of modern systems usually make the job of engineers and designers a tedious one. While working with complex circuits and signals, a designer might encounter problems with circuit validation due to long simulation time. These complexities adversely affect the development time and hence increase time to market incurring higher production costs. By applying a new methodology in their Digital Phase-Locked Loop (Digital PLL) design, the engineers at QuEST reduced the simulation effort to one-by-third.
Performance Evaluation of IEEE STD 802.16d TransceiverIOSR Journals
WiMAX ("Worldwide Interoperability for Microwave Access") technology is developed to meet the
growing demand of increased data rate and accessing the internet at high speeds. 802.16 family of standards is
officially called Wireless MAN in IEEE. Orthogonal frequency division multiplexing (OFDM) is multicarrier
modulation technique used in IEEE 802.16d (fixed WiMAX) communication standard. OFDM is used to
increase data rate of wireless medium with higher spectral efficiency. The proposed work is to evaluate
performance of IEEE Std 802.16d transceiver in MATLAB R2009b simulink environment. System performance
evaluated using BER vs SNR for different modulation technique such as 4 QAM, 16 QAM, 64 QAM under
different channel condition
Design And Simulation of Modulation Schemes used for FPGA Based Software Defi...Sucharita Saha
Design of a BPSK and QPSK digital Modulation scheme and its implementation on FPGAs for universal mobile telecommunications system and SDR applications. The simulation of the system is made in MATLAB Simulink environment and System Generator, a tool used for FPGA design. Hardware Co-Simulation is designed using VHDL a hardware description language targeting a Xilinx FPGA and is verified using MATLAB Simulink. It is then converted to VHDL level using Simulink HDL coder. The design is synthesized and fitted with Xilinx 14.2 ISE Edition software, and downloaded to Spartan 3E (XC3S500E) board.
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SE PAI Unit 5_Serial Port Programming in 8051 microcontroller_Part 2
1. 1
Unit 5: 8051 Serial Port Programming
Part 2
Subject: Processor Architecture & Interfacing
(SPPU, Pune 2015 Course of Information Technology)
Class: SEIT Semester: II
Prepared By,
Ms. K. D. Patil, Assistant Professor
Department of Information Technology
(NBA accredited)
Sanjivani College of Engineering, Kopargaon-423603.
Maharashtra, India.
(An Autonomous Institute, Affiliated with SPPU, Pune.)
NAAC ‘A’ Grade Accredited, ISO 9001:2015 certified
2. Contents
Prepared By: Ms. K. D. Patil, Dept. of Information Technology, Sanjivani
COE, Kopargaon
2
Part 1
Basics of Communication
Serial Vs Parallel communication
Synchronous Vs Asynchronous communication
Data Framing in Asynchronous Serial Communication
Baud Rate
Part 2
Special Function Registers
Operating modes of Serial Communication
Doubling Baud Rate in 8051
Part 3
Importance of TI Flag
Importance of RI Flag
Examples
3. Special Function Registers
Prepared By: Ms. K. D. Patil, Dept. of Information Technology, Sanjivani
COE, Kopargaon
3
SBUF (Serial Buffer) Register
Byte addressable
SCON (Serial Control) Register
Bit addressable
PCON (Power Control) Register
Byte addressable
4. SBUF (Serial Buffer) Register
Prepared By: Ms. K. D. Patil, Dept. of Information Technology, Sanjivani
COE, Kopargaon
4
Byte Addressable
SBUF is an 8-bit register used solely for serial communication
For a byte data to be transferred via the TxD line, it must be placed in the
SBUF register
The moment a byte is written into SBUF, it is framed with the start and stop
bits and transferred serially via the TxD line
SBUF holds the byte of data when it is received by 8051 RxD line
When the bits are received serially via RxD, the 8051 de-frames it by
eliminating the stop and start bits, making a byte out of the data received,
and then placing it in SBUF
Example:
MOV SBUF, # ’B’ ; load SBUF=42, ASCII for ‘B’
MOV SBUF, A ; copy accumulator into SBUF
MOV A, SBUF ; copy SBUF into accumulator
5. SCON (Serial Control) Register
Prepared By: Ms. K. D. Patil, Dept. of Information Technology, Sanjivani
COE, Kopargaon
5
SCON is an 8-bit register used to program the start bit, stop bit, and
data bits of data framing, among other things
Bit addressable
SM0 SM1 SM2 REN TB0 RB0 TI RI
SMO SCON.7 Serial port mode specifier
SM1 SCON.6 Serial port mode specifier
SM2 SCON.5 Used for Multiprocessor Communication
REN SCON.4 Set/cleared by software to enable/disable reception
TB8 SCON.3 Not Widely used
RB8 SCON.2 Not Widely used
TI SCON.1 Transmit interrupt flag. Set by the Hardware at beginning of
stop bit mode 1. Cleared by software
RI SCON.0 Receive interrupt flag. Set by the Hardware halfway through
stop bit mode 1. Cleared by software
6. SCON (Serial Control) Register
Prepared By: Ms. K. D. Patil, Dept. of Information Technology, Sanjivani
COE, Kopargaon
6
SM0 (SCON.7), SM1(SCON.6)
They determine the framing of data by specifying the
number of bits per character, and the start and stop
bits
SM0 SM1 Serial Modes
0 0 Serial Mode 0
0 1 Serial Mode 1, 8 Bit data, 1 stop
Bit, 1 start bit
1 0 Serial Mode 2
1 1 Serial Mode 3
Note: Only mode 1 is of our Interest
7. Serial Modes
Prepared By: Ms. K. D. Patil, Dept. of Information Technology, Sanjivani
COE, Kopargaon
7
Serial Mode 1
Out of 4, only mode 1 is of our interest
Other 3 modes are rarely used
Asynchronous (single character at a time)
Data framing is of 8 bits, 1 stop bit, 1 start bit which
makes it compatible with the COM port of IBM compatible
PCs
Allows baud rate to be variable and is set by Timer 1 of
8051
For each character, a total of 10 bits are transferred
where, First bit is start bit, followed by 8 data bits, and
finally 1 stop bit
8. Serial Modes
Prepared By: Ms. K. D. Patil, Dept. of Information Technology, Sanjivani
COE, Kopargaon
8
Serial Mode 0
Synchronous (Transfers block of character at a time)
Data transferred on RxD
Clock on TxD
Clock is fixed at oscillator frequency
Serial Mode 2
Asynchronous (single character at a time)
Data framing is of 11 bits, 1 stop bit, 1 start bit, 8 data bits
(programmable 9 data bits)
On transmission TB8 bit of SCON is 9th Bit
9th Bit may be used for Data or Parity Bit
Baud rate may be 1/32 or 1/64 of oscillator frequency
Serial Mode 3
Same as Serial mode 2 with programmable baud rate
9. SCON (Serial Control) Register
Prepared By: Ms. K. D. Patil, Dept. of Information Technology, Sanjivani
COE, Kopargaon
9
SM2 (SCON.5)
This enables the multiprocessing capability of the 8051
For us, SM2 = 0 as 8051 will not be used in
multiprocessor environment
REN (SCON.4)
receive enable
When REN = 1 (High), it allows 8051 to receive data
on RxD pin
When REN = 0 (low), the receiver is disable
Can be used to block any serial data reception
10. SCON (Serial Control) Register
Prepared By: Ms. K. D. Patil, Dept. of Information Technology, Sanjivani
COE, Kopargaon
10
TB8 (SCON.3)
Transfer Bit
Used for Serial modes 2 and 3
For us, TB8 = 0 as we are using Serial Mode 1 for
programming
RB8 (SCON.2)
receive Bit
Used for Serial modes 2 and 3
In Serial Mode 1, this bit gets the copy of stop Bit when an
8 bit data is received
For us, RB8 = 0
11. SCON (Serial Control) Register
Prepared By: Ms. K. D. Patil, Dept. of Information Technology, Sanjivani
COE, Kopargaon
11
TI (SCON.1)
transmit interrupt
When 8051 finishes the transfer of 8-bit character
It raises TI flag to indicate that it is ready to transfer
another byte
TI bit is raised at the beginning of the stop bit
RI (SCON.0)
When 8051 receives data serially via RxD, it gets rid of
the start and stop bits and places the byte in SBUF register
It raises the RI flag bit to indicate that a byte has been
received and should be picked up before it is lost
RI is raised halfway through the stop bit
12. Doubling Baud Rate in 8051
Prepared By: Ms. K. D. Patil, Dept. of Information Technology, Sanjivani
COE, Kopargaon
12
There are two ways to increase the baud rate of
data transfer
To use a higher frequency crystal
This is not feasible as System crystal is fixed
New Crystal Frequency may not be compatible with IBM PC
serial COM’s port baud rate
To change a bit in the PCON register
13. PCON (Power Control) Register
Prepared By: Ms. K. D. Patil, Dept. of Information Technology, Sanjivani
COE, Kopargaon
13
It is an 8-bit register
Byte addressable
SMOD (Serial mode) bit
used serial communication
When 8051 is powered up, SMOD is zero
We can set it to high by software and the double the baud
rate
SMOD ---- ---- ---- GF1 GF0 PD IDL
D7 D6 D5 D4 D3 D2 D1 D0
14. PCON (Power Control) Register
Prepared By: Ms. K. D. Patil, Dept. of Information Technology, Sanjivani
COE, Kopargaon
14
Following set of sequence can be used to set high D7
of PCON
MOV A,PCON ;place a copy of PCON in ACC
SETB ACC.7 ;make D7=1
MOV PCON,A ;now SMOD=1 without
;changing any other bits
Note: PCON is byte addressable so cannot directly set
bit D7 to high
15. PCON (Power Control) Register
Prepared By: Ms. K. D. Patil, Dept. of Information Technology, Sanjivani
COE, Kopargaon
15
GF1 and GF0 Bits
Both are general purpose flag bits
PD (Power Down) Bit
Setting this bit activates Power down operation
Available only in CMOS
IDL (Idle mode) Bit
Setting this bit activates Idle mode operation
Available only in CMOS
16. Doubling Baud Rate in 8051
Prepared By: Ms. K. D. Patil, Dept. of Information Technology, Sanjivani
COE, Kopargaon
16
Considering, XTAL = 11.0592 MHz
For SMOD = 0
Machine cycle freq. = 11.0592 MHz / 12 = 921.6 kHz
Timer 1 frequency to set Baud Rate = 921.6 kHz / 32 = 28800 Hz
For SMOD = 1
Machine cycle freq. = 11.0592 MHz / 12 = 921.6 kHz
Timer 1 frequency to set Baud Rate = 921.6 kHz / 16 = 57,600 Hz
17. Doubling Baud Rate in 8051
Prepared By: Ms. K. D. Patil, Dept. of Information Technology, Sanjivani
COE, Kopargaon
17
Baud Rate Comparison for SMOD = 0 and SMOD = 1
TH1
(Decimal)
TH1
(Hex)
Baud Rate
(SMOD = 0)
Baud Rate
(SMOD = 1)
-3 FD 9600 19200
-6 FA 4800 9600
-12 F4 2400 4800
-24 E8 1200 2400
18. Reference
Prepared By: Ms. K. D. Patil, Dept. of Information Technology, Sanjivani
COE, Kopargaon
18
“The 8051 Microcontroller and Embedded Systems
using Assembly and C” , Muhammad Ali Mazidi,
Janice Gillispie Mazidi, Rolin D. McKinlay, Second
Edition, Pearson publication
19. Prepared By: Ms. K. D. Patil, Dept. of Information Technology, Sanjivani
COE, Kopargaon
19
