This document provides an overview of CISC and RISC architectures. CISC uses complex instructions that perform multiple low-level operations in one instruction, taking multiple clock cycles to execute. It has few general purpose registers. RISC uses simpler instructions that are executed in one clock cycle. It has many general purpose registers and only load and store instructions can access memory directly. Pipelining allows RISC processors to process multiple instructions simultaneously for improved efficiency compared to CISC which executes instructions sequentially.

1. RISC / CISC
Architecture.

2. Overview
• CISC Architecture
• RISC Architecture
• Pipelining
• RISC vs CISC

3. What is CISC
• Complex Instruction Set Computer
• “High level” Instruction Set
• Executes several “low level
operations”
• Ex: load, arithmetic operation,
memory store

4. Features of CISC
• Instructions can operate directly on memory
• Small number of general purpose registers
• Instructions take multiple clocks to execute
• Few lines of code per operation

5. What is RISC?
• Reduced Instruction Set Computer
• RISC is a CPU design that recognizes only a
limited number of instructions
• Simple instructions
• Instructions are executed quickly

6. Features of RISC
 “Reduced” instruction set
 Executes a series of simple instruction instead of a complex
instruction
• Instructions are executed within one clock cycle
• Incorporates a large number of general registers
for arithmetic operations to avoid storing variables
on a stack in memory
• Only the load and store instructions operate
directly onto memory
• Pipelining = speed

7. Pipelining
• “Assembly Line”
• Technique to process multiple instructions at
the same time
• Allows instructions to be executed efficiently

8. Stages of Pipelining
• Fetch instructions from memory
• Decode the instruction
• Execute the instruction or calculate an
address
• Access an operand in data memory
• Write the result into a register

9. Pipelining Example

10. CISC vs RISC
CISC RISC
Complex instructions require
multiple cycles
Reduced instructions take 1
cycle
Many instructions can
reference memory
Only Load and Store
instructions can reference
memory
Instructions are executed one
at a time
Uses pipelining to execute
instructions
Few general registers Many general registers