An interrupt pauses the normal execution of a microprocessor. When an interrupt occurs, the program counter is saved to the stack and interrupts are disabled. An interrupt acknowledge signal is sent and the service routine address is executed. After servicing, the original program counter is retrieved from the stack and execution resumes. There are hardware and software interrupts. Hardware interrupts come from I/O devices and software from CPU instructions. Interrupts can be maskable/non-maskable, vectored/non-vectored, edge/level-triggered, and have different priorities like the 8085's TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR interrupts.

2. What is an Interrupt?
• It means interrupting the normal
execution of the microprocessor.

3. Steps whenever there is an interrupt?
current
PC PC contents are
stored in stack
100
101
102
103
104
103
103
STACK
SP

4. 4
Interrupts in 8085
Main routine
Interrupt
Save
program
counter
Disable
interrupts
Send out
interupt
acknowledge
Service routine
Go to
service
routine
Get
original
program
counter
Go back
EI
RET

5. HARDWARE INTERRUPT
• It is a special signal from an I/O device
to the computer.

6. SOFTWARE INTERRUPT
• It is generated by a program interrupt
instructions in the CPU.

7. TYPES OF INTERRUPTS
• MASKABLE & NON- MASKABLE INTERRUPTS
• VECTORED & NON-VECTORED INTERRUPTS
• EDGE TRIGGERED & LEVEL TRIGGERED
INTERRUPTS
• PRIORITY BASED INTERRUPTS

8. MASKABLE INTERRUPTS
EXAMPLE:
• RST 7.5
• RST 6.5
• RST 5.5
• INTR
• ONLY TRAP IS A NON MASKABLE INTERRUPT

9. VECTORED INTERRUPTS
EXAMPLE:
• RST 7.5
• RST 6.5
• RST 5.5
• TRAP

10. 8085 Interrupts
8085
TRAP
RST7.5
RST6.5
RST 5.5
INTR
INTA

11. The addresses to which program control goes:
NAME VECTOR
ADDRESSES
RST 7.5 003CH(7.5 X 0008H)
RST 6.5 0034H(6.5 X 0008H)
RST 5.5 002CH(5.5 X 0008H)
TRAP 0024H(4.5 X 0008H)
Absolute address is calculated by multiplying the RST value
with 0008H.

12. NON – VECTORED
INTERRUPT
EXAMPLE:
• INTR is a non vectored interrupt.

13. The 8085 Interrupts
Interrupt
name
Maskable Vectored
INTR Yes No
RST 5.5 Yes Yes
RST 6.5 Yes Yes
RST 7.5 Yes Yes
TRAP No Yes

14. EDGE TRIGGERED
INTERRUPTS
EXAMPLE:
• RST 7.5

15. Edge triggering
Rising edge
Falling edge

16. LEVEL TRIGGERED
INTERRUPT
EXAMPLE:
• RST 6.5
• RST 5.5
• INTR
• TRAP is EDGE & LEVEL triggered interrupt.

17. Level triggering
Low level
High level

18. PRIORITY BASED
INTERRUPTS
INTERRUPT PRIORITY
TRAP 1
RST 7.5 2
RST 6.5 3
RST 5.5 4
INTR 5

19. Five hardware interrupts
are:
• TRAP
• RST 7.5
• RST 6.5
• RST 5.5
• INTR

20. TRAP (PIN-6)
• Non- maskable
• Has highest priority
• Can not disable.
• Edge & level triggered
• Used for power failure & emergency shut off.

21. RST 7.5
• Maskable interrupt.
• Has 2nd highest priority.
• +ve edge triggered only.

22. RST 6.5
• Maskable interrupt.
• 3rd highest priority.
• Level triggered only.

23. RST 5.5
• Maskable interrupt.
• 4th highest priority.
• Level triggered only.

24. INTR
• Maskable interrupt.
• Lowest priority.
• Level triggered.

25. INTA’
• Stands for Interrupt acknowledge.
• Outgoing signal.
• Active low signal.