This document discusses RISC (Reduced Instruction Set Computer) architecture. It provides a brief history of early RISC projects from IBM, Stanford, and UC-Berkeley in the late 1970s and early 1980s. Key characteristics of RISC include simpler instructions that take a single clock cycle to execute, a large number of general purpose registers, and the use of pipelining to allow simultaneous execution of instruction stages. The document concludes that while RISC and CISC designs have converged over time, RISC chips still utilize uniform single-cycle instructions and have a register-to-register load/store architecture with many general purpose registers.

1. MADE BY;
ASHISH LATWAL
CSE/40/18

2. RISC
RISC, or Reduced Instruction Set
Computer. is a type of microprocessor
architecture that utilizes a small, highly-
optimized set of instructions, rather than a
more specialized set of instructions often
found in other types of architectures.

3. HISTORY
The first RISC projects came from IBM, Stanford, and UC-
Berkeley in the late 70s and early 80s. The IBM 801, Stanford
MIPS, and Berkeley RISC 1 and 2 were all designed with a
similar philosophy which has become known as RISC.
Certain design features have been characteristic of most
RISC processors:
• One Cycle Execution Time: RISC processors have a CPI
(clock per instruction) of one cycle. This is due to the
optimization of each instruction on the CPU and a
technique called;
• Pipelining: a technique that allows for simultaneous
execution of parts, or stages, of instructions to more
efficiently process instructions;
• Large Number Of Registers: the RISC design
philosophy generally incorporates a larger number of
registers to prevent in large amounts of interactions with
memory

4. CHARACTERISTICS
1. Simpler instruction, hence simple
instruction decoding.
2. Instruction come under size of one
word.
3. Instruction take single clock cycle to
get executed.
4. More number of general purpose
register.
5. Simple Addressing Modes.
6. Less Data types.
7. Pipelining can be achieved

5. BASIC RISC DESIGN PRINCIPLES

6. APPLICATIONS OF RISC

7. DIFFERENCE BETWEEN RISC AND CISC

8. PERFORMANCE EQUATION

9. RISC AND CISC CONVERGENCE
• CISC, now executes more than one instruction
within a single clock.
• This allows CISC chips to make use of
pipelining.
• With other technological improvements, it is
now possible to fit many more transistors on a
single chip.
• RISC , incorporate more complicated, CISC-like
commands

10. CONCLUSION
 We are in a “ post-RISC” era, in which two styles have
become so similar that disgusting between them is no
longer relevant.
 RISC chips still retain some important traits.
• utilize uniform, single-cycle instructions.
• register-to-register, load/store architecture.
• still have a large no. of general purpose registers.