This document discusses the history and characteristics of CISC and RISC architectures. It describes how CISC architectures were developed in the 1950s-1970s to address hardware limitations at the time by allowing instructions to perform multiple operations. RISC architectures emerged in the late 1970s-1980s as hardware improved, focusing on simpler instructions that could be executed faster through pipelining. Common RISC and CISC processors used commercially are also outlined.
RISC - Reduced Instruction Set ComputingTushar Swami
A detailed presentation about what is RISC and some of the basic differences between RISC and CISC Computers.
Also enlisting some of the major applications of RISC in the field of Technology.
Pipelining is an speed up technique where multiple instructions are overlapped in execution on a processor. It is an important topic in Computer Architecture.
This slide try to relate the problem with real life scenario for easily understanding the concept and show the major inner mechanism.
RISC - Reduced Instruction Set ComputingTushar Swami
A detailed presentation about what is RISC and some of the basic differences between RISC and CISC Computers.
Also enlisting some of the major applications of RISC in the field of Technology.
Pipelining is an speed up technique where multiple instructions are overlapped in execution on a processor. It is an important topic in Computer Architecture.
This slide try to relate the problem with real life scenario for easily understanding the concept and show the major inner mechanism.
Student will be able to know that fundamental concepts behind computer organization. this PPT includes the following topics: Introduction
Functional Units of Computer
Number Representation and Arithmetic Operations
Memory Location and Addresses
Addressing Modes
Pipelining
Memory Hierarchy
I/O Organization
Control Signals Generation
There are situations, called hazards, that prevent the next instruction in the instruction stream from executing during its designated cycle
There are three classes of hazards
Structural hazard
Data hazard
Branch hazard
(Ref : Computer System Architecture by Morris Mano 3rd edition) : Microprogrammed Control unit, micro instructions, micro operations, symbolic and binary microprogram.
Student will be able to know that fundamental concepts behind computer organization. this PPT includes the following topics: Introduction
Functional Units of Computer
Number Representation and Arithmetic Operations
Memory Location and Addresses
Addressing Modes
Pipelining
Memory Hierarchy
I/O Organization
Control Signals Generation
There are situations, called hazards, that prevent the next instruction in the instruction stream from executing during its designated cycle
There are three classes of hazards
Structural hazard
Data hazard
Branch hazard
(Ref : Computer System Architecture by Morris Mano 3rd edition) : Microprogrammed Control unit, micro instructions, micro operations, symbolic and binary microprogram.
This slide contain the detail about the various organization of computer(Register based organization, Stack Based Organization and Accumulator Based Organization), Addressing Modes, Instruction Formats and finally RISC and CISC
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
An advanced processor is a type of microprocessor that is designed to handle complex tasks and perform calculations at a high speed. These processors are typically used in high-performance computing applications, such as scientific research, artificial intelligence, and data analysis. They often have multiple cores and advanced instruction sets that allow them to process large amounts of data quickly and efficiently. Some examples of advanced processors include Intel's Core i9 and AMD's Ryzen Threadripper
Question 1. please describe an embedded system in less than 100 word.pdfarmcomputers
Question 1. please describe an embedded system in less than 100 words. You will need to cover
all the major characteristics of the embedded system to earn full points.
Question 2. please explain RISC and CISC and give the advantages and disadvantages of both.
Solution
1.An embedded system is a combination of computer hardware and software and some additional
parts, either mechanical or electronic—designed to perform a dedicated function.
Example of embedded system is Digital Watch
It contains a simple, inexpensive 4-bit processor and its own on-chip ROM. The only other
hardware elements of the watch are the inputs (buttons) and outputs (display and speaker).It
consists of a software, which when carefully designed, allows enormous flexibility and helps to
create a reasonably reliable product at extraordinarily low production cost.
other examples are:Microwave oven, cordless phones, ATMS etc
2) RISC (Reduced Instruction Set Computer)
RISC stands for Reduced Instruction Set Computer.
To execute each instruction, if there is separate electronic circuitry in the control unit, which
produces all the necessary signals, this approach of the design of the control section of the
processor is called RISC design.It is also called hard-wired approach.
Examples of RISC processors:
IBM RS6000, MC88100
DEC’s Alpha 21064, 21164 and 21264 processors
Features of RISC Processors:
The standard features of RISC processors are listed below:
RISC processors use a small and limited number of instructions.
RISC machines mostly uses hardwired control unit.
RISC processors consume less power and are having high performance.
Each instruction is very simple and consistent.
RISC processors uses simple addressing modes.
RISC instruction is of uniform fixed length.
CISC (Complex Instruction Set Computer)
CISC stands for Complex Instruction Set Computer. If the control unit contains a number of
micro-electronic circuitry to generate a set of control signals and each micro-circuitry is
activated by a micro-code, this design approach is called CISC design.
Examples of CISC processors are:
Intel 386, 486, Pentium, Pentium Pro, Pentium II, Pentium III
Motorola’s 68000, 68020, 68040, etc.
Features of CISC Processors:
The standard features of CISC processors are listed below:
CISC chips have a large amount of different and complex instructions.
CISC machines generally make use of complex addressing modes.
Different machine programs can be executed on CISC machine.
CISC machines uses micro-program control unit.
CISC processors are having limited number of registers.
Advantages of CISC Architecture:
1)Microprogramming is easy to implement and much less expensive than hard wiring a control
unit.
2)It is easy to add new commands into the chip without changing the structure of the instruction
set as the architecture uses general-purpose hardware to carry out commands.
3)This architecture makes the efficient use of main memory since the complexity (or more
capability) of instruction allo.
Industrial Training at Shahjalal Fertilizer Company Limited (SFCL)MdTanvirMahtab2
This presentation is about the working procedure of Shahjalal Fertilizer Company Limited (SFCL). A Govt. owned Company of Bangladesh Chemical Industries Corporation under Ministry of Industries.
About
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Technical Specifications
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
Key Features
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface
• Compatible with MAFI CCR system
• Copatiable with IDM8000 CCR
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
Application
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdffxintegritypublishin
Advancements in technology unveil a myriad of electrical and electronic breakthroughs geared towards efficiently harnessing limited resources to meet human energy demands. The optimization of hybrid solar PV panels and pumped hydro energy supply systems plays a pivotal role in utilizing natural resources effectively. This initiative not only benefits humanity but also fosters environmental sustainability. The study investigated the design optimization of these hybrid systems, focusing on understanding solar radiation patterns, identifying geographical influences on solar radiation, formulating a mathematical model for system optimization, and determining the optimal configuration of PV panels and pumped hydro storage. Through a comparative analysis approach and eight weeks of data collection, the study addressed key research questions related to solar radiation patterns and optimal system design. The findings highlighted regions with heightened solar radiation levels, showcasing substantial potential for power generation and emphasizing the system's efficiency. Optimizing system design significantly boosted power generation, promoted renewable energy utilization, and enhanced energy storage capacity. The study underscored the benefits of optimizing hybrid solar PV panels and pumped hydro energy supply systems for sustainable energy usage. Optimizing the design of solar PV panels and pumped hydro energy supply systems as examined across diverse climatic conditions in a developing country, not only enhances power generation but also improves the integration of renewable energy sources and boosts energy storage capacities, particularly beneficial for less economically prosperous regions. Additionally, the study provides valuable insights for advancing energy research in economically viable areas. Recommendations included conducting site-specific assessments, utilizing advanced modeling tools, implementing regular maintenance protocols, and enhancing communication among system components.
Hierarchical Digital Twin of a Naval Power SystemKerry Sado
A hierarchical digital twin of a Naval DC power system has been developed and experimentally verified. Similar to other state-of-the-art digital twins, this technology creates a digital replica of the physical system executed in real-time or faster, which can modify hardware controls. However, its advantage stems from distributing computational efforts by utilizing a hierarchical structure composed of lower-level digital twin blocks and a higher-level system digital twin. Each digital twin block is associated with a physical subsystem of the hardware and communicates with a singular system digital twin, which creates a system-level response. By extracting information from each level of the hierarchy, power system controls of the hardware were reconfigured autonomously. This hierarchical digital twin development offers several advantages over other digital twins, particularly in the field of naval power systems. The hierarchical structure allows for greater computational efficiency and scalability while the ability to autonomously reconfigure hardware controls offers increased flexibility and responsiveness. The hierarchical decomposition and models utilized were well aligned with the physical twin, as indicated by the maximum deviations between the developed digital twin hierarchy and the hardware.
Water scarcity is the lack of fresh water resources to meet the standard water demand. There are two type of water scarcity. One is physical. The other is economic water scarcity.
Final project report on grocery store management system..pdfKamal Acharya
In today’s fast-changing business environment, it’s extremely important to be able to respond to client needs in the most effective and timely manner. If your customers wish to see your business online and have instant access to your products or services.
Online Grocery Store is an e-commerce website, which retails various grocery products. This project allows viewing various products available enables registered users to purchase desired products instantly using Paytm, UPI payment processor (Instant Pay) and also can place order by using Cash on Delivery (Pay Later) option. This project provides an easy access to Administrators and Managers to view orders placed using Pay Later and Instant Pay options.
In order to develop an e-commerce website, a number of Technologies must be studied and understood. These include multi-tiered architecture, server and client-side scripting techniques, implementation technologies, programming language (such as PHP, HTML, CSS, JavaScript) and MySQL relational databases. This is a project with the objective to develop a basic website where a consumer is provided with a shopping cart website and also to know about the technologies used to develop such a website.
This document will discuss each of the underlying technologies to create and implement an e- commerce website.
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptxR&R Consult
CFD analysis is incredibly effective at solving mysteries and improving the performance of complex systems!
Here's a great example: At a large natural gas-fired power plant, where they use waste heat to generate steam and energy, they were puzzled that their boiler wasn't producing as much steam as expected.
R&R and Tetra Engineering Group Inc. were asked to solve the issue with reduced steam production.
An inspection had shown that a significant amount of hot flue gas was bypassing the boiler tubes, where the heat was supposed to be transferred.
R&R Consult conducted a CFD analysis, which revealed that 6.3% of the flue gas was bypassing the boiler tubes without transferring heat. The analysis also showed that the flue gas was instead being directed along the sides of the boiler and between the modules that were supposed to capture the heat. This was the cause of the reduced performance.
Based on our results, Tetra Engineering installed covering plates to reduce the bypass flow. This improved the boiler's performance and increased electricity production.
It is always satisfying when we can help solve complex challenges like this. Do your systems also need a check-up or optimization? Give us a call!
Work done in cooperation with James Malloy and David Moelling from Tetra Engineering.
More examples of our work https://www.r-r-consult.dk/en/cases-en/
2. History Of CISC & RISC
Need Of CISC
CISC
CISC Characteristics
CISC Architecture
The Search for RISC
RISC Characteristics
Bus Architecture
Pipeline Architecture
Compiler Structure
Commercial Application
Reference
Overview
3. History Of CISC & RISC
1950s IBM instituted a research program.
1964 Release of System/360.
Mid-1970s improved measurement tools demonstrated on
CISC.
1975 801 project initiated at IBM’s Watson Research Center.
1979 32-bit RISC microprocessor (801) developed led by
Joel Birnbaum.
1984 MIPS (Microprocessor without Interlocked Pipeline Stages)
developed at Stanford, as well as projects done at Berkeley.
1988 RISC processors had taken over high-end of the
workstation market.
4. Need Of CISC
In the past, it was believed that hardware design was easier than
compiler design
Most programs were written in assembly language
Hardware concerns of the past:
Limited and slower memory
Few registers
5. The Solution
As limited registers so …
Instructions have do more work, thereby minimizing the number of
instructions called in a program.
Allow for variations of each instruction
Usually variations in memory access.
6. CISC, which stands for Complex Instruction Set Computer.
Each instruction executes multiple low level operations.
Ex. A single instruction can load from memory, perform an
arithmetic operation, and store the result in memory.
Smaller program size.
CISC
7. CISC Characteristics
A large number of instructions.
Some instructions for special tasks used infrequently.
A large variety of addressing modes (5 to 20).
Variable length instruction formats.
Disadvantages :
However, it soon became apparent that a complex instruction set has
a number of disadvantages:
These include a complex instruction decoding scheme, an
increased size of the control unit, and increased logic delays.
8. CISC Architecture
The essential goal of a CISC architecture is to attempt to provide a
single machine instruction for each high level language instruction
Ex:
IBM/370 computers
Intel Pentium processors
9. The Search for RISC
Compilers became more prevalent.
The majority of CISC instructions were rarely used.
Some complex instructions were slower than a group of simple
instructions performing an equivalent task:
Too many instructions for designers to optimize each one.
Smaller instructions allowed for constants to be stored in the unused bits
of the instruction
This would mean less memory calls to registers or memory.
10. RISC
RISC Stands for Reduced Instruction Set Computer.
It is a microprocessor that is designed to perform a smaller
number of types of computer instruction so that it can operate
at a higher speed.
11. RISC Characteristics
Relatively few instructions
128 or less
Relatively few addressing modes.
Memory access is limited to LOAD and STORE instructions.
All operations done within the registers of the CPU.
This architectural feature simplifies the instruction set and encourages
the optimization of register manipulation.
An essential RISC philosophy is to keep the most frequently accessed
operands in registers and minimize register-memory operations.
12. RISC Characteristics Cont..
Fixed Length, easily decoded instruction format
Typically 4 bytes in length
Single cycle instruction execution
Done by overlapping the fetch, decode and execute phases of
two or three instructions known as Pipelining!!
Large number of registers in the processor unit.
Use of overlapped Register Windows.
13. BUS Architecture
Bus Interconnection of Processor units to memory and IO
subsystem
14. BUS Architecture Cont..
Memory Bus:
Memory bus (also called system bus since it interconnects the
subsystems)
Interconnects the processor with the memory systems and also
connects the I/O bus.
Three sets of signals –address bus, data bus and control bus
15. BUS Architecture Cont..
System Bus :
A system’s bus characteristics --- according to the needs of the
processor, speed, and word length for instructions and data.
Processor internal bus(es) characteristics differ from the system
external bus(es).
16. BUS Architecture Cont..
Buses to interconnect the processor Functional units to memory and
IO subsystem
17. BUS Architecture Cont..
Address Bus
Processor issues the address of the instruction byte or
word to the memory system through the address bus
Processor execution unit, when required, issues the
address of the data (byte or word) to the memory
system through the address bus.
18. Data Bus
BUS Architecture Cont..
When the Processor issues the address of the instruction,
it gets back the instruction through the data bus When
it issues the address of the data, it loads the data through
the data bus.
When it issues the address of the data, it stores the data
in the memory through the data bus.
19. BUS Architecture Cont..
Control Bus
Issues signals to control the timing of various actions
during interconnection.
Bus signals synchronize the subsystems
20. Pipeline Architecture
A technique used in advanced microprocessors where the
microprocessor begins executing a second instruction before the first
has been completed.
A Pipeline is a series of stages, where some work is done at each stage.
The work is not finished until it has passed through all stages.
With pipelining, the computer architecture allows the next instructions
to be fetched while the processor is performing arithmetic operations,
holding them in a buffer close to the processor until each instruction
operation can performed.
21. Pipeline Architecture
The pipeline is divided
into segments and
each segment can
execute it operation
concurrently with the
other segments.
Once a segment
completes an
operations, it passes
the result to the next
segment in the
pipeline and fetches
the next operations
from the preceding
segment.
Instruction 1 Instruction 2
X X
Instruction 4 Instruction 3
X X
Four sample instructions, executed linearly
22. Pipeline Architecture
CISC instructions do not fit pipelined architectures very well.
For pipelining to work effectively, each instruction needs to have
similarities to other instructions, at least in terms of relative instruction
complexity.
23. Instruction Pipelining
Similar to the use of an assembly line in manufacturing plant.
New inputs are accepted at one end before previously accepted
inputs appear as outputs at the other end.
Pipeline requires instruction to be divided into more stages.
So, that at every clock cycle, new instruction can be inserted for
processing
Pipeline Architecture
25. Pipeline Architecture Cont..
Various instruction phases:
Fetch Instruction(FI): fetch the next instruction
Decode Instruction(DI): determine the opcode and operand
Calculate Operands(CO):calculate the effective address of
source operands.
Fetch Operands(FO):fetch each operand from memory.
Execute Instructions(EI): perform the indicated operation and
store the result.
Write result or Operand(WO): store the result into memory.
26. Pipeline Architecture Cont..
RISC Pipeline.
Different from normal one.
Based on type of instruction.
According to instruction type, decide the number of phases in
pipeline.
Number of stages in pipeline are not fixed.
27. Pipeline Architecture Cont..
RISC Pipeline.
Most instructions are register to register
Two phases of execution
I: Instruction fetch
E: Execute
ALU operation with register input and output
For load and store
Three phase execution
I: Instruction fetch
E: Execute
Calculate memory address
D: Memory
Register to memory or memory to register operation
30. Pipeline Architecture Cont..
Increase the Speedup Factor:
I and E stages of two different instructions are performed
simultaneously.
Which yields up to twice the execution rate of serial scheme.
Two problem prevents to achieve this the maximum speedup:
Single port memory is used so only one memory access is possible
per stage.
Branch instruction interrupts the sequential flow.
31. Pipeline Architecture Cont..
Four stage pipeline:
E stage usually involves an ALU operation, it may be longer. So
we can divide into two stages:
E1: Register file read.
E2: ALU operation and register write.
33. Pipeline Architecture Cont..
Optimization of RISC Pipelining:
Delayed branch:
Does not take effect until after execution of following instruction.
This following instruction is the delay slot.
Increased performance can be achieved by reordering the
instructions!!!
This can be applicable for unconditional branches.
34. Pipeline Architecture Cont..
Normal and Delayed Branch:
Address Normal
Branch
Delayed
Branch
Optimized
Delayed
Branch
100 LOAD X, rA LOAD X, rA LOAD X, rA
101 ADD 1, rA ADD 1, rA JUMP 105
102 JUMP 105 JUMP 106 ADD 1, rA
103 ADD rA, rB NOOP ADD rA, rB
104 SUB rC, rB ADD rA, rB SUB rC, rB
105 STORE rA, Z SUB rC, rB STORE rA, Z
106 STORE rA, Z
35. Compiler Structure
A compiler is a Computer Program (or set of programs) that
transforms Source Code written in a Programming Language (the
source language) into another computer language (the target language,
often having a binary form known as Object Code).
The most common reason for wanting to transform source code is to
create an Executable program.
37. Compiler Structure Cont..
In a compiler,
linear analysis
is called Lexical Analysis or Scanning and is performed by
the Lexical Analyzer or Lexer,
hierarchical analysis
is called Syntax Analysis or Parsing and is performed by
the Syntax Analyzer or Parser.
During the analysis, the compiler manages a Symbol Table by
recording the identifiers of the source program
collecting information (called Attributes) about them: storage
allocation, type, scope, and (for functions) signature.
38. Compiler Structure Cont..
When the identifier x is found by the lexical analyzer
generates the token id
enters the lexeme x in the symbol-table (if it is not already there)
associates to the generated token a pointer to the symbol-table
entry x. This pointer is called the Lexical Value of the token.
During the analysis or synthesis, the compiler may Detect Errors and
report on them.
However, after detecting an error, the compilation should proceed
allowing further errors to be detected.
The syntax and semantic phases usually handle a large fraction of the
errors detectable by the compiler.
39. Commercial Applications
RISC:
First commercially available RISC processor was MIPS
R4000
Supports thirty-two 64-bit registers
128Kb of high speed cache
SPARC
Based on Berkeley RISC model
PowerPC.
Motorola.
Nintendo Game Boy Advance (ARM7)
Nintendo DS (ARM7, ARM9)
40. Commercial Applications Cont..
CISC:
CISC instruction set architectures are
System/360 through z/Architecture,
PDP-11,
VAX,
Motorola 68k, and Intel(R) 80x86.
41. Reference
Computer Organization And Architecture,8th Edition , William Stallings
http://nptel.ac.in/courses/Webcourse-contents/IIT-
%20Guwahati/comp_org_arc/web/
http://www.borrett.id.au/computing/art-1991-06-02.htm