RISC vs CISC architecture

1. RISC Processors
by GANESH P

2. CONTENTS
Introduction
History
RISC versus CISC
RISC Design Principles
Examples for RISC Processors
Pipelining
Modern Day Advancement
References

3. INTRODUCTION
Two basic types of processor design philosophies : CISC and
RISC
CISC – Complex Instruction Set Computer
RISC- Reduced Instruction Set Computer
The difference between RISC and CISC can lays on many
levels, lots of plausible arguments are put forward by both
side.
Such as code density, transistor counts, memory bottlenecks,
compiler and decode complexity etc.

4. HISTORY
The IBM 360 system, created in 1964, was probably the first
modern processor system.
From that CISC microprocessors became prevalent, each
successive processor having more and more complicated
hardware and more and more complex instruction sets.
In the middle of 70's with more and more complex
instructions sets, decoding and execution of such instructions
were complicated and time-consuming, finally which affects
the performance.

5. RISC chips were evolved in 70’s.
John Cocke at IBM's T.J Watson Research centre provided the
fundamental concepts of RISC.
The idea came from the IBM 801minicomputer built in 1971
which is used as a fast controller in a very large telephone
switching system.

6. RISC versus CISC
1. Multiple clock cycle 1. Single clock cycle
2. Any instructions may refer
memory.
2. Only LOAD/STORE refer
memory.
3. Not pipelined or less pipelined 3. Highly pipelined
4. Instructions interpreted by the
micro program.
4. Instructions executed by the
hardware.
5. Variable format instructions 5. Fixed format instruction
6. Many instructions and modes 6. Few instructions and modes
7. Complexity in micro program 7. Complexity in the compiler
8. Single register set 8. Multiple register set
CISC RISC

7. Multiplying two Numbers in Memory

8. The CISC Approach
Multiplying two numbers can be completed with one
instruction:
MULT 2:3, 5:2
It operates directly on the computer's memory banks and
does not require the programmer to explicitly call any loading
or storing functions.
Advantages: Compiler has to do very little work to translate a
high-level language statement into assembly.
Because length of the code is short, very little RAM is
required to store instructions.

9. The RISC Approach
Thus, the "MULT" command described above could be divided into
three separate commands:
LOAD A, 2:3
LOAD B, 5:2
PROD A, B
STORE 2:3, A
LOAD - move data from the memory bank to a register.
PROD - finds the product of two operands located within the registers.
STORE - moves data from a register to the memory banks.
Requires only one clock cycle to execute one instruction.
Require less transistors of hardware space but leaving more room for
general purpose registers.

10. RISC Design Principles
1. Simple Instructions:
The objective is to design simple instruction so that each
can execute in one cycle.
2. Register-to-Register operations:
RISC processors only allow LOAD/STORE operations to
access memory.
Rest of the operations work on the register-to-register
basis.
This feature of restricting operands to registers also
simplifies the control unit.

11. 3. Simple Addressing modes:
RISC processors employ register-to-register instruction so
most instruction use register based addressing.
Only LOAD/STORE instructions need memory addressing
modes.
4. Large Register Set:
For register-to-register operation large number of
registers required.
Provide ample opportunities for the compiler to optimize
their usage.

12. With large register set can minimize overhead associated
with the procedure calls and returns.
To speed up procedure calls, we can use registers to
store local variables as well as passing arguments.
5. Fixed-Length:
RISC design use fixed-length instructions. Variable length
instructions cause implementation and execution inefficient.
The boundaries of various fields in an instruction such as
opcode and source operands are fixed. This allows efficient
decoding and scheduling of instructions.

13. Examples for RISC Architectures
MIPS (Million Instructions Per Second)
Dominant in embedded applications including digital
cameras, digital tv’s, sony playstaion2, network routers and
so on.
SPARC (Scalable Processor ARChitecture)
1987 – SPARC version 7, 32-bit processor.
1990 – SPARC version 8, 32–bit.
1993 – SPARC version 9, 64-bit.

14. POWER PC
Developed by IBM, MOTOROLA, APPLE
64bit architecture can use in two modes : 64bit/ 32bit. It
supports dynamic switching between these two modes.
ITANIUM
Developed by INTEL.
Based on EPIC (Explicit Parallel Instruction Computing) design
philosophy
ARM(Advanced RISC Machines)
Cost – sensitive embedded applications modems, mobile
phones, pagers and most DSP instructions.

15. Pipelining
A RISC processor pipeline operates in much the same way,
although the stages in the pipeline are different.
While different processors have different numbers of steps,
they are basically variations of these five, used in the MIPS
R3000 processor:
Fetch instructions from memory
Read registers and decode the instruction
Execute the instruction or calculate an address
Access an operand in data memory
Write the result into a register

16. Modern Day Advancement
NISC PROCESSORS
 Further advancement of compiler and memory
technologies leads to emerging VLIW processors.
 NISC is a successor of VLIW processors.
 In NISC, the compiler has both horizontal and vertical
control of the operations in the datapath. Therefore, the
hardware is much simpler.
 No instruction set computing (NISC). NISC is a statically-
scheduled horizontal nanocoded architecture (SSHNA).
 The term "statically scheduled" means, operation
scheduling and hazard handling are done by a compiler.
 The term "horizontal nanocoded" means that NISC does
not have any predefined instruction set or microcode.

17. References
 http://cse.stanford.edu/class/sophomore-college/projects-00/risc/
 http://www.visionengineer.com/comp/why_cisc.shtml
 http://www.visionengineer.com/comp/why_risc.shtml
 http://www.embedded.com/story/OEG20030205S0025
 http://encyclopedia.laborlawtalk.com/PowerPC
 http://www.sunderland.ac.uk/~ts0jti/comparch/ciscrisc.htm
 http://www.heyrick.co.uk/assembler/riscvcisc.html
 http://www.aallison.com/history.htm