1) Amritha P V is seeking a challenging position to continuously learn, create, innovate and contribute to short and long term organizational goals using her technological and managerial skills. 2) She has extensive experience in Verilog HDL, SystemVerilog, UVM verification methodologies, and industry standard EDA tools for front-end design and verification. 3) Her projects include UART IP core verification using SystemVerilog and UVM, and designing and verifying a 1x3 router using Verilog, SystemVerilog, and UVM.

1. Name : AMRITHA P V
Address:
Address: #1/11, “SRI SAI SANNIDHI” 1st Main Road,1st Stage,
BrindavanExtenstion Road,
Arekere Micro Layout,
Bannerghetta Road,
Bangalore,
Karnataka: 560076.
Ph. No: +91-8867166426
Email id:
amritha12menon@gmail.com
PROFESSIONAL OBJECTIVE
Passionate to learn new technologies and to excel in innovative technology application.
Seeking a challenging position which will enable me to continuously learn, create, innovate
and simultaneously contribute to the short and long term goals of the organization effectively
using technological & managerial skills.
SUMMARY OF QUALIFICATIONS
 Good understanding of the ASIC and FPGA design flow
 Extensive experience in writing RTL models in Verilog HDL and Testbenches in
SystemVerilog and UVM
 Very good knowledge in verification methodologies
 Experience in using industry standard EDA tools for the front-end design and
verification
VLSI DOMAIN SKILLS
HDL : Verilog
HVL : SystemVerilog
Verification Methodologies : Coverage Driven Verification
Assertion Based Verification - SVA
TB Methodology : UVM
Script : Make, Perl
EDA Tool : Questasim and ISE
Domain : ASIC/FPGA front-end Design and Verification
Knowledge : RTL Coding, FSM based design, Simulation,
Code Coverage, Functional Coverage, Synthesis,
Static Timing Analysis
PROFESSIONAL QUALIFICATION
Maven SiliconCertified Advanced VLSI Designand Verificationcourse from
Maven Silicon VLSI Design and Training Center, Bangalore.
(April 2015)

2. ACADEMIC SUMMARY
COURSE BOARD OF EXAM INSTITUTION AGGREGATE
B.Tech in
Electronics &
Communication
(2010-2014)
Cochin University of
Science And
Technology,
Ernakulam, Kerala
Toc H institute Of Science
And Technology,
Arakkunnam, Kerala
67.7%
HIGHER
SECONDARY
(2007-2009)
State Board Of
Secondary Education
Presentation H S S ,
Kozhikode, Kerala. 79%
S.S.L.C
(2007)
State Board Of
Secondary Education
F.M.E.M.H.S.S, Tirur,
Kerala. 94%
VLSI PROJECTS
[1] UART IP CORE– Verification
HVL: SystemVerilog
TB Methodology: UVM
EDA Tools: Questasim – Verification Platform
Description: The UART core provides serial communication capabilities ,which allow
communication with modem or other external devices.
Responsibilities:
 Created the verification plan.
 Architected the class based verification environment using UVM
 Verified the RTL model using UVM.
 Generated functional and code coverage for the RTL verification sign-off
[2] Router 1x3 – RTL design and Verification
HDL: Verilog
HVL: SystemVerilog
TB Methodology: UVM
EDA Tools: Questasim and ISE
Description: The router accepts data packets on a single 8-bit port and routes them to
one of the three output channels, channel0, channel1 and channel2.
Responsibilities:
 Architected the design
 Implemented RTL using Verilog HDL.
 Architected the class based verification environment using UVM.
 Verified the RTL model using UVM
 Generated functional and code coverage for the RTL verification sign-off
 Synthesized the design

3. ENGINEERING PROJECTS
Major: Software Defined Radio
Minor: Intelligent Ambulance
.
PERSONAL DETAILS
Date of Birth : 30-04-1991
Sex :Female
Marital Status : Single
Nationality : Indian
Languages Known : English, Hindi, Malayalam.
DECLARATION
I hereby declare that the above-mentioned particulars are true to the best of my knowledge
and belief.
AMRITHA P V