I am Apoorva Tripathi currently worked in Cadence Design System as a Solution Intern. trained in front-end design and Verification, I have experience in writing RTL models in Verilog HDL and Testbenches in SystemVerilog and UVM. Currently, I am and looking for opportunities that require the same skills, I am sharing my resume with you. Please review my profile and my resume is attached herewith. Thanks and Regards Apoorva Tripathi {apoorvatripathi24@gmail.com}

1. Career Objective
Aiming to learn new technologies and gain knowledge by working for a VLSI
Industry preferably in Design and Verification domain with an opportunity of work-
ing with diverse group of people and acquire proficiency. Take up new challenges
and overcome hurdles by utilizing my skills and abilities.
Professional Experience
Solution Intern. in Cadence Design Systems, Inc.
(13 April 2020 - 12 April 2021.)
-Verification of ARM-based Internal reference SoC using VIP and AVIP test benches.
-Assistance in the development of constraint random design verification Environ-
ment pertaining to simulation and regression.
-Having working knowledge for ARM-Based interconnected specifically targeted to
NIC400 and CCI500.
-Key Role in Analysis and verification of flows for Internal reference SoC, their de-
bugging and Bring up.
-Worked for Getting User control in from command line and Capturing data from
.log files using Script.
-Working knowledge for AMBA Protocols AXI, ABP, AHB.
-Working on EDA Tools like Cadence Palladium, Xcelium, and vManager.
-Idea for AI/ML Implementation in SoC.
Summary of Qualification
• Good Understanding of ASIC and FPGA design flow.
• Extensive experience in writing RTL module using Verilog HDL.
• Good experience in writing Test benches using System Verilog and UVM.
• Good Knowledge in Verification methodologies.
• Experience in using industry standard EDA tools for the front-end and verifi-
cation.
• Exposure in verification test plan, track debug in design units.
Technical Skills
VLSI Domain Skills.
• HDL : Verilog.
• HVL : SystemVerilog
• Verification Methodology:Coverage driven Verification, Assertion based Veri-
fication.
• Tb Methodology : UVM/SV, Formal(JasperG), MDV (vManager)
• Protocol : AMBA
• EDA Tools : QuestaSim - Mentor Graphics, Riviera Pro - Aldec, ISE - Xilinx.
• Domain : ASIC/FPGA front-end Design Verification.
• Simulation : Xcelium
• Emulation : Palladium
• Memory/Peripheral interfaces : PCIe
• Configuration Management : P4
Apoorva Shanker
Tripathi
i Solution Intern.
Cadence Design System
B apoorvatripathi24@gmail.com
T +91 7839357152
m https://www.linkedin.com/in/
apoorva-tripathi-71aaa4137/
Education
Btech.(ECE) KIET Group of
Institutions | 2019 | GPA:80/100
Class XII
Vidyashram Public School, Kota |
2014 | 75/100
Class X
Kendriya Vidyalaya, Azamgarh | 2012
| 9.2/10
Maven Silicon VLSI Design and
Training Center, Bangalore
May-2019-> March2020
Advanced VLSI Design and
Verification course
MOOCs
-C++ Language Fundamentals for
Design and Verification.
By Cadence Design Systems
-SystemVerilog for Design and
Verification v20.5 Exam.
By Cadence Design Systems
-Verilog Language and Application
v26.0 Exam.
By Cadence Design Systems
Extra-Curricular
-Participated in Quiz, Debate and MUN
(Model United Nation).
-Student Placement coordinator
(SPC) of College (2018-19).
-ROBOWAR Technical Event : First
Position.
-Part of Electric Vehicle Club
(Developed Hybrid Electric Vehicle).

2. DFT Skills.
VLSI Testing : Design For Testability using Tessent tool, Boundary scan, MBIST, Scan
chain Insertion, Clock and DRC, IJTAG Implementations.
IT Skills.
Programming Languages : C, C++,
Scripting Language : Perl, Shell.

3. Curriculum Project
[1] Router 1x3 RTL Design and Verification.
HDL: Verilog
HVL: SystemVerilog TB Methodology: UVM EDA Tools: Questasim and ISE
Description: The Router accepts data packets on a single 8-bit port and routes them
to one of the three output channels those are channel0, channel1 and channel2.
Responsibilities: -Architected the block level structure for the design.
-Implemented RTL using Verilog HDL.
-Architected the class-based verification environment using SystemVerilog.
-Verified the RTL model using SystemVerilog.
-Generated functional and code coverage for the RTL Verification sign-off
-Synthesized the design.
[2] AHB2APB Bridge IP Core Verification.
HVL: System Verilog TB Methodology: UVM EDA Tool: Questasim
Description: The AHB to APB bridge is an AHB slave which works as an interface
between the high speed AHB and the low performance APB buses
Responsibilities: -Architected the class based verification environment in UVM.
-Verified the RTL module with single master and single slave.
-Generated functional and code coverage for the RTL verification sign-off.
Academic Achievements And Co-Curricular Activities
-Participated in Quiz, Debate and MUN (Model United Nation).
-Student Placement Coordinator (SPC) of College (2018-19).
-ROBOWAR Technical Event : First Position.
-Part of Electric Vehicle Club (Developed Hybrid Electric Vehicle).
-Digital Champions Program at JIO Completed with Platinum Certification.
-Internshala Student Partner12 (ISP) at Internshala.
Declaration
I hear by declare that the information furnished above is true to best of my knowl-
edge.
Date :
Place Name
Hobbies
-Cricket Enthusiastic
-Volunteering
PersonalDetails
Father’s Name: Prabha Shanker
Tripathi.
Mother’s Name: Poonam
Tripathi.
Date of Birth: 22-March-1997
Linguistic Proficiency: English,
Hindi.