This document contains the resume of Sarveshwar Kumar. He has over 7 years of experience in RTL design, verification and synthesis. He has worked on projects involving PCIe checker implementation using UVM, designing an APB bridge, and verifying the SPI protocol. He is proficient in SystemVerilog, Verilog, C/C++ and has experience using EDA tools like Cadence and Xilinx. He holds an MSc in VLSI Design and Verification from Manipal University and a BTech in Telecommunication from BMS Institute of Technology.

1. SARVESHWAR KUMAR
Mob. No.: +91-9738436646
Email id: sarveshwar930@gmail.com
Career Objective
I am a creative person who always thinks of setting new goals to reach the peaks. Seeking a position to utilize
my creative problem solving, programming skills and abilities in a Semiconductor Industry that offers
professional growth while being resourceful, innovative and flexible.
Summary of Skills:
 Excellent knowledge of RTL design , integration, verification and synthesis
 Excellent knowledge of System Verilog and UVM
 Excellent knowledge of ASIC design flow, digital circuit design, and Chip Partitioning
 In-depth knowledge of EDA tools, Verilog HDL
 Comprehensive coding skills in Perl and shell scripting languages
 Comprehensive knowledge of physical design implementation, and static timing analysis
 Sound knowledge of Design for Test, Clock Tree, Memory BIST, and physical design methodologies
 Strong leadership, troubleshooting, and communication skills
Experience
Whizchip Design Technologies Pvt. Ltd., Bangalore, India
Responsibilities include:
 Assigned the task of RTL design of AMBA-APB.
 Handle the tasks of analysis of the given specification
 Responsible for and developing the Verification plan
 Assigned responsibilities of developing test scenarios and sequences for PCIe.
 Handle the task of UVM driver for PCIe.
 Assigned the task of developing verification environment for SPI.
Key Skills
Proficient or familiar with a vast array of concepts, technologies, and programming languages including:
Tools
Cadence Tool-set:
o Incisive Platform
o Encounter Platform
o Virtuoso Platform
Quartus-II
Xilinx ISE
Languages
System Verilog, Verilog, C++, C & Data structures, Assembly Languages, Perl and Shell Scripting.
Operating systems
LINUX Red Hat/Ubuntu, WINDOWS

2. Projects
Implementation of PCIe Checker in UVM
Objective:
Implementation of a PCIe checker that would be able to monitor LTSSM (Link Training and State Status
Machine) of PCIe (version 1, 2.0 and 3.0).
Tools Used:
 Cadence INCISIVE-12.2
 System Verilog (UVM)
Team size: 03
Roles and responsibilities:
 Analyze and design UVM Drivers and sequences for the RC (Root Complex) of the PCIe checker.
 The framework designed should be able to generate the next sequence based on the response from the
UVM monitor.
Designing Advanced Peripheral Bus (APB) Bridge
Objective:
The main idea behind this system is to provide a bridge between high performance devices (like processor)
and low speed devices (like UART, RTC, and SPI etc.)
Tools Used:
 Cadence INCISIVE-12.2
 System Verilog (UVM)
Team size: 01
Roles and responsibilities:
Designed and developed an APB bridge to interface several peripherals to the main processor
Verification of the Serial Peripheral Interface (SPI)
Objective:
Analysis and development of the test scenarios in order to verify the SPI protocol of a microprocessor unit.
Tools Used:
 Cadence INCISIVE-12.2
 System Verilog (UVM)
Team size: 01
Roles and responsibilities:
 To develop the Verification Environment for the SPI protocol and to verify the functionality of the
same.
Design of OCX protocol
Objective:
The main idea behind this system is to provide facility to synchronize the data between two systems of
different speed.
Tools Used:
 Cadence INCISIVE-12.2
 System Verilog (UVM)
Team size: 01
Roles and responsibilities:
 The design part of this protocol consists of two parts: design of the receiver and design of the transmitter. The
design was carried in such a way that they can be connected back to back.

3. Education
MSc. Tech in VLSI Design and Verification
SOIS, MANIPAL UNIVERSITY, Manipal
CGPA: 8.54 on a scale of 10
Bachelor of Engineering in Telecommunication
B M S INSTITUTE OF TECHNOLOGY, Bangalore
Affiliated to VISVESVARAYA TECHNOLOGICAL UNIVERSITY, Belgaum
CGPA: 7.3 on a scale of 10
Activities
 Organized various Verilog/System Verilog workshops for Digital design and verification in Manipal
University.
 Undergone an in-plant training at Bharat Heavy Electricals Limited in July’2010.
 Participated in the Li2-Robo-III workshop (Building of autonomous robots using Microcontrollers on
Arduino based platform).
 Member of IEEE student’s chapter during B.E. in BMSIT Bangalore.
 Organized and participated in various events in college fest.
 A core member of NSS- organized and participated in various NSS activities during BE.
Personal Details
Date of Birth: 25th
December’1989
Languages Known: English and Hindi.
Mobile No.: +91-97 38 436646
Email ID: sarveshwar930@gmail.com
Address:
#72/3, Anand Bhawan, 9th Main, 3rd Cross, Mathikhere, Karnataka (INDIA)
PIN: 560054
References
Will be pleased to furnish upon request