1. RESUME
KRISHNA KUMAR T
Mobile :- +91-9966719530
Email-id :- kkece414@gmail.com
OBJECTIVE:
To learn and function effectively in an organization and be able to deliver to the Bottom-line and
constantly upgrade my knowledge and skills and make a difference in whatever I do.
PROFILE SUMMARY :
 Conversant with Digital Electronics, Analog Electronics.
 Good understanding of the ASIC & FPGA design flow.
 Proficient with hands on experience in Digital Design with Verilog, Development of Verification
Environment & Constraint Random Test Generation in System Verilog and UVM.
 Possess flexibility to adapt to new working environments.
 Good knowledge on static timing analysis and synthesis.
 Having 1 year experience in Teaching.
ACADEMIC DETAILS :
 M. Tech (VLSI System Design) from SVIET (JNTUK) in 2015 with 68%.
 B. Tech (Electronics and Communication Engineering) from ASR College of Engg.,Tanuku in 2010 with
61.2%.
 12th from Sri chaithanya Junior College, Machilipatnam, Board of intermediate Education in 2006 with
80.9%.
 10th from RVM High School, Pedana, Board of Secondary Education in 2004 with 60.2%.
TECHNICAL SKILLS :
 HDL’s : Verilog.
 HVL's : System Verilog.
 Verification Methodology : UVM.
 Programming Languages : Basic knowledge on C.
 EDA Tools : Xilinx ISE, Rivera Pro.
 Platforms : Working knowledge of Windows, Linux.
 Scripting Language : Perl.

2. PROJECTS :
[1] AHB To APB Bridge - Verification
HVL: SystemVerilog
TB Methodology: UVM
EDA Tools: Riviera-Pro
Description: AHB to APB Bridge is required to communicate between a high frequency operating AHB
components and low frequency operating APB components. It supports both read and writes operations. AHB
is nearly 3 times faster than APB, to avoid the loss of data between these 2 components the bridge is designed
on Pipe-lining concept. This Bridge acts as master for APB components and as a slave for AHB components, it
supports single, burst and increment type of data transfer.
Responsibilities:
 Developed architecture of verification environment using UVM.
 Developed various test cases.
 Generated functional and code coverage for verification sign-off.
[2] SPI – Verification
HVL: SystemVerilog
TB Methodology: UVM
EDA Tools: Riviera-Pro
Description: The SPI provides the interfacing between Master and Slave. It is responsible for buffering
address, control and data from the Master and converting the data to a serial form and send to the slave. And
slave will send the data in the form of serial it has to convert back to parallel. At a time only one slave can be
selected.
Responsibilities:
 Created the verification plan.
 Architected the class based verification environment using UVM
 Verified the RTL model using UVM.
 Generated functional and code coverage for the RTL verification sign-off
[3] Router 1X3 – RTL Design and Verification HDL : Verilog
TB Methodology : UVM
EDA Tools : Xilinx ISE and Riviera-Pro
Description : The router accepts data packets on a single 8-bit port and routes them to one of the three output
channels, channel0, channel1 and channel2.
Responsibilities :
 Implemented RTL using Verilog-HDL.
 Architectured the class based Verification environment using UVM.
 Generated Functional Coverage and Code Coverage for the Design.
M.TECH PROJECT:
[4]Improved Fault Tolerant Mechanism & Area Optimization Using Dmc-
HDL : VHDL
EDA Tools : Xilinx ISE
Description : The main objective of this project is to implement a fault tolerant mechanism using
decimal matrix code (DMC).The DMC utilizes decimal algorithm to obtain the
maximum error detection capability.
Responsibilities : Design RTL using VHDL.
Simulation by using ISIM in implementaion design

3. PROFESSIONAL QUALIFICATION:
Maven Silicon Certified Advanced VLSI Design and Verification Course
From Maven Silicon VLSI Design and Training Centre, Bengaluru
Duration:April-2016 to September-2016.
Presently doing Project in Maven Silicon VLSI Design and Training Centre, Bengaluru.
PUBLICATIONS:
Paper published on “Improved Fault Tolerant Mechanism and Area Optimization using Decimal
Matrix Code” in International Journal of Scientific Engineering Technology Research Volume.04, IssueNo.51,
Pages: 10963-10968, December-2015.
Link: http://ijsetr.com/issue.php?issue=ISSUE%2051&volume=Volume4&page=2
STRENGTHS :
 Willingness to learn and ability to implement.
 Ability to work as an individual and in a team.
 Positive thinking.
HOBBIES :
 Reading Books, Playing Cricket & Chess, Solving Rubics Cube.
AREAS OF INTEREST :
 Digital Design and Verification, System-on-Chip.
PERSONAL DETAILS :
Address : S/o T.Sudhakar, H.No. 2/59-1-9, Matam Road, Pedana(M), Krishna(Dist)
Andhra Pradesh, Pin - 521366
Languages Known : English & Telugu
Nationality : INDIAN
DECLARATION :
I hereby declare that the information furnished above is true.
PLACE : (KRISHNA KUMAR.T)
DATE :