Gnaneshwar Jogu is seeking a career where he can utilize his technical knowledge and analytical skills. He has good understanding of ASIC verification flow and skills in System Verilog and Verilog. He has hands-on experience with tools like Questasim and Modelsim. He has worked on verification projects including UART, FIFO, AMBA APB3.0 interface, and dual port RAM. He is looking to leverage his qualifications and project experience for the growth of an organization.

1. GNANESHWAR JOGU.
Mobile : +91-9738411835. #39,13th Main, Sector-4,
Email :gnaneshwarjs123@gmail.com HSR Layout,
Bangalore.
CAREER OBJECTIVE:
Seeking a good career where my technical knowledge and analytical skills will be
utilized for the growth of the organization in addition to providing me a good learning
opportunity.
PROFESSIONAL SUMMARY:
 Good understanding of ASIC verification flow.
 Good programming skills in System Verilog and Verilog Hardware
Description Language.
 Good understanding and programming skills using Verification methodologies
UVM.
 Hands on experience with EDA tools (Questasim,Modelsim).
 Good Understanding of HVL concepts. Able to code test scenario using existing
given test plan. Knowledge of HVL test bench components, debugging HVL
environment.
 Understanding of functional coverage metric and identification of additional
scenarios.
 Good programming medium complex HVL test bench modules like monitors,
checker, BFMs etc., from the given verification plan and functional coverage
modules based on coverage plan.
 Experience of developing the verification environment using System Verilog and
UVM.
WORK EXPERIENCE:
 Working as lab co-ordinator in “Expert HDL training & consultancy services”,
Bangalore from March15th2014 – till now.
TECHNICAL SKILLS:
Category Tools/Languages
HDL programming Verilog.
HVL Programming System Verilog.
Methodologies UVM.
EDA Tools Modelsim & Questasim, VCS.
Scripting Languages Basics of Perl.
Operating system Linux, Windows.

2. Academic Projects:
UG project: “AN ADAPTIVE HUFFMAN DECODING ALGORITHM FOR
MP3 DECODER”
PROJECTS During training:
1.Verification of “UART” protocol using “UVM-SV”
Tools Used : Questasim.
Language Used: System Verilog.
Role : Verification Engineer
Description:
UART is a popular serial asynchronous communication to connect the processor and
a peripheral. It essentially consists of transmitter and receiver and interrupt controller.
Transmitter generates the Uart frame and sends the serial data with baud rate of
maximum 3Mbps. Receiver also have 256 byte deep FIFO of each 8 bit wide and
generates the interrupts to the processor as and when the data is ready in FIFO and
also when it receives errors.
Responsibilities:
 Developed UVM Test bench.
 Written the test cases.
 Implemented the Functional Coverage which validates the protocol.
2. Verification of “Asynchronous-FIFO” using “UVM-SV”
Tool Used : Questasim
Language Used : System Verilog.
Role : Verification Engineer
Description:
A FIFO is a special type of buffer. The name FIFO stands for first in first out and
means that the data written into the buffer first comes out of it first. Asynchronous
FIFO means Write and read happens at the same time with different clock
frequencies. In this asynchronous FIFO we are using Gray counters.
Responsibilities:
 Involved in creating verification environment in UVM.
 Involved in creating Test cases.

3. 3. Verification of “AMBA APB3.0“Interface Protocol using “UVM-SV”
Tools Used : Questasim.
Language Used : System Verilog
Role : Verification Engineer
Description:
The APB is part of the AMBA 3 protocol family. It provides a low-cost interface that
isoptimized for minimal power consumption and reduced interface complexity. The
APB interfaces to any peripherals that are low-bandwidth and do not require the high
performance of a pipelined bus interface.
Responsibilities:
 Involved in creating verification environment in UVM.
 Involved in creating Test cases.
4. Verification of “Dual Port RAM –RTL design and verification.
Tools Used : Questasim.
Language Used : System Verilog
Role : Verification Engineer
Description:
Implemented the Dual Port Ram using Verilog HDL independently Architected the
class based verification environment using SV Verified the RTL module using SV.
Responsibilities:
 Involved in creating verification environment in UVM.
 Involved in creating Test cases.
EDUCATION:
No Degree Passed Out
Year
Percentage Board/University
1 B.Tech
(Electronics & Communication
Engg)
April 2013 69% Jawaharlal Nehru
Technological
University,Hyderabad
2 Intermediate(10+2) April 2009 70.7% Board Of
Intermediate.
3 S.S.C (10th ) March 2007 67% Board Of Secondary
Education.

4. ACHIEVEMENTS:
 Qualified in PGECET 2013.
PROFILE & STRENGTHS:
 Qualified B.Tech with excellent technical proficiency and demonstrated
analytical abilities and creativity.
 Detail-oriented, with proven communication and analytical skills, can handle
multiple tasks to meet deadlines in pressure situations.
 Possess good innovative leadership qualities, adaptability, confidence and
strong belief in completing the assigned work successfully and zeal to learn
new things.
PERSONAL DETAILS:
Name : Gnaneshwar jogu
Father’s Name : Sayanna.
Date of Birth : 10-03-1991.
Gender : Male
Languages Known : English, Hindi, and Telugu.
DECLARATION:
I hereby declare that the above-mentioned details are true to my knowledge
and I assure you that I would work to my level best if I were selected in your
company.
PLACE: Bangalore
DATE: (Gnaneshwar jogu)