Siva Tanneru is seeking a position in physical design and provides their contact information and objectives. They have education and experience in areas like VLSI design, Verilog coding, timing analysis, and TCL scripting. Their resume outlines projects and work experience in physical design tasks like floorplanning, placement, timing analysis, and routing.
1. SIVA TANNERU
Email id: tannerusivavlsi@gmail.com
Mobile Number: 9066840141
Career Objective:
I want to work in Physical Design Domain, Seeking a challenging environment that encourages
continuous learning and providing exposure to new ideas that stimulate personnel and
professional growth.
Core Competency:
• Good understanding of fundamentals of Transistors and circuit theory
• Good knowledge of Verilog RTL coding
• Good knowledge of Digital Design Concepts
• Excellent knowledge of IC Fabrication process
• Good in Timing Report Analysing skills
• Good in writing , maintaining the TCL scripts
• Good exposure to technology by undergoing additional training in VLSI
• Implemented a VLSI project during my post graduation
• Attended technology intensive courses conducted by industry experts on VLSI
• Good working knowledge of Linux, and C programming
Education :
Degree Discipline
Institute
University
Year of
Passing
Aggregate
PG Diploma ADAD
RV-VLSI Design
Center
2015 Pursuing
M.Tech VLSI-SD
Aurora's
Technological
Research
Institute
JNTUH
2013 78.25 %
B.Tech
Electronics &
Communication
Vaagdevi College
Of Engineering
JNTUH
2009 66.07 %
12th MPC
Sri Krishnaveni Jr.
College
BIE
2005 89.9 %
10th
Arunodaya
Vidyalayam
BSE
2003 84.16 %
2. Academic Projects:
Title: Analysing different Timing reports for OCV
Role: Analysing Timing reports
Organization:
Duration of Project in
Months:
RV-VLSI Design Center
1
Description: 1.Timing reports has been generated for different designs for MCMM
and analysed the same
2.Analysed CRPR effect in timing reports
3.Understanding the techniques of fixing violations
Tools Used : PT shell
Deliverable/Challenges
Faced:
Understanding signal integrity and cross-talk effects, Timing analysis
of latch based designs, effects of clock skew on timing
Title: Analysing, Writing and debugging TCL Scripts
Role: Analysing various TCL scripts, Maintaining TCL scripts
Organization: RV-VLSI Design Center
Duration of Project in
Months: 1/2
Description: Writing various TCL scripts to extract information from ICC data
base, Understanding TCL scripts generated by ICCompiler, Writing
TCL to various examples
Tools Used : Tclsh, TCL tutor, Linux OS
Deliverable/Challenges
Faced: Debugging TCL Scripts, writing TCL to design examples
Title 180nm Physical Design Of Torpedo Block Level Subsyste
Role:
Responsible for floor planning, placement and Analyzing
timing reports and CTS and routing and chipfinish and
physical verification.
Organization: RV-VLSI Design Center
Duration of Project in
Months: 4½ (On-going)
Description: Torpedo sub block includes 32 macros, 43275 standard cells
with supply voltage of 1.8V, working at an operating
frequency of 400 MHz, it has total of 5 clocks 3 propagated
and 2 generated, Design uses 5 metal layers. Fab: Jazz
semiconductor, Technology node: 180nm
Tools Used : ICCompiler, Prime Time, Hercules from Synopsys, Calibre
3. from Mentor Graphics.
Deliverable/Challenges
Faced:
1.Placement of macros with congestion free Floor planning
2. Deciding number of power straps to get IR drop ( VDD +
VSS ) less than 5% of 1.8V
3. Identifying useful skew and fixing the violations
4. Analysis for DFM
5. Understanding DRC, LVS Errors
Work Experience:
Organization: Aurora’s Technological and Research Institute
Designation: Asst. Professor
Duration of Project in
Months:
Jan 2013 to May 2014
Personal Profile:
Name
: Siva Tanneru
Date of Birth : 12/Dec/1987
Address
: #1239,26th Main ,32 G'Cross near Sudarshan Vidya
Mandir, Jayanagar 4 T Block ,Bangalore – 560041
Father Name : Ramaiah
Nationality : Indian
Sex : Male
Languages known : English, Telugu