1. INDRESH YADAV
Mobile: +91-9033419998/9066881920
Email: yadavindresh@yahoo.com
PROFESSIONAL EXPERIENCE:
3+ Years ofexperience in:
 ASICVerificationexperience that includes development of the Verification Environment, Test
plan definition and development, Test case implementation, Functional Coverage, Code
Coverage and Regression analysis.
 Good knowledge of UVM and OVM methodology.
 Good knowledge in automation using Perl, Python and shell scripting.
 Good Knowledge of Object Oriented Concept & Programming.
 Knowledge of AXI4, eMMC5.0, DDR2 and LPDDR4 protocols.
PROFESSIONAL SKILLS:
Operating Systems Windows, Linux
Programming
Languages
C, C++
Scripting Language Perl, Python, Shell
HDL Language Verilog
HVL System Verilog
HVL Methodology UVM, OVM
EDA Tools Synopsys-VCS, QuestaSim
EXPERIENCE:
 Working as a Verification Engineer at eInfochips Ltd from 1st
May, 2013 to till date.
EXPERIENCE DETAILS:
Project #1
Project Intel Sky Lake and Canon Lake (Onsite Intel Client)
Role Verification Engineer
Duration of Project 11th
May 2015 to till Now
Team Size 6

2. Synopsis
Performance analysis for Graphics architecture
Understood basic level flow of 3D Pipeline
 Pri-Silicon:
 Running regression on emulator.
 Debug waveform to identify bottleneck.
 Post-Silicon:
 Running regression on Platform (Sky Lake) and collect Performance counter stats.
 Debug Performance counter stats to identify bottleneck
 Implemented Python and Perl script to automated debug efforts, Implemented python
based GUI to collect performance counter stats and emulation stats and identify
bottleneck based on stats.
Language and
Tools used
Language: Python, Perl, Shell
Tools: Veloce, Verdi
OS: Unix, Windows
Project #2
Project eMMC5.0 VIP development
Role Verification Engineer
Duration of Project 8th
Oct 2014 to 15th
April 2015
Team Size 4
Synopsis
Development of eMMC5.0 VIP.
 Understood eMMC5.01 specification.
 Prepare test case plan, checkers and verification architecture document for eMMC5.0
 Implemented eMMC5.0 verification environment from scratch, Implemented driver,
monitor and sequences for eMMC5.0
 Implemented test case and checker for eMMC5.0
 Implemented functional coverage for eMMC5.0

3. Language and
Tools used
Language: System Verilog.
Methodology: UVM
Tools: QuestaSim.
OS: Unix, Windows
Project #3
Project LPDDR4 Controller development
Role Verification Engineer
Duration of Project 1st
April 2014 to 30th
Sept 2014
Team Size 4
Synopsis
Development of LPDDR4 Controller.
 Understood LPDDR4 Specification.
 Prepare Test case plan and checkers document for LPDDR4.
 Implemented Test cases and debug test cases for LPDDR4.
 Implemented protocol checkers for LPDDR4.
Language and
Tools used
Language: System Verilog.
Methodology: OVM/UVM
Tools: VCS.
OS: Unix, Windows
Project #4
Project DDR2 test cases and code coverage
Role Verification Engineer
Duration of Project 11th
Feb 2014 to 31st
March 2014
Team Size 2
Synopsis
Implement DDR2 test case to achieve 100% code coverage
 Run regression and generated code coverage report
 Implement test cases to cover missing branch, expression etc for DDR2
 Debug test cases for DDR2.
 Achieved 100% code coverage.

4. Language and
Tools used
Language: System Verilog.
Methodology: OVM
Tools: QuestaSim
OS: Unix, Windows
Project #5
Project AXI 4 VIP development
Role Verification Engineer
Duration of Project 20th
Oct 2013 to 10th
Feb 2014
Team Size 2
Synopsis
Development of AXI4 VIP
 UnderstoodAXI4specification asperRequirement.
 Writingtestplanand checkers forAXI4.
 Implementationof verificationenvironment fromscratch
 Implementationof the Driver,Monitor& Agent componentsforAXI4.
 Implementationof Scoreboard,sequencesandtest casesforAXI4.
Language and
Tools used
Language: System Verilog.
Methodology: UVM
Tools: QuestaSim.
OS: Unix, Windows
Project #6
Project Memory configuration file development
Role Verification Engineer
Duration of project 5th
May 2013 to 10th
Oct 2013
Team Size 5

5. Synopsis
Development of Memory configuration files of DDR3, DDR4, LPDDR2 and LPDDR3 SDRAMs
for different vendors.
 Work to develop Perl script for generation memory configuration files.
 Generated configuration files using PERL script and cross verified generated
configuration files.
Language and
Tools used
Scripting Language: PERL
Tools: Synopsys-VCS
OS: Linux, Windows
TRAINING:
 Professional development course in “VLSI System Design and Verification” from eiTRA
(eInfochips Training and Research Academy), Ahmedabad in 2012-13.
EDUCATIONAL QUALIFICATION:
 Bachelor of Engineering (B.E) in Electronics and Communication from L.C. Institute of
Technology, in 2011.
DECLARATION:
 I hereby declare that the above mentioned information is correct up to my knowledge and
understanding.
INDRESH YADAV