1. SHRUTI NALLA
CAREER OBJECTIVE :
To excel as a VLSI physical design engineer enhancing my skills, experience towards professional growth
with my knowledge, persistence and complete dedication in a sagacious way to achieve organisational goals .
INDUSTRAIL TRAINING :
Trained in VLSI-Physical Design from Institute ofSilicon Systems Pvt.Ltd., Hyderabad from
August, 2015 to January, 2016 using Cadence Tools .
 Experience of working on Physical Design flow from Netlist to GDS II .
 Good understanding on ASIC backend design flow of Floor planning , Power planning , Placement and trail
routing , Clock tree synthesis , block level timing enclosure , Signal integrity analysis , Qualitative R and C
extraction , Static IR drop analysis , Logical Equivalence Check , Physical verification (DRV, LVS ,
Antenna), Static Timing Analysis .
TOOLS :
 SOC Encounter – Floor planning, Power planning, Placement,CTS, Sign-off
Routing .
 Encounter Timing System – Sign-off Timing Closure
 RTL Compiler – Logic Synthesis
 Virtuoso – Layout Designing
 Assura – Physical Verification
PROJECTS :
PROJECT I : Block Level Implementation from Netlist to GDS II in 90nm.
 Gate Count : 296,296
 Cell Count / Macros : 74,074 / 12
 Number of Clocks : 17
 Frequency : 200 MHz
 Metal Layers : 6
 Technology Node : TSMC 90 nm
 Role : Performed Audit Checks,Floor planning, Power planning,
Placement,Trial Route and Congestion Analysis with and without
placement blockage in metal 1 layer , CTS, Detailed Routing and Timing
Closure.
PROJECT II : Chip Top Level Implementation from Netlist to GDS II for aspect ratio
Less than 1 in 45 nm
 Gate Count : 1,074,460
 Cell Count / Macros : 37,654 /2
 Number of Clocks : 6
 Metal Layers : 6
 Technology Node : TSMC 45 nm

2.  Role : Performed Audit Checks, Floor planning, Power planning,
Placement,Trial Route and Congestion Analysis, CTS,
Detailed Routing and Timing Closure ,resolving trans and cap violations .
PROJECT III : Block Level Implementation from Netlist to GDS II in 130nm.
 Gate Count : 128,924
 Cell Count / Macros : 24,462 / 12
 Number of Clocks : 7
 Frequency : 149.9 MHz
 Metal Layers : 6
 Technology Node : TSMC 130 nm
 Role : Performed Audit Checks,Floor planning, Power planning,
Placement,Trial Route and Congestion Analysis, CTS(meeting the skew
target of 100ps), Cap table extraction , Detailed Routing and Timing
Closure.
PROJECT IV : Chip Top Level Implementation from Netlist to GDS II in 180nm .
 Gate Count : 7,701
 Cell Count / Macros : 2,477 / 0
 Number of Clocks : 3
 Frequency : 333.33 MHz
 Metal Layers : 5
 Technology Node : TSMC 180 nm
 Role : Performed Audit Checks,Floor planning, Power planning,
Placement,Trial Route and Congestion Analysis, CTS,
Detailed Routing and Timing Closure.
PROJECT V : 16 Bit Counter Synthesis
 Objectives : Zero Wire Load Model and Wire Load Model Synthesis
 Tools : RTL Compiler
 Gate Count / Area : 87 / 363 um2
 Number of Clocks : 2
 Frequency : 200 MHz
 Technology Node : GF65 nm
 Role : Writing SDC,TCL Scripts, Extracting Area,Timing and
Power Optimized Netlist.
PROJECT VI : 256 Bit Counter Synthesis
 Objective : To run Zero Wire Load Model Synthesis and achieve
maximum Frequency using different VT’s
 Tools : RTL Compiler
 Gate Count / Area : 5954/7621 um2
(RVT), 5307/6793 um2
(HVT),
5903/7556 um2
 Number of Clocks : 1
 Frequency : 523 MHz(RVT), 302 MHz(HVT), 498MHz(MVT)

3.  Technology Node : GF65 nm
 Role : Writing SDC,TCL Scripts, Extracting Area,obtaining maximum frequency
in RVT , HVT , MVT modes and Power Optimized Netlist .
PROJECT VII : Standard Cell Layout Designing
 Tools : Virtuoso XL Editor, Assura Verification
 Cells Designed : Inverter, NAND,NOR,AND,OR,XNOR, XOR, T-Latch
 Technology Node : TSMC 130nm
 Role : Drawing the Layout from the given Spice Netlist and
verifying DRC and LVS clean.
 Challenges : Used only Metal1 layer for routing, maintaining metal pitches
and following half DRC rules.
TECHNICAL SKILLS :
 Programming Languages : Basic c , TCL .
 Tools : Cadence ( SOC Encounter , ETS , RTL
Compiler , Virtuoso , Assura )
 Area of Interest : Backend designing (Synthesis , place
and route , block level timing enclosure, Qualitative R and C
extraction, physical verification , STA )
EDUCATION QUALIFICATION :
Course Board or
University
Name of Institution Year of Passing Percentage
B . Tech
(E.C.E)
J.N.T.U Hyderabad S.R Engineering college 2011- 2015
Intermediate Board of Intermediate
Education (A.P)
Narayana Junior College 2009 - 2011
S.S.C Board of Secondary
School
Education(A.P)
Vignan High School 2008 - 2009
B. Tech Academic Project :
Title : “LOW POWER PROPELLER LED DISPLAY”
Description:
This project has been designed with an aim to design a LED display with low power and low cost using AVR
studio 4. It comprises of circular display of a string of LEDs which uses a high speed motor and mechanical assembly
of 8-LEDs with ATmega8 microcontroller. LED string mounted on a printed circuit board is duly interfaced to the
microcontroller. An appropriate program using embedded C, while executed drives a pair of single line LEDs in space
multiplexing mode. This displays the message,taking the advantage of persistence of vision of human eye .

4. ACHIEVEMENTS :
 Got prize money for best paper presentation in 2013 technical conference on " Space based solar power
transmission " .
DECLARATION :
I here by declare that the above mentioned information is correct up to my knowledge and I bear the responsibility for
the correctness of the above mentioned particulars.
PLACE : HYDERABAD
yours sincerely,
(SHRUTI )