1. SANGEETHA GOPALAKRISHNAN
No – 7, Maruthamalai Gounder Layout,
Ramakrishnapuram, Ganapathy,
Coimbatore, E-mail:
sangeethag.vlsi@gmail.com
TamilNadu – 641006. Mobile: 7598282035
PROFESSIONAL SUMMARY
I have 1year 5months of experience in the ASIC design flow:
• Sound knowledge in Digital electronics.
• Good understanding of the ASIC design flow.
• Experience in writing RTL models using Verilog HDL.
• Experience in writing Test bench using SystemVerilog.
• Experience in developing Test bench environment in verification methodologies.
• Used industry standard EDA tools for the front-end design and verification.
EDUCATION
• Completed Certified Advanced VLSI Design and Verification course, MAVEN SILICON, India, April 2012.
• B.E in Electronics and Communication Engineering, KARUNYA UNIVERSITY, cleared with 79.90% in 2010.
• H.S.C from C.M.S. Matric & Higher Secondary school, India, cleared with 80% in 2006.
• S.S.L.C from C.M.S. Matric & Higher Secondary school, India, cleared with 77% in 2004.
TECHNICAL SKILLSET
Operating System : Windows 7, VISTA, Ubuntu, MAC OS X 10.04.11
Scripting Language : Perl
HDL : Verilog
HVL : SystemVerilog
Verification Methodology: Coverage Driven Verification and Assertion Based Verification
TB Methodology : OVM and VMM
EDA Tool : VCS, DVE, ModelSim and ISE
Domain : ASIC Design Flow, Digital Design methodologies
Knowledge : RTL Coding, FSM based design, Simulation, Code Coverage, Functional Coverage and
Synthesis
EMPLOYMENT HISTORY
EMULEX COMMUNICATIONS PRIVATE LIMITED., BANGALORE SEPTEMBER 2012 - SEPTEMBER
2013
1) Unified Cache (UC) – Verification
Description: Unified cache is a smaller and faster memory used to store the data structure often used in the host
memory. If requested data is contained in the cache then the request is served by simply reading the
cache. This is called cache hit. If the requested data is not in the cache, the data has to be fetched from its
original location. This is called cache miss. Cache hit will reduce the memory access time and inturn it
helps to improve the overall system performance.
Key Roles and Responsibilities:
• Verified all the registers read and write operation.
• Written testcase to check the functionality of UC such as PAUSE, HOLDOFF and DEBUG.
• Used Microsoft Office Visio tool to draw Verification plan schematic.
2) DMA Engine - Design and Verification
Description: Direct Memory Access (DMA) off-loads the CPU operation and hereby it improves the speed of its
operation. A DMA engine can generate addresses and initiate memory read or write cycle. The DMA
engine increments its internal address until the full block of data is transferred.
Key Roles and Responsibilities:

2. • Developed RTL using Verilog HDL.
• Created test plan and build a block diagram using Microsoft Office Visio.
• Developed VMM test bench and verified the DMA design.
MAVEN SILICON PRIVATE LIMITED., BANGALORE DECEMBER 2011 - APRIL 2012 AND JULY 2012
1) Real Time Clock - Design and Verification
Description: A digital alarm clock with the LCD display format. Separate control signals are there to set/correct the
current time and alarm time.
Key Roles and Responsibilities:
• Implemented the Real Time Clock using Verilog HDL.
• Verified the RTL model using SystemVerilog.
• Generated functional and code coverage for the RTL verification sign-off.
2) Dual Port RAM - Design and Verification
Description: Dual port RAM can write and read the data simultaneously.
Key Roles and Responsibilities:
• Implemented the Dual Port Ram using Verilog HDL.
• Verified the RTL module using SystemVerilog.
• Generated functional and code coverage for the RTL verification sign-off.
3) SPI Master Core – Verification
Description: The Serial Peripheral Interface Controller Core is an interface between a single master device and one or
more slave device. Under serial clock, data is serially shifted between the master and slave device.
Key Roles and Responsibilities:
•Written the verification environment using SystemVerilog.
•Verified the RTL module using SystemVerilog.
•Generated functional and code coverage for the RTL verification sign-off.
4) UART – Verification
Description: The Universal Asynchronous Receiver/Transmitter takes bytes of data and transmits the individual bits in
a sequential fashion. At the destination, a second UART re-assembles the bits into complete bytes. The
start bit signals the receiver that a new character is coming and stop bit signals transmission is completed.
Key Roles and Responsibilities:
•Written the verification environment using SystemVerilog.
•Verified the RTL module using SystemVerilog.
RE F E R E N C E
Available on request.
DE C L A R A T I O N
I hereby declare that all the above information is true to my knowledge.
Place: India
Date : 24-12-2015 (SANGEETHA GOPALAKRISHNAN)