This document contains the resume of Nijanthan T. He has 1.8 years of experience in ASIC verification using UVM. His skills include SystemVerilog, UVM, VCS, Questasim, and AMBA protocols. He has worked on projects verifying AXI slave IP, an AXI4-APB bridge, and an AXI4 subsystem. For each project, he developed testbenches, test cases, coverage models, and assertions. He has a Bachelor's degree in Engineering from SBM College of Engineering and Technology.

1. NIJANTHAN
nijanthant91@gmail.com
Phone: +91-9620990318
PROFESSIONAL EXPERIENCE:
1.8 years of experience in:
 AXI Slave verification.
 Experience in Verification using Universal verification Methodology.
 Experience in Verification of AXI2APB Bridge.
 Experience in Assertion checker for APB Slave.
 Experience in Code coverage analysis.
 Experience in function coverage model creation.
PROFESSIONAL SKILLS:
Simulators VCS, ModelSim
Verification Languages System Verilog
Verification
Methodologies
Universal Verification Methodology
HDLs Verilog
Protocols AMBA (AXI, APB) and SPI
Simulators VCS, Questasim
Scripts TCL
EXPERIENCE:
 Working as ASIC Verification Engineer at Orange semiconductor PVT LTD,
Bangalore, from January 2014 to till date.
EDUCATIONAL QUALIFICATION:
 Bachelor of Engineering from SBM college of Engineering and Technology (Anna
University) in 2013.

2. PROJECT DETAILS:
Project #1:
Project Verification of AXI 4 slave DUT using UVM
Technology AMBA 4
Role Team member
Team Size 4
Synopsis
 In this Project AXI master is Verification component and AXI slave is DUT.
 My responsibility is understood functionality of AXI protocol.
 Developed monitor and scoreboard for this AXI Master environment.
 Analyzed remaining AXI environment component in UVM.
 Developed test plan and test cases for AXI master.
 Developed coverage model for AXI master.
Languages &tools
used
System Verilog, UVM and Questasim
Project #2:
Project AXI4_APB bridge verification using UVM
Technology AMBA
Role Team member
Team Size 4
Synopsis
 Axi4 to APB bridge DUT has one AXI4 slave, APB master and AXI4 to APB
converter.
 Understood AXI4 lite and APB protocol.
 Analyzed environment component which has AXI 4 lite master and APB slave in
UVM.
 Developed virtual sequence and test cases for APB slave.
 Developed coverage model for APB Slave.
 Developed SV assertion for APB slave.
Languages &tools
used
System Verilog, UVM and Questasim

3. Project #3:
Project AXI 4 lite -SUB SYSTEM LEVEL VERIFICATION
Technology AMBA 4 th generation
Role Team Member
Team Size 3
Description
The AXI Subsystem DUT includes AXI2APB Bridge, APB slave, SPI Master, ADC
and DAC blocks. It involves the communication between high performance AMBA AXI
and peripherals like ADC, DAC and SPI.
My responsibility was verifying ADC model which is part of sub-system level.
Synopsis
 Understood ADC specification.
 Developed ADC component for this Verification environment.
 Developed test plan and test-cases for ADC bock in UVM.
 Developed SV assertions for ADC.
 Developed RAL model manually for ADC.
 Involved in regression run using TCL scripts.
 Analyzed code coverage for this DUT and developed functional coverage model for
ADC block.
Language & tools
used
Universal Verification Methodology(UVM), Questasim
PERSONAL DETAILS:
Name : Nijanthan T
Gender : Male
Date of Birth : 24-5-1991
Declaration:
I hereby declare that the information furnished above is true to the best of my knowledge.
Bangalore NIJANTHAN T