Rahul Ramani has over 3 years of experience in functional verification of ASICs and FPGAs using SystemVerilog and OVM methodologies. He has worked on projects involving DAL level-A components for avionics and has experience developing testbenches, achieving code and functional coverage, and verifying protocols like Serial RapidIO. Rahul is skilled in Verilog, VHDL, SystemVerilog, OVM, and scripting languages like Perl. He has experience with verification tools like QuestaSim and debugging tools like Modelsim. Rahul has also worked on verification projects involving DO-254 standards where he created compliance documents and reviewed verification artifacts.

1. Rahul Ramani
Verification Engineer, eInfochips, Ahmedabad
Email : rahul.ramani6@gmail.com
Contact : +919726900396
PROFESSIONAL EXPERIENCE:
 3.2+ year experience on functional verification of ASIC and FPGA using system verilog and OVM
methodology.
 Worked in project execution with DAL level-A, which is used for avionics products.
 Experience of worked in different phase of projects like test plan development, test bench development
and achieving 100% code and functional projects.
 Experience in development of OVM verification components, assertions and functional coverage.
 Experience in protocol like Serial Repid IO, NAND controller, ARINC 429 transmitter/receiver, SPI (Serial
Peripheral Interface), McBSP (Multichannel Buffered Serial Protocol), MMC (Multimedia Card).
 Having knowledge of project execution with DO-254 standards.
 Familiar with AS9100C related processes for project execution.
 Experience in development of Hardware Verification test procedures in ETSI tool.
 Worked with HDL languages like Verilog and VHDL for reference model development.
 Having working knowledge of perl scripting and makefile.
SKILLS:
HDL Language VERILOG, VHDL
HVL language System Verilog
Methodologies OVM
Scripting languages PERL basics
Version Control tools SVN
EDA Tools Questasim, ISE
Debugging tools ModelSim
DO-254 process applicable tools
PREP (Peer Review Eclipse Plug-in), DOORS, ALM, JAMA and Clear
quest
AVIONICS DEVICE VERIFICATION BACKGROUND:
 Experience in creating DO-256 compliance verification phase documents like Verification Case Document
(VCD), Verification Phase Document (VPD) and Verification Result Document (VRD) in DOORs and JAMA
tools.
 Worked in review of HRD, VCD, VPD and VRD documents.
 Knowledge of Hardware Design Life Cycle Process.
 Knowledge of Configuration Management .

2. PROJECTS:
PROJECT #1
Project Title GNSS FPGA Verification
Description Global Navigation Satellite System is used for satellite tracking using
complex mixing of input signals and carrier tracking. FPGA having
interface like ARINC-429, SPI, ADC, MMC and McBSP.
Role  Responsible for test plan development from customer requirements.
 Development of MMC (Multimedia Card) OVC.
 Development of McBSP data comparator for scorebording.
 Functional coverage implementation.
 Development of test procedure and failure debug.
 Managing documents for AS9100C process.
 Functional coverage analysis.
 Regression result analysis and bug report/failure debug.
 Code coverage analysis.
Team Size 2
Tools Used QuestaSim10.1b, SVN, DOORS, PREP, ALM
Language OVM
PROJECT #2
Project Title Verification of Serial RapidIO
Description Verification of sRIO Xilinx IP as a part of 737-Max program with DO-
254 standard. SRIO is layered based protocol for serial transmission
and reception of data.
Role  Responsible for test plan documentation and development of test
cases.
 Add support for different error injection in driver and handle other
components to support for normal transactions.
 Test failure debugging.
 Filed 10+ bugs and reported 16+ discrepancies of Xilinx IP with
Standard protocol.
 Random test case development.
 Functional and code coverage analysis.
 Regression Analysis.
 Reviewed test cases vs. test plan, test results against test Plan, test
cases against requirement mapping and traceability.
Technology FPGA
Team Size 5
Tools Used QuestaSim10.2c, SVN, CVS, DOORS, PREP, ALM
Language OVM
PROJECT #3
Project Title ONFI NAND Controller FPGA
Description Development of Hardware test procedure and PREP review activity of
Verification code and DOORs module artifacts as per DO-254
compliance.
Role  Review of DOORs artifacts and Verification code in OVM on PREP
tool.
 Development of prototype test cases with ETSI Tool for hardware
verification.
 Documentation of test results of hardware verification.

3. Technology FPGA
Team Size 2
Tools Used DOORS, PREP, Clear quest, ETSI
Language Prototype testing
PROJECT #4
Project Title ARINC 429 Transmitter and Receiver VIP Model
Description Development of ARINC 429 Transmitter and receiver model for
transmission of 32 bit word over two wire twisted pairs using bipolar
RZ format.
Role  Development of Transmitter and receiver model in Verilog.
 Verification of Tx/Rx model with basic Test scenarios.
 Test plan development.
Team Size 1
Tools Used Questa sim
Language Verilog
PROJECT #5
Project Title VE development of AMBA AHB Lite
Description Development of verification environment of AMBA AHB bus protocol.
Role  Development of verification component (Driver, monitor,
scoreboard) around simple AHB bus model.
 Test plan development.
Team Size 1
Tools Used Questa sim, VCS
Language System Verilog
MAJOR ACHIVEMENTS:
 Awarded with “Core value – On Time Delivery” award 2 times from eInfochips.
 Awarded with “Path-On-Back” award for development of test plan for SRIO protocol.
 Filed 10+ bugs while verification of Xilinx SRIO IP.
 Filed 30+ bugs while verification of GNSS FPGA.
 Participated and successfully completed AS9100C audit for GNSS FPGA project.
ACADEMIC QUALIFICATION:
 Completed B.Tech in Electronics and Communication from Ganpat University in the year 2012.
PERSONAL DETAILS:
Full Name : Rahul Chhaganbhai Ramani
Date of Birth : 28th April 1991
Marital Status : Unmarried
Hobbies : Spent time with friends and family, listening music