1. Vamsi Kumar Paidi
+91-9164500562vamsipaidi@gmail.com 
Career Objective Core Competencies
Dedicated and disciplined VLSI Design and Verification
professional, seeking the position of VLSI Design and
ASIC Verification Engineer, to contribute to the
company's growth and in turn ensuring personal growth
within the organization. I believe that my technical,
functional and communication skills will enable me in
facing the challenging career ahead.
 Verilog, SystemVerilog, VHDL, SystemVerilog
Assertions, UVM
 ASIC/FPGA Design Flow, Digital Design
methodologies, test and checker plan
development
 RTL Coding, FSM based design, Simulation,
Synthesis
 Perforce & Code Collaborator
 Code Coverage, Functional Coverage
 Debugging Skills
 Analytical & Interpersonal Skills
 Quantitative Research and Problem-Solving
Skills
Professional Experience
Verification Engineer
Perfect VIPs Techno Solutions Pvt Ltd, Bangalore
From Nov. 2014 to Present
Intern Engineer(Silicatech)
Perfect VIPs Techno Solutions Pvt Ltd, Bangalore
From Oct. 2013 to Oct. 2014
Education
Year Degree Institute University
2010-2012 M.Tech in VLSI Design Gitam Institute of Technology,
GITAM
University.
2005-2009
B.Tech. in Electronics &
Communication Engg.
Saint Theressa Engineering
Coleege,
JNTU kakinada,
Andrapradesh.
Career Summary
Results-Focused professional offering an experience of 2.6 years in the Front End VLSI & ASIC Design and
Verification. Possessing excellent analytical skills summed up with proficiency in Verilog, SystemVerilog,
SystemVerilog Assertions, Coverage Driven Verification, Assertion Based Verification, Testbench Methodology
(UVM) and test plan development. Practical exposure of working in various phases of Verification IP
development. Hands-on expertise of working on Test Plan, Testbench development, RTL Coding, Simulation,
Synthesis, Debugging, Perforce, Code Collaborator, running regressions, Writing Testcase, Writing Checker Plan
and Checks, EDA Tools and Testbench Methodology (UVM).
Innovative and exceptionally creative to foster ideas that impel the organization towards a result-oriented
direction. Impeccable Client Management and leadership skills with impressive professional-speaking abilities.
Driven by new challenges and adept at adapting to any cultural and business environments.

2. Major Projects Handled
Industrial Experience:
Project: Verification of SATA 3.2Environment using UVM as Verification Engineer at Synopsys Client. (Nov 2014-
March -2016)
Responsibilities:
• Development of test plan for Physical Layer
• Added Sequences and tests according to test plan for Host VIP – Device VIP Configuration And Host DUT –
Device VIP Configuration
• Development of error scenarios test cases.
• Developed tests for Application Layer According to the test plan in Both the Configurations.
• Regression support and primary verification debug
• Debugging and Reporting of failed tests in Regression
• Listed out the uncovered bins And added tests to improve the Coverage Percentage
• Coverage Report analysis and added additional Bins
• Generation of combined coverage report from regression result.
Project: Verification of APB 3.0 Environment using UVM as An Verification Trainee. (Feb 2015-Oct 2015)
Responsibilities:
• Study of APB 3 protocol specification.
• Development of test cases according to test-plan.
• Creation of test-plan development and test-cases
• Coverage implementation for the features to be verified
• Regression support and primary verification debug
• Coverage analysis and closure by adding test cases for uncovered functionality or code and by adding
exclusions.
• Debugging of regression failures.
• Listed out the uncovered bins And added tests to improve the Coverage Percentage
• Implementation of test-cases as per Cover-points.
• Generation of combined coverage report from regression result.
Technical Skills
Category Software/Tool/Technology Proficiency
Operating Systems Linux, Windows Proficient
HDLs Verilog, VHDL Proficient
HVL SystemVerilog Proficient
Verification Methodology Coverage Driven Verification Proficient
TB Methodology UVM Proficient
EDA Tools Xilinx, Modelsim, VCS, NCsim Proficient
Achievement & Publications
Publications:
• Published Journal paper in IJERA ”Boost up the Bus Speed Codec Advanced Mitigation for On-Chip crosstalk
Control (BBS-CAM)” in “International Journal of Engineering Research and Application”.Vol-2 ,Issue3,
Manuscript Entitled ID:220330,May-june 2012.

3. • Presented National Level Conference Paper on “Optimal Numeral Codec Design Advanced Method for
crosstalk Elimination” in ACNCN12 IN ANDHRA UNIVERSITY (March 17-18, 2012).
• Presented National Level Conference Paper on “SPEED UP THE BUS BOOSTER” in NCACT12 IN GITAM
UNIVERSITY (JAN 9-10, 2012).
Personal Details
Marital Status Single
Languages Known English, Hindi, Telugu
Contact Address #164, C/O Ganesh industries, Near sadasraya charitable trust, Shantipura,
Hoskur (post), E-city-I, Bangalore, Karnataka. Pin:560099.
Declaration
I hereby declare that the above information and particulars are true and correct to the best of my personal
knowledge and belief.
Date:
Place: Bangalore VAMSI KUMAR PAIDI