This document contains the resume of Tarun Makwana, including his professional experience, skills, and details of various projects he has worked on. It summarizes his over 10 years of experience in ASIC/FPGA design including digital design, RTL coding, simulation and verification. It lists several projects he led or contributed to related to developing IPs for storage protocols and embedded systems.

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TARUN MAKWANA
M : 9429534868
e-mail : tarun4682@gmail.com
PROFESSIONAL EXPERIENCE:
 Having 10+ years of cumulative experience in ASIC/FPGA based design development
 9+ years of relevant experience in the field of VLSI.
 Digital Design, Micro-Architecture, RTL coding/Integration, Simulation, Timing closure, Linting, ECO
fixes for ASIC Designs
 ASIC IP design, derivative development and sustenance of next generation nonvolatile flash
storage protocol - Universal Flash Storage (UFS) Host Controller from version 1.0 to 2.1
 Micro-Architectural design, RTL Design, and optimization of 128-bit AES-ECB Data
Encryption/Decryption algorithm and integration in UFSHCI IP as an inline crypto engine
 Micro-Architectural design, RTL Design and FPGA Synthesis of Deflate algorithm (RFC 1951)
based Data Compression IP
 Logic Equivalence Check (formal verification) on modem SoC – beginners level
 Design and Validation of Video processing blocks for Object Detection
 Products Development for Industrial Automation and Robotics applications
 FPGA and Micro-controller based low cost Embedded project/product development
PROFESSIONAL SKILLS:
Operating Systems Windows XP, Linux
Programming
Languages
C, 8085/86/51 Assembly
HDL Language Verilog
EDA Tools
Cadence LEC Conformal, Atrenta Spyglass 4.3.5, NC-Verilog, NC
Simulator, VCS, ModelSim, Quartus II, Xilinx ISE and Vivado Series,
Synthesis, PAR, Timing closure and debugging tools from Xilinx and
Altera.
FPGA Technology Xilinx Spartan-3, Virtex-5, Zynq-7, Altera Arria II GX
EXPERIENCE:
 Working as Sr. Technical Leader at eInfochips LTD, Ahmedabad, from April 2015 to till date
 Working as Technical Leader at eInfochips LTD, Ahmedabad, from May 2013 to March 2015
 Working as Senior Engineer at eInfochips LTD, Ahmedabad, from May 2011 to April 2013
 Working as ASIC Engineer at eInfochips LTD, Ahmedabad, from July 2010 to April 2011
 As Project Consultant at Quasar Design Labs LTD, Ahmedabad, from July 2009 to July 2010
 As Project Leader at GlobalTech India Pvt Ltd, Ahmedabad, from April 2008 to June 2009
 As Project Engineer at Wipro Technologies, Pune, from November 2006 to March 2008
 As Design Engineer at GlobalTech India Pvt Ltd, Ahmedabad, from October 2005 to November
2006

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EXPERIENCE DETAILS:
Project #1
Project UFSHCI 2.1 (Universal Flash Storage Host Controller Interface) IP design
Technology MIPI UniPro, Non volatile Storage, Verilog, DVE, Spyglass, LEDA, AES-ECB
128 bit Data Encryption
Role Team Leader
Team Size 3
Duration 8 Months – In progress
Synopsis
 The project task was to migrate JEDEC standard UFSHCI 2.0 to its next verion 2.1 which
includes system level feature addition like AES Data Encryption, IP-XACT model for
MMIO registers, Error Injection feature, support MIPI MPHY HSG-4 throughput
requirement inside Host Controller IP, study of IO Virtualization etc.
 Review of AES ECG 128 bit data encryption and decryption engine architecture and RTL
 Area optimization analysis and implementation efforts for AES
 Integration of AES in UFS Host Controller IP
 Performance analysis of Host Controller IP with AES integration
 Performance analysis of Host Controller IP with MIPI MPHY High Speed Gear 4
integration
 Review of AXI ID implementation in AXI4 master module
 Study of IO virtualization in Host Controller IP and effort estimations
 Overall project management, team management, weekly status report generation and
handling status meetings with client
Project #2
Project UFSHCI 2.0 (Universal Flash Storage Host Controller Interface) IP design
Technology MIPI UniPro, Non volatile Storage, Verilog, DVE, Spyglass, LEDA
Role Team Leader
Team Size 3
Duration 15 Months
Synopsis
 The project task was to migrate JEDEC standard UFSHCI 1.1 to its next verion 2.0 which
includes system level feature addition like Auto Hibernation of MIPI Unipro Link, DMA
ON/OFF capability, Clock gating, configurability of certain registers in debug mode,
Optimization of DMA to deliver higher throughput
 Microarchitecture modification for optimization and configurability in system memory all
DMAs
 Power optimization by restructuring internal memories. Separating one large width
memory into multiple of smaller width memories.
 Architecture and RTL modification of complete IP to adapt Auto Hibernation and clock
gating feature
 Timing closure by register duplication for fanout improvement, breaking combinational,
and redefining place of Flip-Flop in long combo paths
 ASIC variants created to extend the vendor specific on chip debug features e.g. throttling
of packets, trace ports, on the fly altering packet headers etc.
 FPGA Debug support to UFS Driver development team
 Quickly adapted changes of MIPI UniPro RTL from version 1.4 to version 1.6
 Coverage exclusion analysis and documentation
 Maintaining 5 different databases with different feature requirements by end customer
and keeping them all in sync for RTL changes in common area
 Extended support to end customer for query resolution, customization requirement and
ECO(Engineering Change Order) fixes requests.
 Linting check of complete design using spyglass and LEDA tool
 Overall project management, team management, weekly status report generation and
handling status meetings with client

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Project #3
Project UFSHCI (Universal Flash Storage Host Controller Interface) Unified
Memory Architecture IP design - support for more DMAs and 128 bit data
bus
Technology Non volatile Storage, Verilog, DVE, Spyglass
Role Team Member
Team Size 3
Duration 6 Months
Synopsis
 The project task was to add new DMA’s in host controller to enable the system to
incorporate cache of the end device into the system memory
 This results in to a cost effective solution of UFS Device
 Microarchitecture and RTL design of system memory write DMAs
 RTL changes to implement shared memory or Unified Memory Architecture
 RTL changes in system memory write DMAs to be configurable data width up to 128 bit
with all possible unaligned accesses
 Coverage exclusion analysis and documentation
 Linting check of complete design using spyglass tool
 Maintaining 5 different databases with different feature requirements by end customer
and keeping them all in sync for RTL changes in common area
 Weekly status report generation
Project #4
Project UFSHCI (Universal Flash Storage Host Controller Interface) IP design
support for AXI Interface and 64 bit address mode
Technology Non volatile Storage, Verilog, AXI 4 Interface, DVE, Spyglass
Role Team Member
Team Size 3
Duration 6 Months
Synopsis
 The project task was to add new features to support vendor’s specific requirement on
JEDEC standard UFSHCI 1.1 design
 Worked on agile mode of methodology where we need to work on quick specification
changes and requirements with limited processes to help client in system evolution while
implementation of IP
 Microarchitecture and RTL design of Generic AXI Master Read and Write logic to support
N number of clients
 Microarchitecture and RTL design of Generic native interface priority arbier with
 Architectural and RTL changes in top level design to choose between AXI Master and
OCP initiator system bus with synthesizable macro
 RTL changes in system memory write DMA to adapt 64 bit addressing mode including
unaligned transfers
 Module level verification for AXI modules and system memory write DMA
 Coverage exclusion analysis and documentation
 Involved in linting check of complete design using spyglass tool
 Weekly status report generation

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Project #5
Project UFSHCI (Universal Flash Storage Host Controller Interface) IP design
Technology Verilog, OCP (Open Core Protocol) Interface, DVE, Spyglass
Role Team Member
Team Size 4
Duration 4 Months
Synopsis
 The project task was to add new features to upgrade UFSHCI design from version 1.0 to
version 1.1 by JEDEC
 Architectural and RTL changes in OCP initiator module to handle parallel data transfer of
read and write commands in order to support Non-Posted Write transfers
 Architectural and RTL changes in arbiter logic to support read and write transfer in
parallel to clients who gets access of OCP bus
 Addition of Error handling logic to detect various signal and field errors in the packets
coming from Device over Uni-Pro protocol
 Coverage exclusion analysis and documentation
 Maintenance and support activity after project completion
 Involved in linting check of complete design using spyglass tool
Project #6
Project Design of Data Compression IP based on Deflate algorithm (RFC 1951)
Technology Non volatile Storage, Verilog, Quartus II 11.1,Stratix IV GX230, ncsim
Role Team Member
Team Size 6
Duration 6 Months
Synopsis
 This Data Compression IP is used to compress text file using a variance of LZ77
(Lempel-Ziv 1977) and Huffman encoding. Compressed data can be easily
decompressed by using industry standard GZIP software.
 Involved in designing of System level block diagram of complete IP.
 Designed RTL for generation of dynamic Huffman tree codes and code lengths, Hash
Computation and Long match block and bit packing logic in Verilog with assertions.
 Synthesized design on Quartus 11.1.
 Involved in debugging of overall design IP.
Project #7
Project Logic Equivalence Check on modem SoC (ARX CHIP)
Technology Networking
Role Team Member
Team size 2
Duration 1 Month
Synopsis
 Formal verification using Cadence Conformal for a network chip having various IPs and
user modules in Verilog, VHDL, Schematics and pre-synthesized netlist formats.
 Debugging Module level equivalence
 Writing scripts for module level LEC checks (TC2).
 Read, elaborate, mapping, compare and debugging of upper and lower snake modules in
the chip.
 Modifications in the environment for changes in effort level in compare stages, reducing
the run times (TC3).
 Options for solving non-eq points are given to customer.
Language and
tools used
Verilog, VHDL, TCL
Cadence Conformal Ultra 10.1-s480.

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Project #8
Project Motion Detection
Technology Video Processing
Role Team Member
Team size 4
Duration 6 Months
Synopsis
 Functional RTL Designing.
 Architecture and RTL design of various image processing and buffering blocks.
 DDR2 SDRAM interface generation and validation on FPGA board.
 Optimization in Block RAM utilization in Image buffer.
 RTL Design, Synthesis, Place and route, timing closure and Board bring up of the IP on
Xilinx FPGA
Language and
tools used
Verilog
Xilinx ISE 10.1.03, Xilinx XST, Xilinx Timing Analyzer, MIG 2V3.
Project #9
Project Data Acquisition and Control System (DACS)
Technology Data Acquisition and Control System
Role Team Lead
Team Size 3
Duration 3 Month
Synopsis
 Data Acquisition and Control System (DACS) is a Mechatronics system which is used for
laser making on raw diamond with on board FPGA, high speed ADC/DAC, ZBT SRAM
and Micro-controllers.
 Actively Involved in Designing, Verification and successfully implementation DACS into
the Xilinx Spartan-3 FPGA.
 Also involved in Device selection, schematic entry, board bring up and on-site testing.
 Micro architecture and RTL of Slave FIFO Interface, SRAM Interface and FSM modules
and its module level verification.
 Involved in Integration of the entire design and implementation on Spartan-3 FPGA.
 Involved in debugging with ChipScope Pro for board testing.
Language and
tools used
Verilog
Xilinx ISE 9.2i for synthesis and PAR, ModelSim.
Project #10
Project Process Automation Line (PAL)
Technology Robotics
Role Team Member
Team Size 2
Duration 6 Month
Synopsis
 PAL is the solution for robotic application used in PCB manufacturing plants
 The complete system contained FPGA, Micro controllers, EEPROM, and signal
conditioning circuitry
 Involved in implementing design using Verilog RTL for Feedback Control module
 Involved in tailoring and integration of SPI interface for EEPROM interface.
Language and
tools used
Verilog
Xilinx ISE 9.2i for synthesis and PAR, ModelSim.

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Project #11
Project Sensor Deployment System.
Technology Industrial Automation
Role Team Member
Team Size 2
Duration 3 Month
Synopsis
 Sensor Deployment System is an automated system used to deploy hundreds of sensors
into a reaction chamber with predefined vertical profile
 Developed the RTL and Implementation on multiple Spartan-3 based board
 Involved in RTL code for inter FPGA SPI communication, Control logic and UART
interface
 Implemented and validated the design on Hardware
 Created Verification environment using Verilog and verified design using the ModelSim
Language and
tools used
Verilog
Xilinx ISE 9.2i for synthesis and PAR, ModelSim.
Project #12
Project ProSys Board Development.
Technology Data Acquisition and Control
Role Team Member
Team Size 1
Duration 8 Month
Synopsis
 A multipurpose development board with ADC/DAC, SRAM, USER I/O, MCU interface, on
board USB 2.0, TCP/IP 10B, UART capabilities..
 Design and Verification of the Example RTL codes for each Interface.
 Developed test plan and wrote testcases.
Language and
tools used
Verilog
Xilinx ISE 9.2i for synthesis and PAR, ModelSim.
Project #13
Project Static Memory Controller Modeling and Verification
Technology SMC
Role Team Member
Team Size 3
Duration 3 Month
Synopsis
 Involved in testcases development with C
 Generation of timing accurate transactions with “ModelTester” test scripts
 Involved in regression testing and Report generation
Language and
tools used
C
Comet 6.0
EDUCTIONAL QUALIFICATION:
 Master of Technology (Embedded Electronic Systems, V.N.I.T. Nagpur, Visvesvaraya National
Institute of Technology,2005)
 Bachelor of Engineering in (Electronics and Communication Engineering, S.V.I.T. Vasad, Gujarat
University, 2003)