Vanshlata is a project associate with over 3 years of experience in VLSI design and verification. She has expertise in digital design, verification methodologies like UVM, and tools like Questasim and Xilinx. She has worked on projects involving ASIC/FPGA design, SOC verification, and protocol verification. Her experience includes developing verification environments, testbenches, test cases, and functional coverage for designs like radar seekers and accelerometer systems. She has a post-graduate diploma in ASIC design and verification and has cleared the GATE exam multiple times.

1. VANSHLATA
CURRENT LOCATION : GACHIBOWLI, HYDERABAD
CONTACT : +91 9642170322
E-mail : vanshlata@gmail.com
OBJECTIVE
Seeking to work in a professionally stimulating environment, learn new skills and
technologies in ASIC/FPGA Design & Verification and to enhance leadership skills by
embracing greater responsibilities.
AN OVERVIEW
 Around 3.3 years of experience in VLSI in the areas of Design, SoC
Verification, Testbench development using Verilog, VHDL and System
Verilog.
 Good understanding and programming skills in Verification methodologies
(UVM).
 Strong understanding of Digital design concepts and Verification flows
 Hands on experience with EDA tools (Questasim, Xilinx, Synopsys VCS).
 Development of verification components like Scoreboard, Drivers, Monitors using
System Verilog.
 Developing test-cases & achieving defined functional coverage for RTL sign-of
 Familiarity with protocols like AXI, AHB, USB, SPI, I2C, UART, MIL1553B
 Adept in end-to-end development of projects from requirement analysis to
system study, designing, simulation, synthesis, documentation and
implementation.
 Delivered training on Verilog, System Verilog & UVM to the project interns of our
company.
 Good analytical and problem solving along with communication and
interpersonal skills.
WORK EXPERIENCE/PROJECTS
 COMPANY NAME : CDAC, Hyderabad (under DeITy)
PERIOD : SEPTEMBER, 2015 - PRESENT
DESIGNATION : PROJECT ASSOCIATE
 Verification of X – Band RADAR Seeker System (Client Location –
RCI, Hyderabad)
 Description : A RADAR Seeker is a system that assists the missile OBC in
target searching, acquisition and tracking in the supported range. It has four
channels which provide with the range and acceleration of the target based on
Doppler shift measurements and further signal processing done by Tiger
SHARC processors.
 Responsibilities: Designing a MATLAB model to process the received signals
as in the DUV, Create Verification environment for Azimuth Channel and Guard
Channel using UVM, Functional Coverage
 Tools : Xilinx ISE 14.1 with Virtex -6, Questasim, MATLAB R2015
 Language : VHDL, System Verilog with UVM, Tcl
 Verification of ACCDC (Client Location – RCI, Hyderabad )

2.  Description : ACCDC stands for Accelerometer Digitizer Card. As a
subsystem, the card collects temperature, acceleration and gyro data from
sensors, digitises them and sends them over to the OBC. Temperature data is
transferred over I2C extended protocol, acceleration data over SPI protocol and
Gyro data over UART protocol. The OBC interface is also UART.
 Responsibilities: Designing Block level Verification environment for SPI
interface, Integration into and designing Subsystem level verification
environment
 Tools : Xilinx ISE 14.1 with SPARTAN -3ADSP, Questasim
 Language : VHDL, System Verilog, Tcl
 COMPANY NAME : RELIABLE TECHNOSYSTEMS INDIA PVT. LTD.
PERIOD : MAY, 2014 – SEPTEMBER, 2015
DESIGNATION : RTL DESIGN AND VERIFICATION ENGINEER
 Verification of AHB Lite
 Responsibilities:
 Created Test Plan, Functional Coverage specifications.
 Developed UVM Verification Environment for the design.
 Defined verification class components.
 Tools : Questasim
 Language : System Verilog, make scripting
 Methodology : UVM
 Verification of SPI
 Responsibilities:
 Developed UVM Verification Environment for the design
 Defined verification class components.
 Created diferent sequence scenarios
 Tools : Questasim
 Language : System Verilog, make scripting
 Methodology : UVM
 Functional Verification of UART
 Responsibilities:
 Developed UVM Based Test Bench.
 Developed test sequences.
 Developed Cover groups and cover points.
 Tools : Questasim
 Language : System Verilog, make scripting
 Methodology : UVM
 Design of MIL-STD-1553B
 Description : This is a military standard protocol that is widely used in
Defence Avionics(large transports, aerial refuellers, and bombers, tactical
fighters, and helicopters) and Submarines for communication between
diferent systems and subsystems.
 Basic components are RT, BC and BM and works in a command
response mode. Each subsystem acts as an RT and a max of 32 RT’s
can be realized, with 31 subsystems at each RT.

3.  Manchester II encoding is used for data transmission through
diferential bus.
 Operation at 1Mz frequency, word length of 20bits, maximum of 12
microsec response time.
 Responsibilities: Designed Clock Recovery, Sync Detection, Manchester
Validation and Data Recovery Modules for Remote Terminal and verified it.
 Tools : Questasim
 Language : Verilog, scripting using bash
 COMPANY NAME : HCL TECHNOLOGIES PVT. LTD.
PERIOD : APRIL, 2013 – April, 2014
DESIGNATION : Junior Engineer
TECHNICAL (IT) SKILLSET
 LANGUAGES :
 Basic scripting techniques using BASH, PERL, MAKE scripting language
 Design and Verification using VHDL, Verilog, System Verilog.
 Methodologies : UVM
 EDA TOOLS :
 SYNOPSYS DVE and VCS for simulation, Design Compiler for synthesis.
 Xilinx(Xilinx ISE 14.1) for Synthesis and Optimization, Vivado basics
 Modelsim (10.1) and Questasim (10.0b) for RTL Coding, Design and Verification in
Verilog and System Verilog
 PLATFORMS : Windows, Linux
ACADEMIC CREDENTIALS AND TRAININGS
 PG Diploma In ASIC Design And Verification (Oct 2012 – March 2013) from NIELIT,
Calicut (formerly known as DOEACC/CEDTI, Establsihed under Ministry of Communications
and Information Technology; Affiliated to University of Calicut)
 B. Tech ECE, 2011, (64.25%) from DVIET, Karnal (Affiliated to Kurukshetra University)
a. PROLIFIC TRAINING INSTITUTE, NOIDA, 7th
Feb-7th
March, 2011 (Winter Training)
Topic / Course : PLC-Allen Bradley, Siemens S7300, Omron, SCADA Interfacing
b. NTPC, BARH, 29th
July-28th
Aug,2009 (Summer Training)
Topic / Course : DDCMIS
 Senior Secondary, 2006, (67.6% ) from K.V. Deeptinagar, Kahalgaon (CBSE)
 Higher Secondary, 2004, (83.4%) from D.A.V. Public School Deeptinagar, Kahalgaon
(CBSE)
ACADEMIC PROJECTS
 MINI PROJECTS AT NIELIT, CALICUT
Period : Oct 2012-March 2013
Project Details :
 Synthesis of 128X8 FIFO, 128x16 BRAM and DPRAM Memory using Xilinx ISE.
 Design of Arbiter, Arithmetic Instruction Processor using Modelsim.
 Verification of Packet Processor using Synopsys VCS, DVE and Design Compiler,
scripting using bash and perl.
 Realization of basic gates and components like flip-flop, multiplexer and adder using
Leonardo Spectrum (for logic synthesis), Pyxis Layout (for layout entry and editing)
and Calibre (for DRC, LVS and physical verification)
 Linting of basic gate codes using Leda.

4. ACHIEVEMENTS
 Cleared GATE 2015 with a percentile of 87.6
 Cleared GATE 2014 with a percentile of 92.06.
 Cleared GATE 2013 with a percentile of 86.75.
 Cleared GATE 2012 with All India Rank of 5374, GATE Score of 482 and percentile of 96.97.
 An All India Rank 100 in 7th NIIT APTITUDE TEST (2011) with a score of 92 and percentile of
99.
 Member of YIA & NIFAA, non-government organizations during college, campaigned for
eradication of female foeticide and 100% voting.
 Rewarded various prizes in various singing, dancing, quiz, speech, elocution & debate
competitions in school and college
PERSONAL DOSSIER
Father’s Name : Sh. Naveen Kumar
Mother’s Name : Smt. Nilam Devi
Date of Birth : 13th December, 1987.
Marital Status : Single
Hobbies : Singing Songs, Reading Books
Language Known : English and Hindi, Understanding of Bangla and Punjabi
I hereby declare that the information given above are true and correct to the best of
my knowledge.
PLACE :
DATE : (VANSHLATA)