Vivek Munivenkatappa is seeking a summer internship as an ASIC Design/Verification engineer. He has an MS in Electrical Engineering from San Jose State University with a GPA of 3.66/4.0 and a B.E in Electronics and Communication from University Visvesvaraya College of Engineering in India with a GPA of 3.96/4.0. He has skills in RTL design, low power design, verification, synthesis, and EDA tools such as Xilinx ISE, Modelsim, and Cadence Virtuoso. For projects, he designed a 32-bit MIPS pipeline processor and optimized a serial filter design. He also has experience as an ETL developer

1. Vivek Munivenkatappa
San Jose, CA 95112
https://www.linkedin.com/pub/vivek-m/29/351/5a5
vivek.munivenkatappa@sjsu.edu
(408)809-6714
OBJECTIVE: Seeking summer internship as ASIC Design/Verification engineer and to grow along company
EDUCATION:
MS Electrical San Jose State University, CA, USA 3.66/4.0 May 2016
B.E Electronics & Comm. University Visvesvaraya College of Engineering, BLR, IN 3.96/4.0 Jul 2013
VLSI Skills: RTL, Low power Design, STA, Functional verification, Synthesis, PNR, Floor-planning, DFT, BIST
Programming Skills: Verilog, VHDL, Perl, C, C++, UNIX and MATLAB
EDA Tools: Xilinx ISE, NC-Verilog, VCS, Design Compiler, Modelsim, Cadence Virtuoso and Encounter
RELATED COURSE WORK: Advanced Computer Architectures, ASIC CMOS design, High speed CMOS circuits,
Advanced Digital system design and Synthesis, and Analog IC Design, Linear System theory
RELEVANT PROJECTS:
32 bit MIPS 5 stage pipeline Microprocessor, San Jose State University Sept 2014 – Dec 2014
 Developed debugging and designing skills by implementation of forwarding and stall detection
 Synthesized the design using Toshiba 250nm cell library in Design Compiler for 250 MHz clock speed
 Learned to systematically verify functionality by analyzing simulations, waveforms and timing in VCS
 Improved verification skills by writing test bench in Verilog that verified working of all instructions
Serial Filter, San Jose State University Feb 2015
 Optimized the single stage serial filter code to synthesize for 250 MHz by pipelining multiply & add
 Learned how to retime the long path and further optimized the code by splitting multiplierto 3 stages
 Synthesized the new code for 300 MHz in Synopsys Design Compiler using TSMC 0.18um cell library
 Visualized the layout, nets, and cells by placing and routing this design in Cadence Encounter
 Understood the Perl synthesis script on how to set library, clock period, input and output delays etc.
Variable Length Parallel to bits converter, San Jose State University Feb 2015
 Solved this critical thinking problem using FIFO, and shift registers, and synthesized for 200 MHz
 This Bolstered my Verilog coding skills, and enabled me to think faster in a time constraint situation
 Analyzed python script given to automate the functional, gate level simulation and synthesis process
Sigma Delta Modulator (SDM), San Jose State University Feb 2015 – Apr 2015
 Analyzing various topologies, to design digital 5th
order SDM
 Modelling the SDM in Simulink to verify stability, cadence 45nm technology will be used in design
Line Following and Obstacle Sensing Robot,University Visvesvaraya College of Engineering Jan– Jun2012
 Designed sensor boards, comparators and motor drive circuits for the robot
 Coded 8051 and Atmega128 microcontrollers in C to realize the line following robot
EXPERIENCE:
Associate System Engineer (ETL Developer), IBM India Pvt Ltd Dec 2013 - Jul 2014
 Gained designing skills by creating new efficient Datastage jobs that suits the client requirements
 Wrote UNIX scripts to automate daily triggering of jobs and to generate log files.
 Improved debugging skills by enhancing performance of legacy projects by converting server jobs to
parallel jobs
ACTIVITIES:
Organizer, Volunteer, University Visvesvaraya College of Engineering Jan 2010 - Jan 2013
 Organized ‘Switch Play’- circuit design contest – improved my circuit concepts by preparing problems
 Volunteer for ‘IMPETUS’ and ‘INSPIRON’ – college events – learned organizational skills