1. MAANEZ SHAH
Contact No: +91 9400475147,8147369007.
Mail ID: maanezshah@gmail.com
Career Objective:
An Electronics engineer professional trained in ASIC RTL Design and
Verification, seeking a challenging career in VLSI, which helps me to enhance
and develop technical knowledge further, to gain experience and contribute my
best to professional environment.
Educational Qualifications:
Course Institution Year of passing Percentage
Post-
Graduation
Diploma in
ASIC Design .
RV-VLSI
Design Center,
Bengaluru .
2016
(March)
Results awaited
B.Tech
(Electronics and
communication).
MGUCE,
Thodupuzha.
2015 65%
Higher
secondary.
CSHSS, Thrissur. 2009 94%
SSLC. KAUHS,
Vellanikkara,
Thrissur
2007 94%

2. Core Competency:
• Strong knowledge in ASIC Design flow and verification concepts.
• Good knowledge in UVM concepts.
• Good knowledge in System Verilog.
• Good knowledge in Verilog 2001.
• EDA Tool – Questasim, Design Compiler, Calibre (Layouts), Cadence
Virtuoso, Xilinx.
• Good knowledge on Functional Coverage, Assertions, Synthesis, STA.
• Hardware Programming Languages - Verilog, Microcontroller 8051,
Microprocessor 8086, VHDL.
• Protocols – SATA, UART.
• Scripting Language – Perl, shell (Makefile).
• Operating Systems – Linux and Windows.
• Good knowledge of logic design concepts( PMOS , CMOS , NMOS
concepts).
• Good knowledge in Vi Editor, UNIX Linux.
• Strong electronics and communication base.
• Confident and presentation skills are very strong and positive approach to
all circumstances.
Project Experience at RV-VLSI Design Center:
1. Serial ATA Protocol Link Layer verification using UVM: Duration: 20 days
Project
Description
SATA(Serial Advanced Technology Attachment) is a serial interface standard
used to control and transfer data from mass storage devices such as hard disk
drives and optical drives. To Verify its functionality using UVM.
Tool used : Questasim.
Project Challenges:
• Understanding the working of Link Layer of protocol which involves
primitives added for proper communication and significance of each
primitive.

3. • Coming up with complete Testbench environment components in UVM
having two active agents, each for Transport and Physical layer.
• Writing the Sequences / Testcases for checking the functionality of link
layer and hitting the corner cases and implementing virtual sequence
and sequencers.
• Rigorous Functional Coverage for the layer with primitive coverpoints
in Scoreboard.
2. FIFO memory verification using UVM: Duration: 5 days
Tools Used Questasim
Project Challenges:
• Creating the UVM environment for the FIFO verification with one active
and a passive agent.
• Code for input and output functional coverage and writing the corner test
cases for read and write operation.
• Finding a bug related to design specific almost empty and almost full
conditions.
3. Single Port RAM verification in SV Duration: 5 days
Tools Used Questasim
Project Challenges:
• Coming up with SV blocks of environment and SV constructs.
• Implementation of input and output functional coverage and constraint
randomization in transaction block and Regression.
4. ALU verification in Verilog Duration: 2 Days
Tools Used Modelsim
Project Challenges:
• Writing the test cases for ALU and mimicking the ALU operations
• Achieve the expected Code Coverage and finding the toggle condition
bugs.

4. • 5. UART- RTL Design using the Verilog 2001. Duration: 2 Days
Tool Used Modelsim
Project Challenges:
• Understanding the UART packets and FSM model implementation.
• Writing the test bench code in Verilog to verify the same.
B.Tech Project
Project Name:
Cell phone controlled robot with obstacle detection.
Institute Name:
MGUCE
Project
Description:
It has been done using Micro controller 8051 . The robotic system is controlled
using the android software installed in users mobile.
Challenges:
To make the commands through voice process and robot to understand, it was
something difficult. Finally we have made the commands for motion also as
1,2,3,4, as forward, backward, right, left respectively and executed.
Tools:
Hardware: micro controller 8051, Bluetooth module, motor driver, motor, lcd
Display, Software: Kiel, C, Java, Flash magic etc.

5. Extra-Curricular Activities:
• I have trained in INDIAN NAVY (At Indian naval academy) as an
officer cadet after clearing NDA exam and SSB interview in 2009.
• Kerala State level Drama First For 2 years in 2007,2008. (Team
caption).
• Thrissur District level mime 2nd
for 2 years in 2007,2008.(Team
caption).
• Sub district level science and mathematic exhibition winner at
2005,2006.
• Directed two short films in the year 2014-2015.
• Excellence in Sports – Cricket, Football, Running, Swimming.
• Excellence in arts- Acting ,Writing, Directing, Dancing, Singing,
Elocution ,Mono act , Mimicry etc.
Personal details:
Father’s Name: Shajy pm.
Languages: English, Malayalam, Hindi.
Address: Puzhakkarayil house,Near DBHSS,Mannuthy
po,Thrissurr,Kerala,India.
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I hereby confirm that the details furnished above are true to the best of my knowledge.