Saida Dharavath is seeking a job where he can utilize his existing skills in VLSI design and verification. He has 8 months of experience as an intern at Maven Silicon where he worked on projects involving router design, bus bridge design, SPI master verification, and AXI protocol verification. He is proficient in Verilog, SystemVerilog, UVM methodology, and tools like Xilinx ISE and Rivera Pro. He holds a B.Tech degree in electronics and has participated in various extracurricular activities and workshops.

1. Saida Dharavath
Cell: +91-8550870721or +91-9014615316
Email:sdharavath05@gmail.com
CAREER OBJECTIVE
ÿ To work in an organization where I can utilize my existing skills and knowledge and develop
new skills to contribute in the accomplishment of organizational goals.
PERSONALITY TRAITS
ÿ Good interpersonal skills, commitment, result-oriented, zeal to learn new technologies and
undertake challenging tasks.
ÿ Excellent team player and possess leadership ability.
ÿ Easy to be settled in each environment.
SUMMARY OF QUALIFICATIONS
ÿ Working as project intern in maven silicon Pvt ltd for past 8 months.
ÿ Good understanding of the ASIC and FPGA design flow.
ÿ Writing RTL models in Verilog HDL and Test benches in System Verilog and UVM.
ÿ Industry standard EDA tools for the front-end design and verification
VLSI DOMAIN SKILLS
¸ HDL : Verilog.
¸ HVL : System Verilog.
¸ Verification Methodologies : Coverage Driven Verification,
Assertion Based Verification – SVA.
¸ TB Methodology : Universal Verification Methodology (UVM).
¸ EDA Tool : Rivera pro and ISE (Xilinx).
¸ Domain : ASIC/FPGA front-end Design and Verification.
¸ Knowledge : RTL Coding, FSM based design, Simulation,
Code Coverage, Functional Coverage, Synthesis,
Static Timing Analysis (CMOS), ABV- SVA.
TECHNICAL SKILLS
¸ Technologies Use: C, Java, Verilog, System Verilog, Perl Scripts.
¸ Methodologies: UVM.
¸ Tools: Xilinx ISE, Questasim, Rivera Pro.
¸ Operating Systems: Windows XP, Linux.
PROFESSIONAL QUALIFICATION
¸ Maven Silicon Certified Advanced VLSI Design and Verification course
From Maven Silicon VLSI Design and Training Center, Bangalore.

2. PROJECT SUMMARY
Project 1 1X3 Router Design
Team size 1
Technologies Used Verilog
Tools used Xilinx ISE
PROJECT OVERVIEW
¸ This project demonstrates the phenomena of packet switching performed by router from source
network to the one of the three destination networks.
KEY RESPONSIBILITIES HANDLED
¸ Understanding the routing protocol of the prototype.
¸ Designing the RTL of the prototype.
¸ Verifying the design using TB and fixing the design bugs.
Project 2 Design of AHB to APB AMBA BUS BRIDGE
Team size 1
Technologies Used Verilog
Tools used Xilinx ISE
PROJECT OVERVIEW
¸ This is the prototype which acts as the mediator between high frequency AHB and low
frequency APB Bus.
KEY RESPONSIBILITIES HANDLED
¸ Designing the RTL of the prototype.
¸ Verifying the design using TB and identifying drawbacks.
Project 3 SPI Master Core Verification
Team size 1
Technologies Used UVM
Tools used Rivera Pro
PROJECT OVERVIEW
¸ The purpose of this prototype is to handle the communication between parallel host and serial
slaves.
KEY RESPONSIBILITIES HANDLED
¸ Understanding the IP protocol.
¸ Designing The TB architecture.
¸ Implementing TB environment and detecting bugs.
¸ Coverage.

3. Project 4 Advanced Extensible Interface (AXI)
Team size 1
Technologies Used UVM
Tools used Rivera Pro
PROJECT OVERVIEW
¸ The purpose of this prototype is to handle the communication between Write side channels,
Read side channels as well as write Response Channel also. This Protocol also supports for
issuing Multiple out Standing addresses and Support for out-of-order transaction completion.
KEY RESPONSIBILITIES HANDLED
¸ Understanding the IP protocol.
¸ Designing The TB architecture.
¸ Implementing TB environment and detecting bugs.
¸ Coverage.
ACADEMIC CREDENTIALS
ÿ B.Tech@Anurag Engineering college Completed in the Year 2015 with 65%
ÿ Diploma @Sana Polytechnic College Completed in the Year 2011 with 70.96%
ÿ SSC @Chaitanya Patashala (T.M&E.M) School Completed in the Year 2008 with 67.5%
EXTRA CURRICULAR ACTIVITIES
ÿ Participated in the state level volleyball competition.
ÿ Participated in district level essay competition.
ÿ Participated in BSNL Workshop Undergone training on “Over view on latest
Telecom Technology”.
CURRENT EXPERIENCE
ÿ 8 Months.
ÿ Trained at Maven Silicon VLSI Training Center (Bangalore).
PERSONAL DETAILS
ÿ Date of Birth : 07-03-1993.
ÿ Gender : Male.
ÿ Languages Known : English, Hindi and Telugu.
ÿ Current Location : Bangalore.
ÿ Permanent Address : Telangana (state), Nalgonda (Dist.), Kodad.
ÿ Interest : Playing volleyball & cricket.
ABOUT ME
ÿ I am punctual, hardworking, self-motivated individual with a Quick learning ability having team
work skills and love to interact with people.
Date: Sincerely,
Place: Saida Dharavath